From a870975352f4ececddabdf76837a04cd9b700599 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 12 Apr 2021 19:02:41 +0530 Subject: [PATCH] bindings: cpufreq-hw: Add support for SDPM CX/MX offset Introduce an optional addresses and sizes for the SDPM memory of the HW bases in each frequency domain, indicated by an "id"(0/1/2). Change-Id: I7762c62176258fe09c94a0b118340b076940955a --- bindings/cpufreq/cpufreq-qcom-hw.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/cpufreq/cpufreq-qcom-hw.txt b/bindings/cpufreq/cpufreq-qcom-hw.txt index 251ea7dcca40..4ece108cbbb0 100644 --- a/bindings/cpufreq/cpufreq-qcom-hw.txt +++ b/bindings/cpufreq/cpufreq-qcom-hw.txt @@ -50,6 +50,12 @@ Properties: should have the "pdmem-domainX" to indicate the corresponding bases. +- qcom,sdpm-cx-mx- + Usage: Optional + Value type: + Definition: Addresses and sizes for the SDPM memory of the HW bases + in each frequency domain, indicated by an "id"(0/1/2). + * Property qcom,freq-domain Devices supporting freq-domain must set their "qcom,freq-domain" property with phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. @@ -181,6 +187,8 @@ DCVS state together. clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; + qcom,sdpm-cx-mx-1 = <0x00636f08 0x4>; + qcom,sdpm-cx-mx-2 = <0x00636f0c 0x4>; #freq-domain-cells = <1>; };