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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Addition of the Exynos3250 SoC's UART2 and MMC2 clocks.
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This commit is contained in:
Krzysztof Kozlowski
commit
a8b41ea4ba
2 changed files with 25 additions and 1 deletions
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@ -302,10 +302,12 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
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/* SRC_FSYS */
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MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
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MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
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MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
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MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
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/* SRC_PERIL0 */
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MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
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MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
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MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
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@ -389,7 +391,13 @@ static struct samsung_div_clock div_clks[] __initdata = {
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CLK_SET_RATE_PARENT, 0),
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DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
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/* DIV_FSYS2 */
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DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
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CLK_SET_RATE_PARENT, 0),
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DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
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/* DIV_PERIL0 */
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DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
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DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
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DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
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@ -538,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
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GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
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GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
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GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
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GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
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@ -552,6 +562,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
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GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
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GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
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GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
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GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
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@ -630,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
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GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
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GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
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GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
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GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
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GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
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GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
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GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
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@ -649,6 +663,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
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GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
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GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
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GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
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GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
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GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
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GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
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};
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@ -79,6 +79,8 @@
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#define CLK_MOUT_CORE 58
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#define CLK_MOUT_APLL 59
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#define CLK_MOUT_ACLK_266_SUB 60
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#define CLK_MOUT_UART2 61
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#define CLK_MOUT_MMC2 62
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/* Dividers */
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#define CLK_DIV_GPL 64
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@ -127,6 +129,9 @@
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#define CLK_DIV_CORE 107
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#define CLK_DIV_HPM 108
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#define CLK_DIV_COPY 109
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#define CLK_DIV_UART2 110
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#define CLK_DIV_MMC2_PRE 111
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#define CLK_DIV_MMC2 112
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/* Gates */
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#define CLK_ASYNC_G3D 128
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@ -223,6 +228,8 @@
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#define CLK_BLOCK_MFC 219
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#define CLK_BLOCK_CAM 220
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#define CLK_SMIES 221
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#define CLK_UART2 222
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#define CLK_SDMMC2 223
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/* Special clocks */
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#define CLK_SCLK_JPEG 224
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@ -249,12 +256,14 @@
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#define CLK_SCLK_SPI0 245
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#define CLK_SCLK_UART1 246
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#define CLK_SCLK_UART0 247
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#define CLK_SCLK_UART2 248
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#define CLK_SCLK_MMC2 249
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/*
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* Total number of clocks of main CMU.
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* NOTE: Must be equal to last clock ID increased by one.
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*/
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#define CLK_NR_CLKS 248
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#define CLK_NR_CLKS 250
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/*
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* CMU DMC
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