diff --git a/arch/arm64/configs/vendor/lahaina_GKI.config b/arch/arm64/configs/vendor/lahaina_GKI.config index 62f0e25852a7..b3c232e67abe 100644 --- a/arch/arm64/configs/vendor/lahaina_GKI.config +++ b/arch/arm64/configs/vendor/lahaina_GKI.config @@ -245,3 +245,4 @@ CONFIG_INTERCONNECT_QCOM_YUPIK=m CONFIG_SM_VIDEOCC_YUPIK=m CONFIG_SM_CAMCC_YUPIK=m CONFIG_QCOM_YUPIK_LLCC=m +CONFIG_SM_DISPCC_YUPIK=m diff --git a/arch/arm64/configs/vendor/lahaina_QGKI.config b/arch/arm64/configs/vendor/lahaina_QGKI.config index ce638be10844..34cd099b90da 100644 --- a/arch/arm64/configs/vendor/lahaina_QGKI.config +++ b/arch/arm64/configs/vendor/lahaina_QGKI.config @@ -257,3 +257,4 @@ CONFIG_QTI_HW_MEMLAT_LOG=y CONFIG_SRAM=y CONFIG_CRYPTO_SHA1_ARM64_CE=y CONFIG_PRINT_SUSPEND_EPOCH_QGKI=y +CONFIG_SM_DEBUGCC_YUPIK=y diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d91f976e61c6..6c6f52d70890 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -665,6 +665,24 @@ config SM_CAMCC_YUPIK Say Y if you want to support camera devices and functionality such as capturing pictures. +config SM_DISPCC_YUPIK + tristate "YUPIK Display Clock Controller" + select SM_GCC_YUPIK + help + Support for the display clock controller on Qualcomm Technologies, Inc. + YUPIK devices. + Say Y if you want to support display devices and functionality such as + splash screen. + +config SM_DEBUGCC_YUPIK + tristate "YUPIK Debug Clock Controller" + depends on SM_GCC_YUPIK + help + Support for the debug clock controller on Qualcomm Technologies, Inc. + YUPIK devices. + Say Y if you want to support the debug clocks such as clock measurement + functionality. + endif config VIRTIO_CLK diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index c3d11d8c92dc..3b1720b33bd0 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -77,9 +77,11 @@ obj-$(CONFIG_SM_CAMCC_YUPIK) += camcc-yupik.o obj-$(CONFIG_SM_DEBUGCC_8150) += debugcc-sm8150.o obj-$(CONFIG_SM_DEBUGCC_HOLI) += debugcc-holi.o obj-$(CONFIG_SM_DEBUGCC_SHIMA) += debugcc-shima.o +obj-$(CONFIG_SM_DEBUGCC_YUPIK) += debugcc-yupik.o obj-$(CONFIG_SM_DISPCC_8150) += dispcc-sm8150.o obj-$(CONFIG_SM_DISPCC_HOLI) += dispcc-holi.o obj-$(CONFIG_SM_DISPCC_SHIMA) += dispcc-shima.o +obj-$(CONFIG_SM_DISPCC_YUPIK) += dispcc-yupik.o obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o obj-$(CONFIG_SM_GCC_HOLI) += gcc-holi.o obj-$(CONFIG_SM_GCC_SHIMA) += gcc-shima.o diff --git a/drivers/clk/qcom/debugcc-yupik.c b/drivers/clk/qcom/debugcc-yupik.c new file mode 100644 index 000000000000..f0400ebbc42d --- /dev/null +++ b/drivers/clk/qcom/debugcc-yupik.c @@ -0,0 +1,1009 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-debug.h" +#include "common.h" + +static struct measure_clk_data debug_mux_priv = { + .ctl_reg = 0x62038, + .status_reg = 0x6203C, + .xo_div4_cbcr = 0x6200C, +}; + +static const char *const apss_cc_debug_mux_parent_names[] = { + "measure_only_apcs_gold_post_acd_clk", + "measure_only_apcs_goldplus_post_acd_clk", + "measure_only_apcs_l3_post_acd_clk", + "measure_only_apcs_silver_post_acd_clk", +}; + +static int apss_cc_debug_mux_sels[] = { + 0x25, /* measure_only_apcs_gold_post_acd_clk */ + 0x61, /* measure_only_apcs_goldplus_post_acd_clk */ + 0x41, /* measure_only_apcs_l3_post_acd_clk */ + 0x21, /* measure_only_apcs_silver_post_acd_clk */ +}; + +static int apss_cc_debug_mux_pre_divs[] = { + 0x8, /* measure_only_apcs_gold_post_acd_clk */ + 0x8, /* measure_only_apcs_goldplus_post_acd_clk */ + 0x4, /* measure_only_apcs_l3_post_acd_clk */ + 0x4, /* measure_only_apcs_silver_post_acd_clk */ +}; + +static struct clk_debug_mux apss_cc_debug_mux = { + .priv = &debug_mux_priv, + .debug_offset = 0x18, + .post_div_offset = 0x18, + .cbcr_offset = 0x0, + .src_sel_mask = 0x7F0, + .src_sel_shift = 4, + .post_div_mask = 0x7800, + .post_div_shift = 11, + .post_div_val = 1, + .mux_sels = apss_cc_debug_mux_sels, + .pre_div_vals = apss_cc_debug_mux_pre_divs, + .hw.init = &(struct clk_init_data){ + .name = "apss_cc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = apss_cc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(apss_cc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const char *const cam_cc_debug_mux_parent_names[] = { + "cam_cc_bps_ahb_clk", + "cam_cc_bps_areg_clk", + "cam_cc_bps_axi_clk", + "cam_cc_bps_clk", + "cam_cc_camnoc_axi_clk", + "cam_cc_camnoc_dcd_xo_clk", + "cam_cc_cci_0_clk", + "cam_cc_cci_1_clk", + "cam_cc_core_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_csi0phytimer_clk", + "cam_cc_csi1phytimer_clk", + "cam_cc_csi2phytimer_clk", + "cam_cc_csi3phytimer_clk", + "cam_cc_csi4phytimer_clk", + "cam_cc_csiphy0_clk", + "cam_cc_csiphy1_clk", + "cam_cc_csiphy2_clk", + "cam_cc_csiphy3_clk", + "cam_cc_csiphy4_clk", + "cam_cc_gdsc_clk", + "cam_cc_icp_ahb_clk", + "cam_cc_icp_clk", + "cam_cc_ife_0_axi_clk", + "cam_cc_ife_0_clk", + "cam_cc_ife_0_cphy_rx_clk", + "cam_cc_ife_0_csid_clk", + "cam_cc_ife_0_dsp_clk", + "cam_cc_ife_1_axi_clk", + "cam_cc_ife_1_clk", + "cam_cc_ife_1_cphy_rx_clk", + "cam_cc_ife_1_csid_clk", + "cam_cc_ife_1_dsp_clk", + "cam_cc_ife_2_axi_clk", + "cam_cc_ife_2_clk", + "cam_cc_ife_2_cphy_rx_clk", + "cam_cc_ife_2_csid_clk", + "cam_cc_ife_2_dsp_clk", + "cam_cc_ife_lite_0_clk", + "cam_cc_ife_lite_0_cphy_rx_clk", + "cam_cc_ife_lite_0_csid_clk", + "cam_cc_ife_lite_1_clk", + "cam_cc_ife_lite_1_cphy_rx_clk", + "cam_cc_ife_lite_1_csid_clk", + "cam_cc_ipe_0_ahb_clk", + "cam_cc_ipe_0_areg_clk", + "cam_cc_ipe_0_axi_clk", + "cam_cc_ipe_0_clk", + "cam_cc_jpeg_clk", + "cam_cc_lrme_clk", + "cam_cc_mclk0_clk", + "cam_cc_mclk1_clk", + "cam_cc_mclk2_clk", + "cam_cc_mclk3_clk", + "cam_cc_mclk4_clk", + "cam_cc_mclk5_clk", + "cam_cc_sleep_clk", +}; + +static int cam_cc_debug_mux_sels[] = { + 0x18, /* cam_cc_bps_ahb_clk */ + 0x17, /* cam_cc_bps_areg_clk */ + 0x16, /* cam_cc_bps_axi_clk */ + 0x14, /* cam_cc_bps_clk */ + 0x3C, /* cam_cc_camnoc_axi_clk */ + 0x3D, /* cam_cc_camnoc_dcd_xo_clk */ + 0x39, /* cam_cc_cci_0_clk */ + 0x3A, /* cam_cc_cci_1_clk */ + 0x40, /* cam_cc_core_ahb_clk */ + 0x3B, /* cam_cc_cpas_ahb_clk */ + 0x8, /* cam_cc_csi0phytimer_clk */ + 0xA, /* cam_cc_csi1phytimer_clk */ + 0xC, /* cam_cc_csi2phytimer_clk */ + 0xE, /* cam_cc_csi3phytimer_clk */ + 0x10, /* cam_cc_csi4phytimer_clk */ + 0x9, /* cam_cc_csiphy0_clk */ + 0xB, /* cam_cc_csiphy1_clk */ + 0xD, /* cam_cc_csiphy2_clk */ + 0xF, /* cam_cc_csiphy3_clk */ + 0x11, /* cam_cc_csiphy4_clk */ + 0x41, /* cam_cc_gdsc_clk */ + 0x36, /* cam_cc_icp_ahb_clk */ + 0x35, /* cam_cc_icp_clk */ + 0x25, /* cam_cc_ife_0_axi_clk */ + 0x1E, /* cam_cc_ife_0_clk */ + 0x24, /* cam_cc_ife_0_cphy_rx_clk */ + 0x22, /* cam_cc_ife_0_csid_clk */ + 0x21, /* cam_cc_ife_0_dsp_clk */ + 0x2D, /* cam_cc_ife_1_axi_clk */ + 0x27, /* cam_cc_ife_1_clk */ + 0x2C, /* cam_cc_ife_1_cphy_rx_clk */ + 0x2B, /* cam_cc_ife_1_csid_clk */ + 0x2A, /* cam_cc_ife_1_dsp_clk */ + 0x53, /* cam_cc_ife_2_axi_clk */ + 0x7, /* cam_cc_ife_2_clk */ + 0x52, /* cam_cc_ife_2_cphy_rx_clk */ + 0x51, /* cam_cc_ife_2_csid_clk */ + 0x26, /* cam_cc_ife_2_dsp_clk */ + 0x2F, /* cam_cc_ife_lite_0_clk */ + 0x31, /* cam_cc_ife_lite_0_cphy_rx_clk */ + 0x30, /* cam_cc_ife_lite_0_csid_clk */ + 0x2E, /* cam_cc_ife_lite_1_clk */ + 0x37, /* cam_cc_ife_lite_1_cphy_rx_clk */ + 0x32, /* cam_cc_ife_lite_1_csid_clk */ + 0x1D, /* cam_cc_ipe_0_ahb_clk */ + 0x1C, /* cam_cc_ipe_0_areg_clk */ + 0x1B, /* cam_cc_ipe_0_axi_clk */ + 0x19, /* cam_cc_ipe_0_clk */ + 0x33, /* cam_cc_jpeg_clk */ + 0x13, /* cam_cc_lrme_clk */ + 0x1, /* cam_cc_mclk0_clk */ + 0x2, /* cam_cc_mclk1_clk */ + 0x3, /* cam_cc_mclk2_clk */ + 0x4, /* cam_cc_mclk3_clk */ + 0x5, /* cam_cc_mclk4_clk */ + 0x6, /* cam_cc_mclk5_clk */ + 0x42, /* cam_cc_sleep_clk */ +}; + +static struct clk_debug_mux cam_cc_debug_mux = { + .priv = &debug_mux_priv, + .debug_offset = 0xD000, + .post_div_offset = 0xD004, + .cbcr_offset = 0xD008, + .src_sel_mask = 0xFF, + .src_sel_shift = 0, + .post_div_mask = 0xF, + .post_div_shift = 0, + .post_div_val = 4, + .mux_sels = cam_cc_debug_mux_sels, + .hw.init = &(struct clk_init_data){ + .name = "cam_cc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = cam_cc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(cam_cc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const char *const disp_cc_debug_mux_parent_names[] = { + "disp_cc_mdss_ahb_clk", + "disp_cc_mdss_byte0_clk", + "disp_cc_mdss_byte0_intf_clk", + "disp_cc_mdss_dp_aux_clk", + "disp_cc_mdss_dp_crypto_clk", + "disp_cc_mdss_dp_link_clk", + "disp_cc_mdss_dp_link_intf_clk", + "disp_cc_mdss_dp_pixel_clk", + "disp_cc_mdss_edp_aux_clk", + "disp_cc_mdss_edp_link_clk", + "disp_cc_mdss_edp_link_intf_clk", + "disp_cc_mdss_edp_pixel_clk", + "disp_cc_mdss_esc0_clk", + "disp_cc_mdss_mdp_clk", + "disp_cc_mdss_mdp_lut_clk", + "disp_cc_mdss_non_gdsc_ahb_clk", + "disp_cc_mdss_pclk0_clk", + "disp_cc_mdss_rot_clk", + "disp_cc_mdss_rscc_ahb_clk", + "disp_cc_mdss_rscc_vsync_clk", + "disp_cc_mdss_vsync_clk", + "disp_cc_sleep_clk", + "measure_only_disp_cc_xo_clk", +}; + +static int disp_cc_debug_mux_sels[] = { + 0x16, /* disp_cc_mdss_ahb_clk */ + 0xE, /* disp_cc_mdss_byte0_clk */ + 0xF, /* disp_cc_mdss_byte0_intf_clk */ + 0x15, /* disp_cc_mdss_dp_aux_clk */ + 0x13, /* disp_cc_mdss_dp_crypto_clk */ + 0x11, /* disp_cc_mdss_dp_link_clk */ + 0x12, /* disp_cc_mdss_dp_link_intf_clk */ + 0x14, /* disp_cc_mdss_dp_pixel_clk */ + 0x1A, /* disp_cc_mdss_edp_aux_clk */ + 0x18, /* disp_cc_mdss_edp_link_clk */ + 0x19, /* disp_cc_mdss_edp_link_intf_clk */ + 0x17, /* disp_cc_mdss_edp_pixel_clk */ + 0x10, /* disp_cc_mdss_esc0_clk */ + 0xA, /* disp_cc_mdss_mdp_clk */ + 0xC, /* disp_cc_mdss_mdp_lut_clk */ + 0x1B, /* disp_cc_mdss_non_gdsc_ahb_clk */ + 0x9, /* disp_cc_mdss_pclk0_clk */ + 0xB, /* disp_cc_mdss_rot_clk */ + 0x1D, /* disp_cc_mdss_rscc_ahb_clk */ + 0x1C, /* disp_cc_mdss_rscc_vsync_clk */ + 0xD, /* disp_cc_mdss_vsync_clk */ + 0x23, /* disp_cc_sleep_clk */ + 0x24, /* measure_only_disp_cc_xo_clk */ +}; + +static struct clk_debug_mux disp_cc_debug_mux = { + .priv = &debug_mux_priv, + .debug_offset = 0x7000, + .post_div_offset = 0x3000, + .cbcr_offset = 0x3004, + .src_sel_mask = 0xFF, + .src_sel_shift = 0, + .post_div_mask = 0xF, + .post_div_shift = 0, + .post_div_val = 4, + .mux_sels = disp_cc_debug_mux_sels, + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = disp_cc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(disp_cc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const char *const gcc_debug_mux_parent_names[] = { + "apss_cc_debug_mux", + "cam_cc_debug_mux", + "disp_cc_debug_mux", + "gcc_aggre_noc_pcie_0_axi_clk", + "gcc_aggre_noc_pcie_1_axi_clk", + "gcc_aggre_noc_pcie_center_sf_axi_clk", + "gcc_aggre_ufs_phy_axi_clk", + "gcc_aggre_usb3_prim_axi_clk", + "gcc_aggre_usb3_sec_axi_clk", + "gcc_camera_hf_axi_clk", + "gcc_camera_sf_axi_clk", + "gcc_cfg_noc_usb3_prim_axi_clk", + "gcc_cfg_noc_usb3_sec_axi_clk", + "gcc_ddrss_gpu_axi_clk", + "gcc_ddrss_pcie_sf_clk", + "gcc_disp_gpll0_clk_src", + "gcc_disp_hf_axi_clk", + "gcc_disp_sf_axi_clk", + "gcc_gp1_clk", + "gcc_gp2_clk", + "gcc_gp3_clk", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src", + "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gcc_pcie0_phy_rchng_clk", + "gcc_pcie1_phy_rchng_clk", + "gcc_pcie_0_aux_clk", + "gcc_pcie_0_cfg_ahb_clk", + "gcc_pcie_0_mstr_axi_clk", + "gcc_pcie_0_pipe_clk", + "gcc_pcie_0_slv_axi_clk", + "gcc_pcie_0_slv_q2a_axi_clk", + "gcc_pcie_1_aux_clk", + "gcc_pcie_1_cfg_ahb_clk", + "gcc_pcie_1_mstr_axi_clk", + "gcc_pcie_1_pipe_clk", + "gcc_pcie_1_slv_axi_clk", + "gcc_pcie_1_slv_q2a_axi_clk", + "gcc_pcie_throttle_core_clk", + "gcc_pdm2_clk", + "gcc_pdm_ahb_clk", + "gcc_pdm_xo4_clk", + "gcc_qmip_camera_nrt_ahb_clk", + "gcc_qmip_camera_rt_ahb_clk", + "gcc_qmip_disp_ahb_clk", + "gcc_qmip_video_vcodec_ahb_clk", + "gcc_qupv3_wrap0_core_2x_clk", + "gcc_qupv3_wrap0_core_clk", + "gcc_qupv3_wrap0_s0_clk", + "gcc_qupv3_wrap0_s1_clk", + "gcc_qupv3_wrap0_s2_clk", + "gcc_qupv3_wrap0_s3_clk", + "gcc_qupv3_wrap0_s4_clk", + "gcc_qupv3_wrap0_s5_clk", + "gcc_qupv3_wrap0_s6_clk", + "gcc_qupv3_wrap0_s7_clk", + "gcc_qupv3_wrap1_core_2x_clk", + "gcc_qupv3_wrap1_core_clk", + "gcc_qupv3_wrap1_s0_clk", + "gcc_qupv3_wrap1_s1_clk", + "gcc_qupv3_wrap1_s2_clk", + "gcc_qupv3_wrap1_s3_clk", + "gcc_qupv3_wrap1_s4_clk", + "gcc_qupv3_wrap1_s5_clk", + "gcc_qupv3_wrap1_s6_clk", + "gcc_qupv3_wrap1_s7_clk", + "gcc_qupv3_wrap_0_m_ahb_clk", + "gcc_qupv3_wrap_0_s_ahb_clk", + "gcc_qupv3_wrap_1_m_ahb_clk", + "gcc_qupv3_wrap_1_s_ahb_clk", + "gcc_sdcc1_ahb_clk", + "gcc_sdcc1_apps_clk", + "gcc_sdcc1_ice_core_clk", + "gcc_sdcc2_ahb_clk", + "gcc_sdcc2_apps_clk", + "gcc_sdcc4_ahb_clk", + "gcc_sdcc4_apps_clk", + "gcc_throttle_pcie_ahb_clk", + "gcc_titan_nrt_throttle_core_clk", + "gcc_titan_rt_throttle_core_clk", + "gcc_ufs_phy_ahb_clk", + "gcc_ufs_phy_axi_clk", + "gcc_ufs_phy_ice_core_clk", + "gcc_ufs_phy_phy_aux_clk", + "gcc_ufs_phy_rx_symbol_0_clk", + "gcc_ufs_phy_rx_symbol_1_clk", + "gcc_ufs_phy_tx_symbol_0_clk", + "gcc_ufs_phy_unipro_core_clk", + "gcc_usb30_prim_master_clk", + "gcc_usb30_prim_mock_utmi_clk", + "gcc_usb30_prim_sleep_clk", + "gcc_usb30_sec_master_clk", + "gcc_usb30_sec_mock_utmi_clk", + "gcc_usb30_sec_sleep_clk", + "gcc_usb3_prim_phy_aux_clk", + "gcc_usb3_prim_phy_com_aux_clk", + "gcc_usb3_prim_phy_pipe_clk", + "gcc_usb3_sec_phy_aux_clk", + "gcc_usb3_sec_phy_com_aux_clk", + "gcc_usb3_sec_phy_pipe_clk", + "gcc_video_axi0_clk", + "gcc_video_mvp_throttle_core_clk", + "gpu_cc_debug_mux", + "mc_cc_debug_mux", + "measure_only_cnoc_clk", + "measure_only_gcc_camera_ahb_clk", + "measure_only_gcc_camera_xo_clk", + "measure_only_gcc_disp_ahb_clk", + "measure_only_gcc_disp_xo_clk", + "measure_only_gcc_gpu_cfg_ahb_clk", + "measure_only_gcc_video_ahb_clk", + "measure_only_gcc_video_xo_clk", + "measure_only_ipa_2x_clk", + "measure_only_memnoc_clk", + "measure_only_pcie_0_pipe_clk", + "measure_only_pcie_1_pipe_clk", + "measure_only_snoc_clk", + "measure_only_ufs_phy_rx_symbol_0_clk", + "measure_only_ufs_phy_rx_symbol_1_clk", + "measure_only_ufs_phy_tx_symbol_0_clk", + "measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk", + "video_cc_debug_mux", +}; + +static int gcc_debug_mux_sels[] = { + 0xED, /* apss_cc_debug_mux */ + 0x4E, /* cam_cc_debug_mux */ + 0x54, /* disp_cc_debug_mux */ + 0x12C, /* gcc_aggre_noc_pcie_0_axi_clk */ + 0x12D, /* gcc_aggre_noc_pcie_1_axi_clk */ + 0x172, /* gcc_aggre_noc_pcie_center_sf_axi_clk */ + 0x12F, /* gcc_aggre_ufs_phy_axi_clk */ + 0x12E, /* gcc_aggre_usb3_prim_axi_clk */ + 0x170, /* gcc_aggre_usb3_sec_axi_clk */ + 0x49, /* gcc_camera_hf_axi_clk */ + 0x4B, /* gcc_camera_sf_axi_clk */ + 0x1B, /* gcc_cfg_noc_usb3_prim_axi_clk */ + 0x1C, /* gcc_cfg_noc_usb3_sec_axi_clk */ + 0xCD, /* gcc_ddrss_gpu_axi_clk */ + 0xCE, /* gcc_ddrss_pcie_sf_clk */ + 0x45, /* gcc_disp_gpll0_clk_src */ + 0x51, /* gcc_disp_hf_axi_clk */ + 0x52, /* gcc_disp_sf_axi_clk */ + 0xF8, /* gcc_gp1_clk */ + 0xF9, /* gcc_gp2_clk */ + 0xFA, /* gcc_gp3_clk */ + 0x14B, /* gcc_gpu_gpll0_clk_src */ + 0x14C, /* gcc_gpu_gpll0_div_clk_src */ + 0x147, /* gcc_gpu_memnoc_gfx_clk */ + 0x14A, /* gcc_gpu_snoc_dvm_gfx_clk */ + 0x101, /* gcc_pcie0_phy_rchng_clk */ + 0x10A, /* gcc_pcie1_phy_rchng_clk */ + 0xFF, /* gcc_pcie_0_aux_clk */ + 0xFE, /* gcc_pcie_0_cfg_ahb_clk */ + 0xFD, /* gcc_pcie_0_mstr_axi_clk */ + 0x100, /* gcc_pcie_0_pipe_clk */ + 0xFC, /* gcc_pcie_0_slv_axi_clk */ + 0xFB, /* gcc_pcie_0_slv_q2a_axi_clk */ + 0x108, /* gcc_pcie_1_aux_clk */ + 0x107, /* gcc_pcie_1_cfg_ahb_clk */ + 0x106, /* gcc_pcie_1_mstr_axi_clk */ + 0x109, /* gcc_pcie_1_pipe_clk */ + 0x105, /* gcc_pcie_1_slv_axi_clk */ + 0x104, /* gcc_pcie_1_slv_q2a_axi_clk */ + 0x30, /* gcc_pcie_throttle_core_clk */ + 0xA4, /* gcc_pdm2_clk */ + 0xA2, /* gcc_pdm_ahb_clk */ + 0xA3, /* gcc_pdm_xo4_clk */ + 0x47, /* gcc_qmip_camera_nrt_ahb_clk */ + 0x48, /* gcc_qmip_camera_rt_ahb_clk */ + 0x50, /* gcc_qmip_disp_ahb_clk */ + 0x57, /* gcc_qmip_video_vcodec_ahb_clk */ + 0x8D, /* gcc_qupv3_wrap0_core_2x_clk */ + 0x8C, /* gcc_qupv3_wrap0_core_clk */ + 0x8E, /* gcc_qupv3_wrap0_s0_clk */ + 0x8F, /* gcc_qupv3_wrap0_s1_clk */ + 0x90, /* gcc_qupv3_wrap0_s2_clk */ + 0x91, /* gcc_qupv3_wrap0_s3_clk */ + 0x92, /* gcc_qupv3_wrap0_s4_clk */ + 0x93, /* gcc_qupv3_wrap0_s5_clk */ + 0x94, /* gcc_qupv3_wrap0_s6_clk */ + 0x95, /* gcc_qupv3_wrap0_s7_clk */ + 0x99, /* gcc_qupv3_wrap1_core_2x_clk */ + 0x98, /* gcc_qupv3_wrap1_core_clk */ + 0x9A, /* gcc_qupv3_wrap1_s0_clk */ + 0x9B, /* gcc_qupv3_wrap1_s1_clk */ + 0x9C, /* gcc_qupv3_wrap1_s2_clk */ + 0x9D, /* gcc_qupv3_wrap1_s3_clk */ + 0x9E, /* gcc_qupv3_wrap1_s4_clk */ + 0x9F, /* gcc_qupv3_wrap1_s5_clk */ + 0xA0, /* gcc_qupv3_wrap1_s6_clk */ + 0xA1, /* gcc_qupv3_wrap1_s7_clk */ + 0x8A, /* gcc_qupv3_wrap_0_m_ahb_clk */ + 0x8B, /* gcc_qupv3_wrap_0_s_ahb_clk */ + 0x96, /* gcc_qupv3_wrap_1_m_ahb_clk */ + 0x97, /* gcc_qupv3_wrap_1_s_ahb_clk */ + 0x15D, /* gcc_sdcc1_ahb_clk */ + 0x15E, /* gcc_sdcc1_apps_clk */ + 0x15F, /* gcc_sdcc1_ice_core_clk */ + 0x87, /* gcc_sdcc2_ahb_clk */ + 0x86, /* gcc_sdcc2_apps_clk */ + 0x89, /* gcc_sdcc4_ahb_clk */ + 0x88, /* gcc_sdcc4_apps_clk */ + 0x3A, /* gcc_throttle_pcie_ahb_clk */ + 0x4C, /* gcc_titan_nrt_throttle_core_clk */ + 0x4A, /* gcc_titan_rt_throttle_core_clk */ + 0x10E, /* gcc_ufs_phy_ahb_clk */ + 0x10D, /* gcc_ufs_phy_axi_clk */ + 0x114, /* gcc_ufs_phy_ice_core_clk */ + 0x115, /* gcc_ufs_phy_phy_aux_clk */ + 0x110, /* gcc_ufs_phy_rx_symbol_0_clk */ + 0x116, /* gcc_ufs_phy_rx_symbol_1_clk */ + 0x10F, /* gcc_ufs_phy_tx_symbol_0_clk */ + 0x113, /* gcc_ufs_phy_unipro_core_clk */ + 0x70, /* gcc_usb30_prim_master_clk */ + 0x72, /* gcc_usb30_prim_mock_utmi_clk */ + 0x71, /* gcc_usb30_prim_sleep_clk */ + 0x7C, /* gcc_usb30_sec_master_clk */ + 0x7E, /* gcc_usb30_sec_mock_utmi_clk */ + 0x7D, /* gcc_usb30_sec_sleep_clk */ + 0x73, /* gcc_usb3_prim_phy_aux_clk */ + 0x74, /* gcc_usb3_prim_phy_com_aux_clk */ + 0x75, /* gcc_usb3_prim_phy_pipe_clk */ + 0x7F, /* gcc_usb3_sec_phy_aux_clk */ + 0x80, /* gcc_usb3_sec_phy_com_aux_clk */ + 0x81, /* gcc_usb3_sec_phy_pipe_clk */ + 0x58, /* gcc_video_axi0_clk */ + 0x59, /* gcc_video_mvp_throttle_core_clk */ + 0x146, /* gpu_cc_debug_mux */ + 0xD7, /* mc_cc_debug_mux or ddrss_gcc_debug_clk */ + 0x17, /* measure_only_cnoc_clk */ + 0x46, /* measure_only_gcc_camera_ahb_clk */ + 0x4D, /* measure_only_gcc_camera_xo_clk */ + 0x4F, /* measure_only_gcc_disp_ahb_clk */ + 0x53, /* measure_only_gcc_disp_xo_clk */ + 0x144, /* measure_only_gcc_gpu_cfg_ahb_clk */ + 0x55, /* measure_only_gcc_video_ahb_clk */ + 0x5C, /* measure_only_gcc_video_xo_clk */ + 0x132, /* measure_only_ipa_2x_clk */ + 0xD3, /* measure_only_memnoc_clk */ + 0x102, /* measure_only_pcie_0_pipe_clk */ + 0x10B, /* measure_only_pcie_1_pipe_clk */ + 0x9, /* measure_only_snoc_clk */ + 0x112, /* measure_only_ufs_phy_rx_symbol_0_clk */ + 0x117, /* measure_only_ufs_phy_rx_symbol_1_clk */ + 0x111, /* measure_only_ufs_phy_tx_symbol_0_clk */ + 0x79, /* measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk */ + 0x5D, /* video_cc_debug_mux */ +}; + +static struct clk_debug_mux gcc_debug_mux = { + .priv = &debug_mux_priv, + .debug_offset = 0x62000, + .post_div_offset = 0x62004, + .cbcr_offset = 0x62008, + .src_sel_mask = 0x3FF, + .src_sel_shift = 0, + .post_div_mask = 0xF, + .post_div_shift = 0, + .post_div_val = 2, + .mux_sels = gcc_debug_mux_sels, + .hw.init = &(struct clk_init_data){ + .name = "gcc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = gcc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(gcc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const char *const gpu_cc_debug_mux_parent_names[] = { + "gpu_cc_ahb_clk", + "gpu_cc_crc_ahb_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_cx_snoc_dvm_clk", + "gpu_cc_cxo_aon_clk", + "gpu_cc_cxo_clk", + "gpu_cc_gx_gmu_clk", + "gpu_cc_hub_aon_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_mnd1x_0_gfx3d_clk", + "gpu_cc_mnd1x_1_gfx3d_clk", + "gpu_cc_sleep_clk", + "measure_only_gpu_cc_cb_clk", + "measure_only_gpu_cc_cx_gfx3d_clk", + "measure_only_gpu_cc_cx_gfx3d_slv_clk", + "measure_only_gpu_cc_gx_gfx3d_clk", +}; + +static int gpu_cc_debug_mux_sels[] = { + 0x12, /* gpu_cc_ahb_clk */ + 0x13, /* gpu_cc_crc_ahb_clk */ + 0x1A, /* gpu_cc_cx_gmu_clk */ + 0x17, /* gpu_cc_cx_snoc_dvm_clk */ + 0xB, /* gpu_cc_cxo_aon_clk */ + 0x1B, /* gpu_cc_cxo_clk */ + 0x11, /* gpu_cc_gx_gmu_clk */ + 0x27, /* gpu_cc_hub_aon_clk */ + 0x1C, /* gpu_cc_hub_cx_int_clk */ + 0x21, /* gpu_cc_mnd1x_0_gfx3d_clk */ + 0x22, /* gpu_cc_mnd1x_1_gfx3d_clk */ + 0x18, /* gpu_cc_sleep_clk */ + 0x26, /* measure_only_gpu_cc_cb_clk */ + 0x1D, /* measure_only_gpu_cc_cx_gfx3d_clk */ + 0x1E, /* measure_only_gpu_cc_cx_gfx3d_slv_clk */ + 0xD, /* measure_only_gpu_cc_gx_gfx3d_clk */ +}; + +static struct clk_debug_mux gpu_cc_debug_mux = { + .priv = &debug_mux_priv, + .debug_offset = 0x1568, + .post_div_offset = 0x10FC, + .cbcr_offset = 0x1100, + .src_sel_mask = 0xFF, + .src_sel_shift = 0, + .post_div_mask = 0xF, + .post_div_shift = 0, + .post_div_val = 2, + .mux_sels = gpu_cc_debug_mux_sels, + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = gpu_cc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(gpu_cc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const char *const video_cc_debug_mux_parent_names[] = { + "video_cc_iris_ahb_clk", + "video_cc_mvs0_axi_clk", + "video_cc_mvs0_core_clk", + "video_cc_mvsc_core_clk", + "video_cc_mvsc_ctl_axi_clk", + "video_cc_sleep_clk", + "video_cc_venus_ahb_clk", + "video_cc_xo_clk", +}; + +static int video_cc_debug_mux_sels[] = { + 0x5, /* video_cc_iris_ahb_clk */ + 0x9, /* video_cc_mvs0_axi_clk */ + 0x3, /* video_cc_mvs0_core_clk */ + 0x1, /* video_cc_mvsc_core_clk */ + 0x8, /* video_cc_mvsc_ctl_axi_clk */ + 0x7, /* video_cc_sleep_clk */ + 0xC, /* video_cc_venus_ahb_clk */ + 0x6, /* video_cc_xo_clk */ +}; + +static struct clk_debug_mux video_cc_debug_mux = { + .priv = &debug_mux_priv, + .debug_offset = 0x9000, + .post_div_offset = 0x6000, + .cbcr_offset = 0x6004, + .src_sel_mask = 0x3F, + .src_sel_shift = 0, + .post_div_mask = 0xF, + .post_div_shift = 0, + .post_div_val = 2, + .mux_sels = video_cc_debug_mux_sels, + .hw.init = &(struct clk_init_data){ + .name = "video_cc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = video_cc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(video_cc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const char *const mc_cc_debug_mux_parent_names[] = { + "measure_only_mccc_clk", +}; + +static struct clk_debug_mux mc_cc_debug_mux = { + .period_offset = 0x50, + .hw.init = &(struct clk_init_data){ + .name = "mc_cc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = mc_cc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(mc_cc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static struct mux_regmap_names mux_list[] = { + { .mux = &apss_cc_debug_mux, .regmap_name = "qcom,apsscc" }, + { .mux = &cam_cc_debug_mux, .regmap_name = "qcom,camcc" }, + { .mux = &disp_cc_debug_mux, .regmap_name = "qcom,dispcc" }, + { .mux = &gcc_debug_mux, .regmap_name = "qcom,gcc" }, + { .mux = &gpu_cc_debug_mux, .regmap_name = "qcom,gpucc" }, + { .mux = &mc_cc_debug_mux, .regmap_name = "qcom,mccc" }, + { .mux = &video_cc_debug_mux, .regmap_name = "qcom,videocc" }, +}; + +static struct clk_dummy measure_only_apcs_gold_post_acd_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_apcs_gold_post_acd_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_apcs_goldplus_post_acd_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_apcs_goldplus_post_acd_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_apcs_l3_post_acd_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_apcs_l3_post_acd_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_apcs_silver_post_acd_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_apcs_silver_post_acd_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_cnoc_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_cnoc_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_disp_cc_xo_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_disp_cc_xo_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_gcc_camera_ahb_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_gcc_camera_ahb_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_gcc_camera_xo_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_gcc_camera_xo_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_gcc_disp_ahb_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_gcc_disp_ahb_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_gcc_disp_xo_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_gcc_disp_xo_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_gcc_gpu_cfg_ahb_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_gcc_gpu_cfg_ahb_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_gcc_video_ahb_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_gcc_video_ahb_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_gcc_video_xo_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_gcc_video_xo_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_gpu_cc_cb_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_gpu_cc_cb_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_gpu_cc_cx_gfx3d_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_gpu_cc_cx_gfx3d_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_gpu_cc_cx_gfx3d_slv_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_gpu_cc_cx_gfx3d_slv_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_gpu_cc_gx_gfx3d_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_gpu_cc_gx_gfx3d_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_mccc_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_mccc_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_ipa_2x_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_ipa_2x_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_memnoc_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_memnoc_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_pcie_0_pipe_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_pcie_0_pipe_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_pcie_1_pipe_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_pcie_1_pipe_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_snoc_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_snoc_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_ufs_phy_rx_symbol_0_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_ufs_phy_rx_symbol_0_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_ufs_phy_rx_symbol_1_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_ufs_phy_rx_symbol_1_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_ufs_phy_tx_symbol_0_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_ufs_phy_tx_symbol_0_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_hw *debugcc_yupik_hws[] = { + &measure_only_apcs_gold_post_acd_clk.hw, + &measure_only_apcs_goldplus_post_acd_clk.hw, + &measure_only_apcs_l3_post_acd_clk.hw, + &measure_only_apcs_silver_post_acd_clk.hw, + &measure_only_cnoc_clk.hw, + &measure_only_disp_cc_xo_clk.hw, + &measure_only_gcc_camera_ahb_clk.hw, + &measure_only_gcc_camera_xo_clk.hw, + &measure_only_gcc_disp_ahb_clk.hw, + &measure_only_gcc_disp_xo_clk.hw, + &measure_only_gcc_gpu_cfg_ahb_clk.hw, + &measure_only_gcc_video_ahb_clk.hw, + &measure_only_gcc_video_xo_clk.hw, + &measure_only_gpu_cc_cb_clk.hw, + &measure_only_gpu_cc_cx_gfx3d_clk.hw, + &measure_only_gpu_cc_cx_gfx3d_slv_clk.hw, + &measure_only_gpu_cc_gx_gfx3d_clk.hw, + &measure_only_mccc_clk.hw, + &measure_only_ipa_2x_clk.hw, + &measure_only_memnoc_clk.hw, + &measure_only_pcie_0_pipe_clk.hw, + &measure_only_pcie_1_pipe_clk.hw, + &measure_only_snoc_clk.hw, + &measure_only_ufs_phy_rx_symbol_0_clk.hw, + &measure_only_ufs_phy_rx_symbol_1_clk.hw, + &measure_only_ufs_phy_tx_symbol_0_clk.hw, + &measure_only_usb3_phy_wrapper_gcc_usb30_pipe_clk.hw, +}; + +static const struct of_device_id clk_debug_match_table[] = { + { .compatible = "qcom,yupik-debugcc" }, + { } +}; + +static int clk_debug_yupik_probe(struct platform_device *pdev) +{ + struct clk *clk; + int ret = 0, i; + + BUILD_BUG_ON(ARRAY_SIZE(apss_cc_debug_mux_parent_names) != + ARRAY_SIZE(apss_cc_debug_mux_sels)); + BUILD_BUG_ON(ARRAY_SIZE(cam_cc_debug_mux_parent_names) != + ARRAY_SIZE(cam_cc_debug_mux_sels)); + BUILD_BUG_ON(ARRAY_SIZE(disp_cc_debug_mux_parent_names) != + ARRAY_SIZE(disp_cc_debug_mux_sels)); + BUILD_BUG_ON(ARRAY_SIZE(gcc_debug_mux_parent_names) != + ARRAY_SIZE(gcc_debug_mux_sels)); + BUILD_BUG_ON(ARRAY_SIZE(gpu_cc_debug_mux_parent_names) != + ARRAY_SIZE(gpu_cc_debug_mux_sels)); + BUILD_BUG_ON(ARRAY_SIZE(video_cc_debug_mux_parent_names) != + ARRAY_SIZE(video_cc_debug_mux_sels)); + + clk = devm_clk_get(&pdev->dev, "xo_clk_src"); + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get xo clock\n"); + return PTR_ERR(clk); + } + + debug_mux_priv.cxo = clk; + + for (i = 0; i < ARRAY_SIZE(mux_list); i++) { + ret = map_debug_bases(pdev, mux_list[i].regmap_name, + mux_list[i].mux); + if (ret == -EBADR) + continue; + else if (ret) + return ret; + + clk = devm_clk_register(&pdev->dev, &mux_list[i].mux->hw); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n", + clk_hw_get_name(&mux_list[i].mux->hw), + PTR_ERR(clk)); + return PTR_ERR(clk); + } + } + + for (i = 0; i < ARRAY_SIZE(debugcc_yupik_hws); i++) { + clk = devm_clk_register(&pdev->dev, debugcc_yupik_hws[i]); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n", + clk_hw_get_name(debugcc_yupik_hws[i]), + PTR_ERR(clk)); + return PTR_ERR(clk); + } + } + + ret = clk_debug_measure_register(&gcc_debug_mux.hw); + if (ret) { + dev_err(&pdev->dev, "Could not register Measure clocks\n"); + return ret; + } + + dev_info(&pdev->dev, "Registered debug measure clocks\n"); + + return ret; +} + +static struct platform_driver clk_debug_driver = { + .probe = clk_debug_yupik_probe, + .driver = { + .name = "yupik-debugcc", + .of_match_table = clk_debug_match_table, + }, +}; + +static int __init clk_debug_yupik_init(void) +{ + return platform_driver_register(&clk_debug_driver); +} +fs_initcall(clk_debug_yupik_init); + +MODULE_DESCRIPTION("QTI DEBUG CC YUPIK Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:debugcc-yupik"); diff --git a/drivers/clk/qcom/dispcc-yupik.c b/drivers/clk/qcom/dispcc-yupik.c new file mode 100644 index 000000000000..142a23382d90 --- /dev/null +++ b/drivers/clk/qcom/dispcc-yupik.c @@ -0,0 +1,1101 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" +#include "vdd-level.h" + +static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH + 1, 1, vdd_corner); + +static struct clk_vdd_class *disp_cc_yupik_regulators[] = { + &vdd_cx, +}; + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_EVEN, + P_DISP_CC_PLL0_OUT_MAIN, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_EDP_PHY_PLL_LINK_CLK, + P_EDP_PHY_PLL_VCO_DIV_CLK, + P_GCC_DISP_GPLL0_CLK, +}; + +static struct pll_vco lucid_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +/* 1520MHz Configuration*/ +static const struct alpha_pll_config disp_cc_pll0_config = { + .l = 0x4F, + .alpha = 0x2AAA, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329A299C, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll disp_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + .vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1600000000, + [VDD_NOMINAL] = 2000000000}, + }, + }, +}; + +static const struct parent_map disp_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo" }, +}; + +static const struct parent_map disp_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" }, + { .fw_name = "dp_phy_pll_vco_div_clk", .name = + "dp_phy_pll_vco_div_clk" }, +}; + +static const struct parent_map disp_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_byteclk", .name = + "dsi0_phy_pll_out_byteclk" }, +}; + +static const struct parent_map disp_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_EDP_PHY_PLL_LINK_CLK, 1 }, + { P_EDP_PHY_PLL_VCO_DIV_CLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "edp_phy_pll_link_clk", .name = "edp_phy_pll_link_clk" }, + { .fw_name = "edp_phy_pll_vco_div_clk", .name = + "edp_phy_pll_vco_div_clk" }, +}; + +static const struct parent_map disp_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_GCC_DISP_GPLL0_CLK, 4 }, + { P_DISP_CC_PLL0_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &disp_cc_pll0.clkr.hw }, + { .fw_name = "gcc_disp_gpll0_clk" }, + { .hw = &disp_cc_pll0.clkr.hw }, +}; + +static const struct parent_map disp_cc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_GCC_DISP_GPLL0_CLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "gcc_disp_gpll0_clk" }, +}; + +static const struct parent_map disp_cc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_6[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_dsiclk", .name = + "dsi0_phy_pll_out_dsiclk" }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0), + F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { + .cmd_rcgr = 0x1170, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_5, + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk_src", + .parent_data = disp_cc_parent_data_5, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 37500000, + [VDD_NOMINAL] = 75000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { + .cmd_rcgr = 0x10d8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_byte2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 187500000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 358000000}, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr = 0x1158, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { + F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), + F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), + F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), + F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { + .cmd_rcgr = 0x1128, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 180000, + [VDD_LOW_L1] = 360000, + [VDD_NOMINAL] = 540000}, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr = 0x110c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 270000, + [VDD_LOW_L1] = 540000, + [VDD_NOMINAL] = 810000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr = 0x1140, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_dp_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 337500000, + [VDD_NOMINAL] = 675000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = { + .cmd_rcgr = 0x11d0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_aux_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_edp_link_clk_src[] = { + F( 19200000, P_BI_TCXO, 1, 0, 0), + F( 270000000, P_EDP_PHY_PLL_LINK_CLK, 1, 0, 0), + F( 540000000, P_EDP_PHY_PLL_LINK_CLK, 1, 0, 0), + F( 810000000, P_EDP_PHY_PLL_LINK_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = { + .cmd_rcgr = 0x11a0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_edp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_link_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 270000000, + [VDD_LOW_L1] = 540000000, + [VDD_NOMINAL] = 810000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { + .cmd_rcgr = 0x1188, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_pixel_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_dp_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 337500000, + [VDD_NOMINAL] = 675000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { + .cmd_rcgr = 0x10f4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { + F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0), + F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0), + F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(506666667, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { + .cmd_rcgr = 0x1090, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 200000000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 380000000, + [VDD_NOMINAL] = 506666667, + [VDD_HIGH] = 608000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { + .cmd_rcgr = 0x1078, + .mnd_width = 8, + .hid_width = 5, + .parent_map = disp_cc_parent_map_6, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk_src", + .parent_data = disp_cc_parent_data_6, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_pixel_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 328125000, + [VDD_LOW] = 525000000, + [VDD_LOW_L1] = 625000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { + .cmd_rcgr = 0x10a8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 200000000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 380000000, + [VDD_NOMINAL] = 506666667, + [VDD_HIGH] = 608000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { + .cmd_rcgr = 0x10c0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { + .reg = 0x10f0, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_byte0_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { + .reg = 0x1124, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_dp_link_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = { + .reg = 0x11b8, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_edp_link_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_edp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk = { + .halt_reg = 0x1050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk = { + .halt_reg = 0x1030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk = { + .halt_reg = 0x1034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_intf_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg = 0x104c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x104c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg = 0x1044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg = 0x103c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x103c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg = 0x1040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_intf_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk = { + .halt_reg = 0x1048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_aux_clk = { + .halt_reg = 0x1060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_edp_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_link_clk = { + .halt_reg = 0x1058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_link_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_edp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { + .halt_reg = 0x105c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x105c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_link_intf_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_edp_link_div_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_edp_pixel_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_edp_pixel_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_edp_pixel_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk = { + .halt_reg = 0x1038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1038, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk = { + .halt_reg = 0x1014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk = { + .halt_reg = 0x1024, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_lut_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { + .halt_reg = 0x2004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x2004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk = { + .halt_reg = 0x1010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rot_clk = { + .halt_reg = 0x101c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x101c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_rot_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { + .halt_reg = 0x200c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x200c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rscc_ahb_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { + .halt_reg = 0x2008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rscc_vsync_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk = { + .halt_reg = 0x102c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x102c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_sleep_clk = { + .halt_reg = 0x5004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *disp_cc_yupik_clocks[] = { + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = + &disp_cc_mdss_dp_link_div_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, + [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr, + [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, + [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = + &disp_cc_mdss_edp_link_div_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, + [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, + [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, + [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, + [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, + [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] = &disp_cc_pll0.clkr, + [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, +}; + +static const struct regmap_config disp_cc_yupik_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static const struct qcom_cc_desc disp_cc_yupik_desc = { + .config = &disp_cc_yupik_regmap_config, + .clks = disp_cc_yupik_clocks, + .num_clks = ARRAY_SIZE(disp_cc_yupik_clocks), + .clk_regulators = disp_cc_yupik_regulators, + .num_clk_regulators = ARRAY_SIZE(disp_cc_yupik_regulators), +}; + +static const struct of_device_id disp_cc_yupik_match_table[] = { + { .compatible = "qcom,yupik-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_yupik_match_table); + +static int disp_cc_yupik_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap = qcom_cc_map(pdev, &disp_cc_yupik_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + pm_runtime_enable(&pdev->dev); + ret = pm_clk_create(&pdev->dev); + if (ret) + goto disable_pm_runtime; + + ret = pm_clk_add(&pdev->dev, "cfg_ahb"); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to get ahb clock handle\n"); + goto destroy_pm_clk; + } + + clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); + + /* + * Keep the clocks always-ON + * DISP_CC_XO_CLK + */ + regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0)); + + ret = qcom_cc_really_probe(pdev, &disp_cc_yupik_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register DISP CC clocks\n"); + goto destroy_pm_clk; + } + + dev_info(&pdev->dev, "Registered DISP CC clocks\n"); + + return 0; + +destroy_pm_clk: + pm_clk_destroy(&pdev->dev); + +disable_pm_runtime: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static const struct dev_pm_ops disp_cc_yupik_pm_ops = { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static void disp_cc_yupik_sync_state(struct device *dev) +{ + qcom_cc_sync_state(dev, &disp_cc_yupik_desc); +} + +static struct platform_driver disp_cc_yupik_driver = { + .probe = disp_cc_yupik_probe, + .driver = { + .name = "disp_cc-yupik", + .of_match_table = disp_cc_yupik_match_table, + .sync_state = disp_cc_yupik_sync_state, + .pm = &disp_cc_yupik_pm_ops, + }, +}; + +static int __init disp_cc_yupik_init(void) +{ + return platform_driver_register(&disp_cc_yupik_driver); +} +subsys_initcall(disp_cc_yupik_init); + +static void __exit disp_cc_yupik_exit(void) +{ + platform_driver_unregister(&disp_cc_yupik_driver); +} +module_exit(disp_cc_yupik_exit); + +MODULE_DESCRIPTION("QTI DISP_CC YUPIK Driver"); +MODULE_LICENSE("GPL v2");