mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 21:59:12 -04:00
ARM: dts: msm: Correct QUPv3 device nodes
Fix interrupt number, usage of shared flag and GSI mask values. Also remove the obsolete device nodes. Change-Id: Ia735f1f0402e56688a4bb6068b5db4e2f3e7614c
This commit is contained in:
Akash Asthana
parent
d9e39aa973
commit
a91bdb9f1b
1 changed files with 34 additions and 52 deletions
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@ -55,7 +55,7 @@
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0xff>;
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qcom,gpii-mask = <0x7f>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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qcom,gpi-ee-offset = <0x10000>;
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@ -67,7 +67,7 @@
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compatible = "qcom,msm-geni-console";
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reg = <0x994000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -84,7 +84,7 @@
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reg = <0x980000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -105,7 +105,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -126,7 +126,7 @@
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reg = <0x984000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -138,6 +138,7 @@
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<&gpi_dma0 1 1 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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qcom,shared;
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status = "disabled";
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};
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@ -147,7 +148,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -168,7 +169,7 @@
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reg = <0x988000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -189,7 +190,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -210,7 +211,7 @@
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reg = <0x98c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -231,7 +232,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -252,7 +253,7 @@
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reg = <0x990000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -273,7 +274,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -294,7 +295,7 @@
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reg = <0x998000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -315,7 +316,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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@ -336,7 +337,7 @@
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x99c000 0x4000>;
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reg-names = "se_phys";
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interrupts-extended = <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
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interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 31 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
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@ -390,7 +391,7 @@
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<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
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qcom,static-gpii-mask = <0x1>;
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qcom,gpii-mask = <0x7e>;
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qcom,gpii-mask = <0x3f>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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qcom,gpi-ee-offset = <0x10000>;
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@ -403,7 +404,7 @@
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reg = <0xa80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -424,7 +425,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -445,7 +446,7 @@
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reg = <0xa84000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -466,7 +467,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -486,7 +487,7 @@
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0xa88000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -504,7 +505,7 @@
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reg = <0xa88000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -525,7 +526,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -546,7 +547,7 @@
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reg = <0xa8c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -567,7 +568,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -588,7 +589,7 @@
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reg = <0xa90000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -609,7 +610,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -630,7 +631,7 @@
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reg = <0xa94000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -642,7 +643,6 @@
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<&gpi_dma1 1 5 3 64 2>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_1>;
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qcom,shared;
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status = "disabled";
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};
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@ -652,7 +652,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -668,30 +668,12 @@
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status = "disabled";
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};
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/* Travel adapter over 2-wire HSUART, no wakeup */
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qupv3_se14_2uart: qcom,qup_uart@a98000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0xa98000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "active", "sleep";
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pinctrl-0 = <&qupv3_se14_default_txrx>;
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pinctrl-1 = <&qupv3_se14_2uart_active>;
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pinctrl-2 = <&qupv3_se14_2uart_sleep>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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qupv3_se14_i2c: i2c@a98000 {
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compatible = "qcom,i2c-geni";
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reg = <0xa98000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -712,7 +694,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -733,7 +715,7 @@
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reg = <0xa9c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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@ -754,7 +736,7 @@
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#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
|
|
|
|||
Loading…
Reference in a new issue