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iommu/arm-smmu: reduce tlb sync poll retry latency
Limit tlb sync poll retry latency to a upper limit. This reduces the response time of tlb sync completion. Change-Id: I7b92e216c17f5942ad01a9e9f24eff88f7608388 Signed-off-by: Prakash Gupta <guptap@codeaurora.org> Signed-off-by: Chris Goldsworthy <cgoldswo@codeaurora.org>
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1 changed files with 11 additions and 10 deletions
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@ -66,7 +66,7 @@
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#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
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#define TLB_LOOP_TIMEOUT 500000 /* 500ms */
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#define TLB_SPIN_COUNT 10
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#define TLB_LOOP_INC_MAX 1000 /*1ms*/
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#define ARM_SMMU_IMPL_DEF1(smmu) \
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((smmu)->base + (6 * (1 << (smmu)->pgshift)))
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@ -886,19 +886,20 @@ static void arm_smmu_domain_power_off(struct iommu_domain *domain,
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static int __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
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int sync, int status)
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{
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unsigned int spin_cnt, delay;
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unsigned int inc, delay;
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u32 sync_inv_ack, tbu_pwr_status = -EINVAL, sync_inv_progress = -EINVAL;
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u32 reg;
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arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL);
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for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
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for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
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reg = arm_smmu_readl(smmu, page, status);
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if (!(reg & sTLBGSTATUS_GSACTIVE))
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return 0;
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cpu_relax();
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}
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udelay(delay);
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for (delay = 1, inc = 1; delay < TLB_LOOP_TIMEOUT; delay += inc) {
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reg = arm_smmu_readl(smmu, page, status);
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if (!(reg & sTLBGSTATUS_GSACTIVE))
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return 0;
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cpu_relax();
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udelay(inc);
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if (inc < TLB_LOOP_INC_MAX)
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inc *= 2;
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}
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sync_inv_ack = arm_smmu_readl(smmu,
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