From a98568af0da69e69362e6efe494c2247b4ab6130 Mon Sep 17 00:00:00 2001 From: Vivek Aknurwar Date: Tue, 23 Jun 2020 18:44:16 -0700 Subject: [PATCH] clk: qcom: gcc-lahaina: Update video_axi clks to clk_branch2_force_off_ops SMMU fault is observed due to spurious AXI transaction even after gcc video_axi clocks are disabled. HW underlying may not actually turn off clocks since HW enable signals can still be asserted/waiting on certain scenarios like when CVP and MVP both are power collapsed. Use clk_branch2_force_off_ops to guarantee that clocks are actually turned off when SW disables them. Change-Id: I87d62c48b1e24f5d7a8cefe3758e3b2b2b96af59 Signed-off-by: Vivek Aknurwar --- drivers/clk/qcom/gcc-lahaina.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-lahaina.c b/drivers/clk/qcom/gcc-lahaina.c index 65b337be240b..eab1d53fe5ad 100644 --- a/drivers/clk/qcom/gcc-lahaina.c +++ b/drivers/clk/qcom/gcc-lahaina.c @@ -4042,7 +4042,7 @@ static struct clk_branch gcc_video_axi0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_video_axi0_clk", - .ops = &clk_branch2_ops, + .ops = &clk_branch2_force_off_ops, }, }, }; @@ -4057,7 +4057,7 @@ static struct clk_branch gcc_video_axi1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_video_axi1_clk", - .ops = &clk_branch2_ops, + .ops = &clk_branch2_force_off_ops, }, }, };