From 6204011840f41bd71f9857bccfa7552a3bc67df1 Mon Sep 17 00:00:00 2001
From: Anvesh Salveru <asalveru@qti.qualcomm.com>
Date: Sat, 16 Oct 2021 22:33:48 +0530
Subject: [PATCH] ARM: dts: msm: Enable smmu s1 for blsp bam on sdxlemur V2

Enable smmu s1 for blsp bam DMA engine on sdxlemur V2.

Change-Id: I66b47f45832d4ce748d1badae685ed20a0da10c5
---
 qcom/sdxlemur-v2.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi
index 510d478826da..f2cadc6e4814 100644
--- a/qcom/sdxlemur-v2.dtsi
+++ b/qcom/sdxlemur-v2.dtsi
@@ -6,6 +6,20 @@
 	qcom,msm-id = <458 0x20000>, <483 0x20000>, <509 0x20000>;
 };
 
+/* Overriding the BAM node to enable SMMU S1 support in sdxlemur V2
+ * Adding i2c SID's in BAM node, as descriptors buffers for i2c
+ * usecase are allocated in BAM DMA driver.
+ */
+&dma_blsp1 {
+	iommus = <&apps_smmu 0x148 0x1>,
+		<&apps_smmu 0x14a 0x1>,
+		<&apps_smmu 0x14c 0x1>,
+		<&apps_smmu 0x14e 0x1>;
+	qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+	qcom,iommu-geometry = <0x40000000 0x10000000>;
+	qcom,iommu-dma = "fastmap";
+};
+
 &i2c_1 {
 	iommus = <&apps_smmu 0x148 0x1>;
 	qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;