dt-bindings: arm: msm: Introduce qcom,qsee_irq bindings

Interrupts from QSEE are level triggered and are cleared by writing
into a status register. Add the qcom,qsee_irq interrupt chip driver to
abstract this extra work from clients such as GLINK.

Change-Id: I0b2de24dfa2a58b1e076c5b28ad405896cb9c85e

bindings/arm/msm/qcom,qsee_irq.txt

@@ -0,0 +1,82 @@
+Binding for the QTI Secure Execution Environment IRQ controller
+===============================================================
+
+The QTI Secure Execution Environment (QSEE) IRQ controller facilitates receiving
+and clearing interrupts from QSEE. Each interrupt from QSEE has a set of control
+registers to mask, clear and get the status of interrupts. This controller will
+create an interrupt for clients to register with based on the bits available in
+the control registers.
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: must be one of:
+		    "qcom,sm8150-qsee-irq",
+		    "qcom,kona-qsee-irq"
+
+- syscon:
+	usage: required
+	Value type: <prop-encoded-array>
+	Definition: phandle to a syscon node representing the scsr registers
+
+- interrupts:
+	Usage: required
+	Value type: <prop-encoded array>
+	Definition: multiple entries specifying the interrupts from QSEE
+
+- interrupt-names:
+	Usage: required
+	Value type: <string>
+	Definition: Interrupt names should be one of the following to map the
+		    interrupt back to the correct registers.
+		    - sp_ipc%d
+		    - sp_rmb
+
+- interrupt-controller:
+	Usage: required
+	Value type: <empty>
+	Definition: Identifies this node as an interrupt controller
+
+- #interrupt-cells
+	Usage: required
+	Value type: <u32>
+	Definition: must be 3 - for interrupts to encode these properties:
+		    - u32 denoting index of desired interrupt in @interrupts
+		    - u32 denoting bit of interrupt bank
+		    - u32 denoting IRQ flags
+
+= EXAMPLE
+The following example shows the QSEE_IRQ setup with the GLINK SPSS node, defined
+from the sm8150 apps processor's point-of-view. In this example the GLINK node
+registers for the sp_ipc0 interrupt(index 0 in interrupt-names) and the 0th
+bit on the sp_ipc0 interrupt bank.
+
+sp_scsr_block: syscon@1880000 {
+	compatible = “syscon”;
+	reg = <0x1880000 0x10000>;
+};
+
+intsp: qcom,qsee_irq {
+	compatible = "qcom,sm8150-qsee-irq";
+
+	syscon = <&sp_scsr_block>;
+	interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>,
+		     <0 349 IRQ_TYPE_LEVEL_HIGH>;
+
+	interrupt-names = "sp_ipc0",
+			  "sp_ipc1";
+
+	interrupt-controller;
+	#interrupt-cells = <3>;
+};
+
+spss {
+	...
+	glink {
+		qcom,remote-pid = <8>;
+		mboxes = <&sp_scsr 0>;
+		mbox-names = "spss_spss";
+		interrupts = <&intsp 0 0 IRQ_TYPE_EDGE_RISING>;
+	};
+};
+