mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 03:27:44 -04:00
Merge branch 'topic/asoc' into for-linus
Conflicts: arch/powerpc/platforms/85xx/p1022_ds.c
This commit is contained in:
Takashi Iwai
commit
aa5c14d5c0
380 changed files with 31455 additions and 16117 deletions
|
|
@ -286,6 +286,7 @@
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|||
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ssi@16100 {
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compatible = "fsl,mpc8610-ssi";
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status = "disabled";
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cell-index = <1>;
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reg = <0x16100 0x100>;
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interrupt-parent = <&mpic>;
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|
|
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@ -124,6 +124,9 @@ CONFIG_I2C_CPM=m
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CONFIG_I2C_MPC=y
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# CONFIG_HWMON is not set
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CONFIG_VIDEO_OUTPUT_CONTROL=y
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CONFIG_FB=y
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CONFIG_FB_FSL_DIU=y
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# CONFIG_VGA_CONSOLE is not set
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CONFIG_SOUND=y
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CONFIG_SND=y
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# CONFIG_SND_SUPPORT_OLD_API is not set
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|
|
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@ -126,6 +126,9 @@ CONFIG_I2C_CPM=m
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CONFIG_I2C_MPC=y
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# CONFIG_HWMON is not set
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CONFIG_VIDEO_OUTPUT_CONTROL=y
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CONFIG_FB=y
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CONFIG_FB_FSL_DIU=y
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# CONFIG_VGA_CONSOLE is not set
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CONFIG_SOUND=y
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CONFIG_SND=y
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# CONFIG_SND_SUPPORT_OLD_API is not set
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@ -1,5 +1,5 @@
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/**
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* MPC86xx Internal Memory Map
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* Freecale 85xx and 86xx Global Utilties register set
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*
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* Authors: Jeff Brown
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* Timur Tabi <timur@freescale.com>
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@ -10,73 +10,112 @@
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This header file defines structures for various 86xx SOC devices that are
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* used by multiple source files.
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*/
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#ifndef __ASM_POWERPC_IMMAP_86XX_H__
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#define __ASM_POWERPC_IMMAP_86XX_H__
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#ifndef __ASM_POWERPC_FSL_GUTS_H__
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#define __ASM_POWERPC_FSL_GUTS_H__
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#ifdef __KERNEL__
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/* Global Utility Registers */
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struct ccsr_guts {
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/*
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* These #ifdefs are safe because it's not possible to build a kernel that
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* runs on e500 and e600 cores.
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*/
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#if !defined(CONFIG_PPC_85xx) && !defined(CONFIG_PPC_86xx)
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#error Only 85xx and 86xx SOCs are supported
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#endif
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/**
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* Global Utility Registers.
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*
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* Not all registers defined in this structure are available on all chips, so
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* you are expected to know whether a given register actually exists on your
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* chip before you access it.
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*
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* Also, some registers are similar on different chips but have slightly
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* different names. In these cases, one name is chosen to avoid extraneous
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* #ifdefs.
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*/
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#ifdef CONFIG_PPC_85xx
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struct ccsr_guts_85xx {
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#else
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struct ccsr_guts_86xx {
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#endif
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__be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
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__be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
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__be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
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__be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
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__be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
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u8 res1[0x20 - 0x14];
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__be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
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u8 res018[0x20 - 0x18];
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__be32 porcir; /* 0x.0020 - POR Configuration Information Register */
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u8 res2[0x30 - 0x24];
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u8 res024[0x30 - 0x24];
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__be32 gpiocr; /* 0x.0030 - GPIO Control Register */
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u8 res3[0x40 - 0x34];
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u8 res034[0x40 - 0x34];
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__be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
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u8 res4[0x50 - 0x44];
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u8 res044[0x50 - 0x44];
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__be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
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u8 res5[0x60 - 0x54];
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u8 res054[0x60 - 0x54];
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__be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
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u8 res6[0x70 - 0x64];
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__be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
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__be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
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u8 res06c[0x70 - 0x6c];
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__be32 devdisr; /* 0x.0070 - Device Disable Control */
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__be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
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u8 res7[0x80 - 0x78];
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u8 res078[0x7c - 0x78];
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__be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
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__be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
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u8 res8[0x90 - 0x84];
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__be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
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__be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
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__be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
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__be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
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__be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
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u8 res9[0xA0 - 0x98];
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__be32 ectrstcr; /* 0x.0098 - Exception reset control register */
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__be32 autorstsr; /* 0x.009c - Automatic reset status register */
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__be32 pvr; /* 0x.00a0 - Processor Version Register */
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__be32 svr; /* 0x.00a4 - System Version Register */
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u8 res10[0xB0 - 0xA8];
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u8 res0a8[0xb0 - 0xa8];
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__be32 rstcr; /* 0x.00b0 - Reset Control Register */
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u8 res11[0xC0 - 0xB4];
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u8 res0b4[0xc0 - 0xb4];
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#ifdef CONFIG_PPC_85xx
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__be32 iovselsr; /* 0x.00c0 - I/O voltage select status register */
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#else
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__be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */
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u8 res12[0x800 - 0xC4];
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#endif
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u8 res0c4[0x224 - 0xc4];
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__be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
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__be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
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u8 res22c[0x800 - 0x22c];
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__be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
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u8 res13[0x900 - 0x804];
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u8 res804[0x900 - 0x804];
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__be32 ircr; /* 0x.0900 - Infrared Control Register */
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u8 res14[0x908 - 0x904];
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u8 res904[0x908 - 0x904];
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__be32 dmacr; /* 0x.0908 - DMA Control Register */
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u8 res15[0x914 - 0x90C];
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u8 res90c[0x914 - 0x90c];
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__be32 elbccr; /* 0x.0914 - eLBC Control Register */
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u8 res16[0xB20 - 0x918];
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u8 res918[0xb20 - 0x918];
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__be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
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__be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
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__be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
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u8 res17[0xE00 - 0xB2C];
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u8 resb2c[0xe00 - 0xb2c];
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__be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
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u8 res18[0xE10 - 0xE04];
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u8 rese04[0xe10 - 0xe04];
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__be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
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u8 res19[0xE20 - 0xE14];
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u8 rese14[0xe20 - 0xe14];
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__be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
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u8 res20[0xF04 - 0xE24];
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__be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
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u8 rese28[0xf04 - 0xe28];
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__be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
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__be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
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u8 res21[0xF40 - 0xF0C];
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__be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */
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__be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */
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u8 resf0c[0xf2c - 0xf0c];
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__be32 itcr; /* 0x.0f2c - Internal transaction control register */
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u8 resf30[0xf40 - 0xf30];
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__be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
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__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
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} __attribute__ ((packed));
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#ifdef CONFIG_PPC_86xx
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#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
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#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
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@ -93,7 +132,7 @@ struct ccsr_guts {
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* ch: The channel on the DMA controller (0, 1, 2, or 3)
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* device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
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*/
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static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
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static inline void guts_set_dmacr(struct ccsr_guts_86xx __iomem *guts,
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unsigned int co, unsigned int ch, unsigned int device)
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{
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unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
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@ -129,7 +168,7 @@ static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
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* ch: The channel on the DMA controller (0, 1, 2, or 3)
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* value: the new value for the bit (0 or 1)
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*/
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static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
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static inline void guts_set_pmuxcr_dma(struct ccsr_guts_86xx __iomem *guts,
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unsigned int co, unsigned int ch, unsigned int value)
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{
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if ((ch == 0) || (ch == 3)) {
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@ -152,5 +191,7 @@ static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
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#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
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#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
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#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
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#endif /* __KERNEL__ */
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#endif
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#endif
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#endif
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@ -8,7 +8,6 @@
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This file is taken from the Freescale P1022DS BSP, with modifications:
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* 1) No DIU support (pending rewrite of DIU code)
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* 2) No AMP support
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* 3) No PCI endpoint support
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*
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@ -20,12 +19,211 @@
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#include <linux/pci.h>
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#include <linux/of_platform.h>
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#include <linux/memblock.h>
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#include <asm/div64.h>
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#include <asm/mpic.h>
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#include <asm/swiotlb.h>
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|
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <asm/fsl_guts.h>
|
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|
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
|
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|
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/*
|
||||
* Board-specific initialization of the DIU. This code should probably be
|
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* executed when the DIU is opened, rather than in arch code, but the DIU
|
||||
* driver does not have a mechanism for this (yet).
|
||||
*
|
||||
* This is especially problematic on the P1022DS because the local bus (eLBC)
|
||||
* and the DIU video signals share the same pins, which means that enabling the
|
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* DIU will disable access to NOR flash.
|
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*/
|
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|
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/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
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#define CLKDVDR_PXCKEN 0x80000000
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#define CLKDVDR_PXCKINV 0x10000000
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#define CLKDVDR_PXCKDLY 0x06000000
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#define CLKDVDR_PXCLK_MASK 0x00FF0000
|
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|
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/* Some ngPIXIS register definitions */
|
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#define PX_BRDCFG1_DVIEN 0x80
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#define PX_BRDCFG1_DFPEN 0x40
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#define PX_BRDCFG1_BACKLIGHT 0x20
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#define PX_BRDCFG1_DDCEN 0x10
|
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|
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/*
|
||||
* DIU Area Descriptor
|
||||
*
|
||||
* Note that we need to byte-swap the value before it's written to the AD
|
||||
* register. So even though the registers don't look like they're in the same
|
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* bit positions as they are on the MPC8610, the same value is written to the
|
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* AD register on the MPC8610 and on the P1022.
|
||||
*/
|
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#define AD_BYTE_F 0x10000000
|
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#define AD_ALPHA_C_MASK 0x0E000000
|
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#define AD_ALPHA_C_SHIFT 25
|
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#define AD_BLUE_C_MASK 0x01800000
|
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#define AD_BLUE_C_SHIFT 23
|
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#define AD_GREEN_C_MASK 0x00600000
|
||||
#define AD_GREEN_C_SHIFT 21
|
||||
#define AD_RED_C_MASK 0x00180000
|
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#define AD_RED_C_SHIFT 19
|
||||
#define AD_PALETTE 0x00040000
|
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#define AD_PIXEL_S_MASK 0x00030000
|
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#define AD_PIXEL_S_SHIFT 16
|
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#define AD_COMP_3_MASK 0x0000F000
|
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#define AD_COMP_3_SHIFT 12
|
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#define AD_COMP_2_MASK 0x00000F00
|
||||
#define AD_COMP_2_SHIFT 8
|
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#define AD_COMP_1_MASK 0x000000F0
|
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#define AD_COMP_1_SHIFT 4
|
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#define AD_COMP_0_MASK 0x0000000F
|
||||
#define AD_COMP_0_SHIFT 0
|
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|
||||
#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
|
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cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
|
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(blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
|
||||
(red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
|
||||
(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
|
||||
(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
|
||||
|
||||
/**
|
||||
* p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
|
||||
*
|
||||
* The Area Descriptor is a 32-bit value that determine which bits in each
|
||||
* pixel are to be used for each color.
|
||||
*/
|
||||
static unsigned int p1022ds_get_pixel_format(unsigned int bits_per_pixel,
|
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int monitor_port)
|
||||
{
|
||||
switch (bits_per_pixel) {
|
||||
case 32:
|
||||
/* 0x88883316 */
|
||||
return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
|
||||
case 24:
|
||||
/* 0x88082219 */
|
||||
return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
|
||||
case 16:
|
||||
/* 0x65053118 */
|
||||
return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
|
||||
default:
|
||||
pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* p1022ds_set_gamma_table: update the gamma table, if necessary
|
||||
*
|
||||
* On some boards, the gamma table for some ports may need to be modified.
|
||||
* This is not the case on the P1022DS, so we do nothing.
|
||||
*/
|
||||
static void p1022ds_set_gamma_table(int monitor_port, char *gamma_table_base)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* p1022ds_set_monitor_port: switch the output to a different monitor port
|
||||
*
|
||||
*/
|
||||
static void p1022ds_set_monitor_port(int monitor_port)
|
||||
{
|
||||
struct device_node *pixis_node;
|
||||
u8 __iomem *brdcfg1;
|
||||
|
||||
pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
|
||||
if (!pixis_node) {
|
||||
pr_err("p1022ds: missing ngPIXIS node\n");
|
||||
return;
|
||||
}
|
||||
|
||||
brdcfg1 = of_iomap(pixis_node, 0);
|
||||
if (!brdcfg1) {
|
||||
pr_err("p1022ds: could not map ngPIXIS registers\n");
|
||||
return;
|
||||
}
|
||||
brdcfg1 += 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */
|
||||
|
||||
switch (monitor_port) {
|
||||
case 0: /* DVI */
|
||||
/* Enable the DVI port, disable the DFP and the backlight */
|
||||
clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT,
|
||||
PX_BRDCFG1_DVIEN);
|
||||
break;
|
||||
case 1: /* Single link LVDS */
|
||||
/* Enable the DFP port, disable the DVI and the backlight */
|
||||
clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT,
|
||||
PX_BRDCFG1_DFPEN);
|
||||
break;
|
||||
default:
|
||||
pr_err("p1022ds: unsupported monitor port %i\n", monitor_port);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* p1022ds_set_pixel_clock: program the DIU's clock
|
||||
*
|
||||
* @pixclock: the wavelength, in picoseconds, of the clock
|
||||
*/
|
||||
void p1022ds_set_pixel_clock(unsigned int pixclock)
|
||||
{
|
||||
struct device_node *guts_np = NULL;
|
||||
struct ccsr_guts_85xx __iomem *guts;
|
||||
unsigned long freq;
|
||||
u64 temp;
|
||||
u32 pxclk;
|
||||
|
||||
/* Map the global utilities registers. */
|
||||
guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
|
||||
if (!guts_np) {
|
||||
pr_err("p1022ds: missing global utilties device node\n");
|
||||
return;
|
||||
}
|
||||
|
||||
guts = of_iomap(guts_np, 0);
|
||||
of_node_put(guts_np);
|
||||
if (!guts) {
|
||||
pr_err("p1022ds: could not map global utilties device\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Convert pixclock from a wavelength to a frequency */
|
||||
temp = 1000000000000ULL;
|
||||
do_div(temp, pixclock);
|
||||
freq = temp;
|
||||
|
||||
/* pixclk is the ratio of the platform clock to the pixel clock */
|
||||
pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
|
||||
|
||||
/* Disable the pixel clock, and set it to non-inverted and no delay */
|
||||
clrbits32(&guts->clkdvdr,
|
||||
CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
|
||||
|
||||
/* Enable the clock and set the pxclk */
|
||||
setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
|
||||
}
|
||||
|
||||
/**
|
||||
* p1022ds_show_monitor_port: show the current monitor
|
||||
*
|
||||
* This function returns a string indicating whether the current monitor is
|
||||
* set to DVI or LVDS.
|
||||
*/
|
||||
ssize_t p1022ds_show_monitor_port(int monitor_port, char *buf)
|
||||
{
|
||||
return sprintf(buf, "%c0 - DVI\n%c1 - Single link LVDS\n",
|
||||
monitor_port == 0 ? '*' : ' ', monitor_port == 1 ? '*' : ' ');
|
||||
}
|
||||
|
||||
/**
|
||||
* p1022ds_set_sysfs_monitor_port: set the monitor port for sysfs
|
||||
*/
|
||||
int p1022ds_set_sysfs_monitor_port(int val)
|
||||
{
|
||||
return val < 2 ? val : 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void __init p1022_ds_pic_init(void)
|
||||
{
|
||||
|
|
@ -92,6 +290,15 @@ static void __init p1022_ds_setup_arch(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
|
||||
diu_ops.get_pixel_format = p1022ds_get_pixel_format;
|
||||
diu_ops.set_gamma_table = p1022ds_set_gamma_table;
|
||||
diu_ops.set_monitor_port = p1022ds_set_monitor_port;
|
||||
diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
|
||||
diu_ops.show_monitor_port = p1022ds_show_monitor_port;
|
||||
diu_ops.set_sysfs_monitor_port = p1022ds_set_sysfs_monitor_port;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
mpc85xx_smp_init();
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue