From aa7d071da6b32cb64424e70f4bb7f5e9046291c8 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Wed, 29 Jul 2020 16:03:18 -0700 Subject: [PATCH] clk: qcom: gcc-lahaina: Enable clocks for pm8008 by default The pm8008 regulator is connected over I2C and the I2C device configures its clocks in runtime_resume and runtime_suspend. These callbacks are triggered from the pm8008 driver's regmap calls. This means regulator framework requests for pm8008 call into the clock framework with the regulator framework locks held. The qcom clock providers also call into the regulator framework with the clock framework locks held. If thread A makes a pm8008 request at the same time thread B makes a clock request, then it can result in deadlocks. Thread A will be stuck waiting on the clock locks while thread B is stuck waiting on the regulator locks. To prevent these deadlocks, enable the I2C clocks required for pm8008 by default during probe and stop registering them with the framework. This NOPs any client requests, since of_clk_get() returns NULL when passed an unregistered clock and all other clock APIs return success before grabbing any locks when passed NULL. Change-Id: If308d3dab36a1ef9650256a0343789c2aaf56930 Signed-off-by: Mike Tipton --- drivers/clk/qcom/gcc-lahaina.c | 65 ++++++++-------------------------- 1 file changed, 14 insertions(+), 51 deletions(-) diff --git a/drivers/clk/qcom/gcc-lahaina.c b/drivers/clk/qcom/gcc-lahaina.c index eab1d53fe5ad..524cddcf5845 100644 --- a/drivers/clk/qcom/gcc-lahaina.c +++ b/drivers/clk/qcom/gcc-lahaina.c @@ -2979,24 +2979,6 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { }, }; -static struct clk_branch gcc_qupv3_wrap1_s5_clk = { - .halt_reg = 0x185fc, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { .halt_reg = 0x23278, .halt_check = BRANCH_HALT_VOTED, @@ -3161,36 +3143,6 @@ static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { }, }; -static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { - .halt_reg = 0x18004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x18004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(20), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { - .halt_reg = 0x18008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x18008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { .halt_reg = 0x1e004, .halt_check = BRANCH_HALT_VOTED, @@ -4178,7 +4130,6 @@ static struct clk_regmap *gcc_lahaina_clocks[] = { [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, - [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, @@ -4196,8 +4147,6 @@ static struct clk_regmap *gcc_lahaina_clocks[] = { [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, @@ -4422,6 +4371,20 @@ static int gcc_lahaina_probe(struct platform_device *pdev) regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); + /* + * Enable clocks required by the i2c-connected pm8008 regulators. Don't + * register them with the clock framework so that client requests are + * short-circuited before grabbing the enable/prepare locks. This + * prevents deadlocks between the clk/regulator frameworks. + * + * gcc_qupv3_wrap_1_m_ahb_clk + * gcc_qupv3_wrap_1_s_ahb_clk + * gcc_qupv3_wrap1_s5_clk + */ + regmap_update_bits(regmap, 0x52008, BIT(20), BIT(20)); + regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); + regmap_update_bits(regmap, 0x52008, BIT(27), BIT(27)); + ret = qcom_cc_really_probe(pdev, &gcc_lahaina_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register GCC clocks\n");