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Merge "dt-bindings: qcom-sps-dma: Add snapshot of SPS DMA driver"
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42
bindings/dma/qcom-sps-dma.txt
Normal file
42
bindings/dma/qcom-sps-dma.txt
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* Qualcomm technologies inc, DMA engine driver for BAM (Bus Access Manager).
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Required properties:
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- compatible: Should be "qcom,sps-dma".
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- reg: Should contain DMA registers location and length. This should include
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all of the per-channel registers.
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- interrupts: Should contain the BAM interrupt number.
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- qcom,summing-threshold: Should contain the BAM event threshold of
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the sum of descriptors' sizes in bytes.
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Optional properties:
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- qcom,managed-locally : Use when BAM global device control is managed locally
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by the application processor.
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Example:
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dma_blsp1: qcom,sps-dma@f9904000 { /* BLSP1 */
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#dma-cells = <4>;
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compatible = "qcom,sps-dma";
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reg = <0xf9904000 0x19000>;
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interrupts = <0 238 0>;
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qcom,summing-threshold = <10>;
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};
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DMA clients connected to the qcom-sps-dma DMA controller must use the format
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described in the dma.txt file, using a five-cell specifier for each channel,
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a phandle plus four integer cells, as shown below:
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dmas = <[phandle of the dma controller] [pipe index] [number of descriptors]
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[sps_connect flags] [sps_register_event flags]>;
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Example:
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i2c_2: i2c@f9924000 { /* BLSP1 QUP2 */
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.
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.
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.
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/* <&phandle pipe-idx n-descs connect-flags event-flags> */
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dmas = <&dma_blsp1 14 32 0x20000020 0x20>,
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<&dma_blsp1 15 64 0x20000020 0x20>;
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dma-names = "tx", "rx";
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};
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120
bindings/serial/msm_serial_hs.txt
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120
bindings/serial/msm_serial_hs.txt
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* Qualcomm Technologies Inc, BLSP MSM HSUART
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Required properties:
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- compatible :
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- "qcom,msm-hsuart-v14" to be used for UARTDM Core v1.4
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- reg : offset and length of the register set for both the device,
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uart core and bam core
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- reg-names :
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- "core_mem" to be used as name of the uart core
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- "bam_mem" to be used as name of the bam core
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- interrupts : interrupts for both the device,uart core and bam core
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- interrupt-names :
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- "core_irq" to be used as uart irq
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- "bam irq" to be used as bam irq
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- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
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source. The type shall be a <u32> and the value shall be 1
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- #address-cells: Specifies the number of cells needed to encode an address.
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The type shall be <u32> and the value shall be 0
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- interrupt-parent = It is needed for interrupt mapping
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- bam-tx-ep-pipe-index : BAM TX Endpoint Pipe Index for HSUART
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- bam-rx-ep-pipe-index : BAM RX Endpoint Pipe Index for HSUART
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BLSP has a static pipe allocation and assumes a pair-pipe for each uart core.
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Pipes [2*i : 2*i+1] are allocated for UART cores where i = [0 : 5].
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Hence, Minimum and Maximum permitted value of endpoint pipe index to be used
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with uart core is 0 and 11 respectively.
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There is one HSUART block used in MSM devices,
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"qcom,msm-hsuart-v14". The msm-serial-hs driver is
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able to handle this, and matches against the "qcom,msm-hsuart-v14"
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as the compatibility.
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The registers for the "qcom,msm-hsuart-v14" device need to specify both
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register blocks - uart core and bam core.
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Example:
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uart7: uart@f995d000 {
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compatible = "qcom,msm-hsuart-v14";
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reg = <0xf995d000 0x1000>,
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<0xf9944000 0x5000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq";
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#address-cells = <0>;
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interrupt-parent = <&uart7>;
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interrupts = <0 1>;
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#interrupt-cells = <1>;
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interrupt-map = <0 &intc 0 113 0
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1 &intc 0 239 0>
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qcom,bam-tx-ep-pipe-index = <0>;
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qcom,bam-rx-ep-pipe-index = <1>;
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};
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Optional properties:
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- qcom,<gpio-name>-gpio : handle to the GPIO node, see "gpios property" in
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Documentation/devicetree/bindings/gpio/gpio.txt.
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"gpio-name" can be "tx", "rx", "cts" and "rfr" based on number of UART GPIOs
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need to configured.
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Gpio's are optional if it is required to be not configured by UART driver or
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case where there is nothing connected and we want to use internal loopback mode
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for uart.
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- qcom, wakeup_irq : UART RX GPIO IRQ line to be configured as wakeup source.
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- qcom,inject-rx-on-wakeup : inject_rx_on_wakeup enables feature where on
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receiving interrupt with UART RX GPIO IRQ line (i.e. above wakeup_irq property),
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HSUART driver injects provided character with property rx_to_inject.
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- qcom, rx-char-to-inject : The character to be inserted on wakeup.
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- qcom, no-suspend-delay : This decides system to go to suspend immediately
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or not
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- interconnects: pairs of phandles and interconnect provider specifier
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to denote the edge source and destination ports of
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the interconnect path. Please refer to
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Documentation/devicetree/bindings/interconnect/
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for more details.
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- interconnect-names: List of interconnect path name strings sorted in the same
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order as the interconnects property. Consumers drivers will use
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interconnect-names to match interconnect paths with interconnect
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specifiers. Please refer to Documentation/devicetree/bindings/
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interconnect/ for more details.
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Aliases :
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An alias may be optionally used to bind the UART device to a TTY device
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(ttyHS<alias_num>) with a given alias number. Aliases are of the form
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uart<n> where <n> is an integer representing the alias number to use.
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On systems with multiple UART devices present, an alias may optionally be
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defined for such devices. The alias value should be from 0 to 255.
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Example:
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aliases {
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uart4 = &uart7; // This device will be enumerated as ttyHS4
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};
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uart7: uart@f995d000 {
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compatible = "qcom,msm-hsuart-v14"
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reg = <0x19c40000 0x1000">,
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<0xf9944000 0x5000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&uart7>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 113 0
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1 &intc 0 239 0
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2 &msmgpio 42 0>;
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qcom,tx-gpio = <&msmgpio 41 0x00>;
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qcom,rx-gpio = <&msmgpio 42 0x00>;
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qcom,cts-gpio = <&msmgpio 43 0x00>;
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qcom,rfr-gpio = <&msmgpio 44 0x00>;
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qcom,inject-rx-on-wakeup = <1>;
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qcom,rx-char-to-inject = <0xFD>;
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qcom,bam-tx-ep-pipe-index = <0>;
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qcom,bam-rx-ep-pipe-index = <1>;
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interconnect-names = "blsp-ddr";
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interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
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};
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