From aa872263c7410e9b647de44bc52e7224445ab1de Mon Sep 17 00:00:00 2001
From: Murali Nalajala <mnalajal@quicinc.com>
Date: Mon, 29 Jul 2019 14:09:08 -0700
Subject: [PATCH] ARM: dts: msm: Add edac node for Lahaina SoC

Add edac node with compatibility of arm,arm64-kryo-cpu-erp,
to enable error reporting capability for L1/L2 & L3 memories
on Lahaina SoC.

Change-Id: Id561334e40c0aaf04348db90df4a30252ded2432
---
 qcom/lahaina.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index 10fcbb2025a9..a1fb72c58381 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -612,6 +612,13 @@
 
 		status = "disabled";
 	};
+
+	kryo-erp {
+		compatible = "arm,arm64-kryo-cpu-erp";
+		interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
+	};
 };
 
 #include "lahaina-pinctrl.dtsi"