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ARM: dts: msm: Add l3 endpoints and pwrlevels for gpu

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Add the l3 endpoints as well as the frequency table to be
able to vote for l3 for gpu usecases that need l3 scaling.

Change-Id: If1398e4554c83b32cfc31a5609e9c237883003fb
This commit is contained in:
Harshdeep Dhatt 2020-06-02 15:20:31 -06:00
commit aaeb47fada
2 changed files with 47 additions and 2 deletions
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27
qcom/lahaina-gpu.dtsi
View file

@ -57,8 +57,9 @@
qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
interconnect-names = "gpu_icc_path";
interconnect-names = "gpu_icc_path", "l3_path";
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>,
<&epss_l3_cpu MASTER_EPSS_L3_APPS &epss_l3_cpu SLAVE_EPSS_L3_SHARED>;
qcom,bus-table-ddr7 =
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
@ -93,6 +94,28 @@
<0>, /* Off */
<100>; /* On */
qcom,l3-pwrlevels {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,l3-pwrlevels";
qcom,l3-pwrlevel@0 {
reg = <0>;
qcom,l3-freq = <0>;
};
qcom,l3-pwrlevel@1 {
reg = <1>;
qcom,l3-freq = <614400000>;
};
qcom,l3-pwrlevel@2 {
reg = <2>;
qcom,l3-freq = <1516800000>;
};
};
qcom,gpu-mempools {
#address-cells = <1>;
#size-cells = <0>;

22
qcom/lahaina-v2-gpu.dtsi
View file

@ -4,6 +4,28 @@
/delete-property/qcom,initial-pwrlevel;
/delete-node/qcom,gpu-pwrlevels;
qcom,l3-pwrlevels {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,l3-pwrlevels";
qcom,l3-pwrlevel@0 {
reg = <0>;
qcom,l3-freq = <0>;
};
qcom,l3-pwrlevel@1 {
reg = <1>;
qcom,l3-freq = <614400000>;
};
qcom,l3-pwrlevel@2 {
reg = <2>;
qcom,l3-freq = <1593600000>;
};
};
/* Power levels bins */
qcom,gpu-pwrlevel-bins {
compatible="qcom,gpu-pwrlevel-bins";