From ab0460954f6aa97e99aaf39608cbdebc97b341eb Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 9 Mar 2021 18:19:44 -0800 Subject: [PATCH] ARM: dts: msm: update PCIe LTR value to 150us for sdxlemur On sdxlemur, PCIe L1.2 exit is about 150us. Therefore update PCIe so that it will program all PCI devices LTR register with 150us. Devices can use this value to deterine if L1.2 should be entered or not based on their latency requirement. Change-Id: Ife11959879bd7c09b9cbe256b5e46933124ad6b1 --- qcom/sdxlemur-mtp-mbb.dtsi | 2 -- qcom/sdxlemur-pcie.dtsi | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index a88fe19912ae..b0249a0ff28d 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -30,8 +30,6 @@ &pcie0 { qcom,boot-option = <0x1>; - qcom,l1-2-th-scale = <2>; /* 1us */ - qcom,l1-2-th-value = <70>; }; &pm7250b_vadc { diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index b433831ef634..9834159a1112 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -109,6 +109,8 @@ <0x100 &apps_smmu 0x0201 0x1>; qcom,aux-clk-freq = <17>; /* 16.6 MHz */ + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <150>; qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>;