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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge git://git.infradead.org/mtd-2.6
* git://git.infradead.org/mtd-2.6: (59 commits) mtd: mtdpart: disallow reading OOB past the end of the partition mtd: pxa3xx_nand: NULL dereference in pxa3xx_nand_probe UBI: use mtd->writebufsize to set minimal I/O unit size mtd: initialize writebufsize in the MTD object of a partition mtd: onenand: add mtd->writebufsize initialization mtd: nand: add mtd->writebufsize initialization mtd: cfi: add writebufsize initialization mtd: add writebufsize field to mtd_info struct mtd: OneNAND: OMAP2/3: prevent regulator sleeping while OneNAND is in use mtd: OneNAND: add enable / disable methods to onenand_chip mtd: m25p80: Fix JEDEC ID for AT26DF321 mtd: txx9ndfmc: limit transfer bytes to 512 (ECC provides 6 bytes max) mtd: cfi_cmdset_0002: add support for Samsung K8D3x16UxC NOR chips mtd: cfi_cmdset_0002: add support for Samsung K8D6x16UxM NOR chips mtd: nand: ams-delta: drop omap_read/write, use ioremap mtd: m25p80: add debugging trace in sst_write mtd: nand: ams-delta: select for built-in by default mtd: OneNAND: lighten scary initial bad block messages mtd: OneNAND: OMAP2/3: add support for command line partitioning mtd: nand: rearrange ONFI revision checking, add ONFI 2.3 ... Fix up trivial conflict in drivers/mtd/Kconfig as per DavidW.
This commit is contained in:
commit
ab2020f2f1
50 changed files with 595 additions and 351 deletions
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@ -527,8 +527,7 @@ struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t s
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struct cfi_fixup {
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uint16_t mfr;
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uint16_t id;
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void (*fixup)(struct mtd_info *mtd, void* param);
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void* param;
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void (*fixup)(struct mtd_info *mtd);
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};
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#define CFI_MFR_ANY 0xFFFF
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@ -16,6 +16,7 @@
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#ifndef __MTD_FSMC_H
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#define __MTD_FSMC_H
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/types.h>
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@ -27,7 +28,7 @@
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/*
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* The placement of the Command Latch Enable (CLE) and
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* Address Latch Enable (ALE) is twised around in the
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* Address Latch Enable (ALE) is twisted around in the
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* SPEAR310 implementation.
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*/
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#if defined(CONFIG_MACH_SPEAR310)
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@ -62,7 +63,7 @@ struct fsmc_nor_bank_regs {
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/* ctrl_tim register definitions */
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struct fsms_nand_bank_regs {
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struct fsmc_nand_bank_regs {
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uint32_t pc;
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uint32_t sts;
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uint32_t comm;
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@ -78,7 +79,7 @@ struct fsms_nand_bank_regs {
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struct fsmc_regs {
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struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
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uint8_t reserved_1[0x40 - 0x20];
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struct fsms_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
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struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
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uint8_t reserved_2[0xfe0 - 0xc0];
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uint32_t peripid0; /* 0xfe0 */
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uint32_t peripid1; /* 0xfe4 */
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@ -114,25 +115,6 @@ struct fsmc_regs {
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#define FSMC_THOLD_4 (4 << 16)
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#define FSMC_THIZ_1 (1 << 24)
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/* peripid2 register definitions */
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#define FSMC_REVISION_MSK (0xf)
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#define FSMC_REVISION_SHFT (0x4)
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#define FSMC_VER1 1
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#define FSMC_VER2 2
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#define FSMC_VER3 3
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#define FSMC_VER4 4
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#define FSMC_VER5 5
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#define FSMC_VER6 6
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#define FSMC_VER7 7
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#define FSMC_VER8 8
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static inline uint32_t get_fsmc_version(struct fsmc_regs *regs)
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{
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return (readl(®s->peripid2) >> FSMC_REVISION_SHFT) &
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FSMC_REVISION_MSK;
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}
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/*
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* There are 13 bytes of ecc for every 512 byte block in FSMC version 8
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* and it has to be read consecutively and immediately after the 512
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@ -144,6 +144,17 @@ struct mtd_info {
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*/
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uint32_t writesize;
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/*
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* Size of the write buffer used by the MTD. MTD devices having a write
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* buffer can write multiple writesize chunks at a time. E.g. while
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* writing 4 * writesize bytes to a device with 2 * writesize bytes
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* buffer the MTD driver can (but doesn't have to) do 2 writesize
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* operations, but not 4. Currently, all NANDs have writebufsize
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* equivalent to writesize (NAND page size). Some NOR flashes do have
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* writebufsize greater than writesize.
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*/
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uint32_t writebufsize;
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uint32_t oobsize; // Amount of OOB data per block (e.g. 16)
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uint32_t oobavail; // Available OOB bytes per block
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@ -448,6 +448,8 @@ struct nand_buffers {
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* See the defines for further explanation.
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* @badblockpos: [INTERN] position of the bad block marker in the oob
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* area.
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* @badblockbits: [INTERN] number of bits to left-shift the bad block
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* number
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* @cellinfo: [INTERN] MLC/multichip data from chip ident
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* @numchips: [INTERN] number of physical chips
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* @chipsize: [INTERN] the size of one chip for multichip arrays
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@ -118,6 +118,8 @@ struct onenand_chip {
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int (*chip_probe)(struct mtd_info *mtd);
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int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
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int (*scan_bbt)(struct mtd_info *mtd);
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int (*enable)(struct mtd_info *mtd);
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int (*disable)(struct mtd_info *mtd);
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struct completion complete;
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int irq;
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@ -137,6 +139,14 @@ struct onenand_chip {
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void *bbm;
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void *priv;
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/*
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* Shows that the current operation is composed
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* of sequence of commands. For example, cache program.
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* Such command status OnGo bit is checked at the end of
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* sequence.
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*/
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unsigned int ongoing;
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};
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/*
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@ -171,6 +181,9 @@ struct onenand_chip {
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#define ONENAND_IS_2PLANE(this) (0)
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#endif
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#define ONENAND_IS_CACHE_PROGRAM(this) \
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(this->options & ONENAND_HAS_CACHE_PROGRAM)
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/* Check byte access in OneNAND */
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#define ONENAND_CHECK_BYTE_ACCESS(addr) (addr & 0x1)
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@ -181,6 +194,7 @@ struct onenand_chip {
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#define ONENAND_HAS_UNLOCK_ALL (0x0002)
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#define ONENAND_HAS_2PLANE (0x0004)
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#define ONENAND_HAS_4KB_PAGE (0x0008)
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#define ONENAND_HAS_CACHE_PROGRAM (0x0010)
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#define ONENAND_SKIP_UNLOCK_CHECK (0x0100)
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#define ONENAND_PAGEBUF_ALLOC (0x1000)
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#define ONENAND_OOBBUF_ALLOC (0x2000)
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@ -89,7 +89,7 @@ static inline int mtd_has_cmdlinepart(void) { return 1; }
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static inline int mtd_has_cmdlinepart(void) { return 0; }
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#endif
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int mtd_is_master(struct mtd_info *mtd);
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int mtd_is_partition(struct mtd_info *mtd);
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int mtd_add_partition(struct mtd_info *master, char *name,
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long long offset, long long length);
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int mtd_del_partition(struct mtd_info *master, int partno);
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