mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
mvebu SoC suspend changes for v3.19
- Armada 370/XP suspend/resume support
- mvebu SoC driver suspend/resume support
- irqchip
- clocksource
- mbus
- clk
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Merge tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu into next/soc
Pull "mvebu SoC suspend changes for v3.19" from Jason Cooper:
- Armada 370/XP suspend/resume support
- mvebu SoC driver suspend/resume support
- irqchip
- clocksource
- mbus
- clk
* tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller
Signed-off-by: Arnd Bergmann <[email protected]>
This commit is contained in:
Arnd Bergmann
commit
ab64920c37
18 changed files with 777 additions and 32 deletions
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@ -57,6 +57,7 @@
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#include <linux/of_address.h>
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#include <linux/debugfs.h>
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#include <linux/log2.h>
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#include <linux/syscore_ops.h>
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/*
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* DDR target is the same on all platforms.
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@ -94,20 +95,42 @@
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#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
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/* Relative to mbusbridge_base */
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#define MBUS_BRIDGE_CTRL_OFF 0x0
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#define MBUS_BRIDGE_BASE_OFF 0x4
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/* Maximum number of windows, for all known platforms */
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#define MBUS_WINS_MAX 20
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struct mvebu_mbus_state;
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struct mvebu_mbus_soc_data {
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unsigned int num_wins;
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unsigned int num_remappable_wins;
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bool has_mbus_bridge;
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unsigned int (*win_cfg_offset)(const int win);
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void (*setup_cpu_target)(struct mvebu_mbus_state *s);
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int (*save_cpu_target)(struct mvebu_mbus_state *s,
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u32 *store_addr);
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int (*show_cpu_target)(struct mvebu_mbus_state *s,
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struct seq_file *seq, void *v);
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};
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/*
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* Used to store the state of one MBus window accross suspend/resume.
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*/
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struct mvebu_mbus_win_data {
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u32 ctrl;
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u32 base;
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u32 remap_lo;
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u32 remap_hi;
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};
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struct mvebu_mbus_state {
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void __iomem *mbuswins_base;
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void __iomem *sdramwins_base;
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void __iomem *mbusbridge_base;
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phys_addr_t sdramwins_phys_base;
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struct dentry *debugfs_root;
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struct dentry *debugfs_sdram;
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struct dentry *debugfs_devs;
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@ -115,6 +138,11 @@ struct mvebu_mbus_state {
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struct resource pcie_io_aperture;
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const struct mvebu_mbus_soc_data *soc;
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int hw_io_coherency;
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/* Used during suspend/resume */
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u32 mbus_bridge_ctrl;
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u32 mbus_bridge_base;
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struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
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};
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static struct mvebu_mbus_state mbus_state;
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@ -516,6 +544,28 @@ mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
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mvebu_mbus_dram_info.num_cs = cs;
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}
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static int
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mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
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u32 *store_addr)
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{
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int i;
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for (i = 0; i < 4; i++) {
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u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
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u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
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writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
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store_addr++);
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writel(base, store_addr++);
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writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
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store_addr++);
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writel(size, store_addr++);
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}
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/* We've written 16 words to the store address */
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return 16;
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}
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static void __init
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mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
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{
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@ -546,10 +596,35 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
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mvebu_mbus_dram_info.num_cs = cs;
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}
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static int
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mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
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u32 *store_addr)
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{
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int i;
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for (i = 0; i < 2; i++) {
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u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
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writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
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store_addr++);
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writel(map, store_addr++);
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}
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/* We've written 4 words to the store address */
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return 4;
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}
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int mvebu_mbus_save_cpu_target(u32 *store_addr)
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{
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return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
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}
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static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
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.num_wins = 20,
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.num_remappable_wins = 8,
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.has_mbus_bridge = true,
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.win_cfg_offset = armada_370_xp_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -558,6 +633,7 @@ static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -566,6 +642,7 @@ static const struct mvebu_mbus_soc_data dove_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_dove_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_dove,
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};
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@ -578,6 +655,7 @@ static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 4,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -586,6 +664,7 @@ static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
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.num_wins = 8,
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.num_remappable_wins = 2,
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.win_cfg_offset = orion_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -594,6 +673,7 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
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.num_wins = 14,
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.num_remappable_wins = 8,
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.win_cfg_offset = mv78xx0_mbus_win_offset,
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.save_cpu_target = mvebu_mbus_default_save_cpu_target,
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.setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
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.show_cpu_target = mvebu_sdram_debug_show_orion,
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};
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@ -698,11 +778,73 @@ static __init int mvebu_mbus_debugfs_init(void)
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}
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fs_initcall(mvebu_mbus_debugfs_init);
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static int mvebu_mbus_suspend(void)
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{
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struct mvebu_mbus_state *s = &mbus_state;
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int win;
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if (!s->mbusbridge_base)
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return -ENODEV;
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for (win = 0; win < s->soc->num_wins; win++) {
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void __iomem *addr = s->mbuswins_base +
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s->soc->win_cfg_offset(win);
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s->wins[win].base = readl(addr + WIN_BASE_OFF);
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s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
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if (win >= s->soc->num_remappable_wins)
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continue;
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s->wins[win].remap_lo = readl(addr + WIN_REMAP_LO_OFF);
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s->wins[win].remap_hi = readl(addr + WIN_REMAP_HI_OFF);
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}
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s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
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MBUS_BRIDGE_CTRL_OFF);
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s->mbus_bridge_base = readl(s->mbusbridge_base +
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MBUS_BRIDGE_BASE_OFF);
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return 0;
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}
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static void mvebu_mbus_resume(void)
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{
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struct mvebu_mbus_state *s = &mbus_state;
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int win;
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writel(s->mbus_bridge_ctrl,
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s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
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writel(s->mbus_bridge_base,
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s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
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for (win = 0; win < s->soc->num_wins; win++) {
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void __iomem *addr = s->mbuswins_base +
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s->soc->win_cfg_offset(win);
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writel(s->wins[win].base, addr + WIN_BASE_OFF);
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writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
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if (win >= s->soc->num_remappable_wins)
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continue;
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writel(s->wins[win].remap_lo, addr + WIN_REMAP_LO_OFF);
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writel(s->wins[win].remap_hi, addr + WIN_REMAP_HI_OFF);
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}
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}
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struct syscore_ops mvebu_mbus_syscore_ops = {
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.suspend = mvebu_mbus_suspend,
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.resume = mvebu_mbus_resume,
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};
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static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
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phys_addr_t mbuswins_phys_base,
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size_t mbuswins_size,
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phys_addr_t sdramwins_phys_base,
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size_t sdramwins_size)
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size_t sdramwins_size,
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phys_addr_t mbusbridge_phys_base,
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size_t mbusbridge_size)
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{
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int win;
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@ -716,11 +858,26 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
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return -ENOMEM;
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}
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mbus->sdramwins_phys_base = sdramwins_phys_base;
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if (mbusbridge_phys_base) {
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mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
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mbusbridge_size);
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if (!mbus->mbusbridge_base) {
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iounmap(mbus->sdramwins_base);
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iounmap(mbus->mbuswins_base);
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return -ENOMEM;
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}
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} else
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mbus->mbusbridge_base = NULL;
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for (win = 0; win < mbus->soc->num_wins; win++)
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mvebu_mbus_disable_window(mbus, win);
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mbus->soc->setup_cpu_target(mbus);
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register_syscore_ops(&mvebu_mbus_syscore_ops);
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return 0;
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}
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@ -746,7 +903,7 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
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mbuswins_phys_base,
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mbuswins_size,
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sdramwins_phys_base,
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sdramwins_size);
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sdramwins_size, 0, 0);
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}
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#ifdef CONFIG_OF
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@ -887,7 +1044,7 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
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int __init mvebu_mbus_dt_init(bool is_coherent)
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{
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struct resource mbuswins_res, sdramwins_res;
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struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
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struct device_node *np, *controller;
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const struct of_device_id *of_id;
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const __be32 *prop;
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@ -923,6 +1080,19 @@ int __init mvebu_mbus_dt_init(bool is_coherent)
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return -EINVAL;
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}
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/*
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* Set the resource to 0 so that it can be left unmapped by
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* mvebu_mbus_common_init() if the DT doesn't carry the
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* necessary information. This is needed to preserve backward
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* compatibility.
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*/
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memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
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if (mbus_state.soc->has_mbus_bridge) {
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if (of_address_to_resource(controller, 2, &mbusbridge_res))
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pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
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}
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mbus_state.hw_io_coherency = is_coherent;
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/* Get optional pcie-{mem,io}-aperture properties */
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@ -933,7 +1103,9 @@ int __init mvebu_mbus_dt_init(bool is_coherent)
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mbuswins_res.start,
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resource_size(&mbuswins_res),
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sdramwins_res.start,
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resource_size(&sdramwins_res));
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resource_size(&sdramwins_res),
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mbusbridge_res.start,
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resource_size(&mbusbridge_res));
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if (ret)
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return ret;
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