mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 15:49:17 -04:00
Merge "ARM: dts: msm: Add LLCC PMU device nodes on Direwolf"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
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1 changed files with 404 additions and 0 deletions
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@ -9,6 +9,15 @@
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,direwolf.h>
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#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
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#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
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#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
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opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
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opp-supported-hw = <ddrtype>;}
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#define DDR_TYPE_LPDDR4X 7
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#define DDR_TYPE_LPDDR5 8
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/ {
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model = "Qualcomm Technologies, Inc. Direwolf";
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compatible = "qcom,direwolf";
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@ -1072,6 +1081,401 @@
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mbox-desc-offset = <0x0>;
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#mbox-cells = <1>;
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};
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llcc_pmu: llcc-pmu@9095000 {
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compatible = "qcom,llcc-pmu-ver2";
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reg = <0x09095000 0x300>;
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reg-names = "lagg-base";
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};
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llcc_bw_opp_table: llcc-bw-opp-table {
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compatible = "operating-points-v2";
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BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
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BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
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BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
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BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
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BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
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BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
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BW_OPP_ENTRY( 1000, 16); /* 15258 MB/s */
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};
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ddr_bw_opp_table: ddr-bw-opp-table {
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compatible = "operating-points-v2";
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BW_OPP_ENTRY_DDR( 200, 4, 0x80); /* 762 MB/s */
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BW_OPP_ENTRY_DDR( 451, 4, 0x80); /* 1720 MB/s */
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BW_OPP_ENTRY_DDR( 547, 4, 0x80); /* 2086 MB/s */
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BW_OPP_ENTRY_DDR( 681, 4, 0x80); /* 2597 MB/s */
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BW_OPP_ENTRY_DDR( 768, 4, 0x80); /* 2929 MB/s */
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BW_OPP_ENTRY_DDR( 1017, 4, 0x80); /* 3879 MB/s */
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BW_OPP_ENTRY_DDR( 1353, 4, 0x80); /* 5161 MB/s */
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BW_OPP_ENTRY_DDR( 1555, 4, 0x80); /* 5931 MB/s */
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BW_OPP_ENTRY_DDR( 1708, 4, 0x80); /* 6515 MB/s */
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BW_OPP_ENTRY_DDR( 2092, 4, 0x80); /* 7980 MB/s */
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BW_OPP_ENTRY_DDR( 2133, 4, 0x80); /* 8136 MB/s */
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BW_OPP_ENTRY_DDR( 2736, 4, 0x80); /* 10437 MB/s */
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BW_OPP_ENTRY_DDR( 3196, 4, 0x80); /* 12191 MB/s */
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};
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qoslat_opp_table: qoslat-opp-table {
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compatible = "operating-points-v2";
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opp-1 {
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opp-hz = /bits/ 64 < 1 >;
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};
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opp-2 {
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opp-hz = /bits/ 64 < 2 >;
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};
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};
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cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
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compatible = "qcom,devfreq-icc";
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governor = "performance";
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interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
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qcom,active-only;
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operating-points-v2 = <&llcc_bw_opp_table>;
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};
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cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
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compatible = "qcom,bimc-bwmon4";
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reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
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reg-names = "base", "global_base";
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interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
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qcom,mport = <0>;
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qcom,hw-timer-hz = <19200000>;
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qcom,target-dev = <&cpu_cpu_llcc_bw>;
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qcom,count-unit = <0x10000>;
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};
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cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "performance";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 {
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compatible = "qcom,bimc-bwmon5";
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reg = <0x9091000 0x1000>;
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reg-names = "base";
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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qcom,hw-timer-hz = <19200000>;
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qcom,target-dev = <&cpu_llcc_ddr_bw>;
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qcom,count-unit = <0x10000>;
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};
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cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "performance";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU0>;
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};
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cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "performance";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU1>;
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};
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cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "performance";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU2>;
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};
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cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "performance";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU3>;
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};
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cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "performance";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU4>;
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};
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cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "performance";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU5>;
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};
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cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "performance";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU6>;
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};
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cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat {
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compatible = "qcom,devfreq-icc-l3";
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reg = <0x18590100 0xa0>;
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reg-names = "ftbl-base";
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governor = "performance";
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interconnects =
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<&epss_l3_cpu MASTER_EPSS_L3_APPS
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&epss_l3_cpu SLAVE_EPSS_L3_CPU7>;
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};
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cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
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compatible = "qcom,devfreq-icc";
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governor = "performance";
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interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
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qcom,active-only;
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operating-points-v2 = <&llcc_bw_opp_table>;
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};
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cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {
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compatible = "qcom,devfreq-icc";
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governor = "performance";
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interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
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qcom,active-only;
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operating-points-v2 = <&llcc_bw_opp_table>;
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};
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cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "performance";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "performance";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
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compatible = "qcom,devfreq-icc-ddr";
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governor = "performance";
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interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
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||||
qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat {
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compatible = "qcom,devfreq-qoslat";
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governor = "powersave";
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operating-points-v2 = <&qoslat_opp_table>;
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};
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cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {
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qcom,core-dev-table =
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< 300000 300000000 >,
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< 403200 403200000 >,
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< 499200 499200000 >,
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< 691200 614400000 >,
|
||||
< 806400 710400000 >,
|
||||
< 998400 806400000 >,
|
||||
< 1190400 998400000 >,
|
||||
< 1286400 1094400000 >,
|
||||
< 1459200 1248000000 >,
|
||||
< 1728000 1344000000 >,
|
||||
< 1804800 1440000000 >,
|
||||
< 1900800 1516800000 >;
|
||||
};
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|
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cpu4_cpu_l3_tbl: qcom,cpu4-cpu-l3-tbl {
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qcom,core-dev-table =
|
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< 300000 300000000 >,
|
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< 787200 614400000 >,
|
||||
< 1209600 806400000 >,
|
||||
< 1497600 998400000 >,
|
||||
< 1689600 1248000000 >,
|
||||
< 1900800 1344000000 >,
|
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< 2188800 1440000000 >,
|
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< 2400000 1516800000 >;
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};
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cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
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compatible = "qcom,arm-memlat-cpugrp";
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
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cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU0>;
|
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qcom,target-dev = <&cpu0_cpu_l3_lat>;
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||||
qcom,cachemiss-ev = <0x17>;
|
||||
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
|
||||
};
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||||
cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU1>;
|
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qcom,target-dev = <&cpu1_cpu_l3_lat>;
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||||
qcom,cachemiss-ev = <0x17>;
|
||||
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
|
||||
};
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||||
cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon {
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||||
compatible = "qcom,arm-memlat-mon";
|
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qcom,cpulist = <&CPU2>;
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||||
qcom,target-dev = <&cpu2_cpu_l3_lat>;
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||||
qcom,cachemiss-ev = <0x17>;
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||||
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
|
||||
};
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||||
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cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU3>;
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||||
qcom,target-dev = <&cpu3_cpu_l3_lat>;
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||||
qcom,cachemiss-ev = <0x17>;
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||||
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
|
||||
};
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||||
|
||||
cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,target-dev = <&cpu0_cpu_llcc_lat>;
|
||||
qcom,cachemiss-ev = <0x2A>;
|
||||
qcom,core-dev-table =
|
||||
< 300000 MHZ_TO_MBPS( 150, 16) >,
|
||||
< 691200 MHZ_TO_MBPS( 300, 16) >,
|
||||
< 1459200 MHZ_TO_MBPS( 466, 16) >,
|
||||
< 1900800 MHZ_TO_MBPS( 600, 16) >;
|
||||
};
|
||||
|
||||
cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
|
||||
qcom,target-dev = <&cpu0_llcc_ddr_lat>;
|
||||
qcom,cachemiss-ev = <0x1000>;
|
||||
qcom,core-dev-table =
|
||||
< 300000 MHZ_TO_MBPS( 200, 4) >,
|
||||
< 691200 MHZ_TO_MBPS( 451, 4) >,
|
||||
< 1190400 MHZ_TO_MBPS( 547, 4) >,
|
||||
< 1459200 MHZ_TO_MBPS( 768, 4) >,
|
||||
< 1900800 MHZ_TO_MBPS( 1017, 4) >;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
|
||||
compatible = "qcom,arm-memlat-cpugrp";
|
||||
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
||||
|
||||
cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,cpulist = <&CPU4>;
|
||||
qcom,target-dev = <&cpu4_cpu_l3_lat>;
|
||||
qcom,cachemiss-ev = <0x17>;
|
||||
qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
|
||||
};
|
||||
|
||||
cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,cpulist = <&CPU5>;
|
||||
qcom,target-dev = <&cpu5_cpu_l3_lat>;
|
||||
qcom,cachemiss-ev = <0x17>;
|
||||
qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
|
||||
};
|
||||
|
||||
cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,cpulist = <&CPU6>;
|
||||
qcom,target-dev = <&cpu6_cpu_l3_lat>;
|
||||
qcom,cachemiss-ev = <0x17>;
|
||||
qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
|
||||
};
|
||||
|
||||
cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,cpulist = <&CPU7>;
|
||||
qcom,target-dev = <&cpu7_cpu_l3_lat>;
|
||||
qcom,cachemiss-ev = <0x17>;
|
||||
qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
|
||||
};
|
||||
|
||||
cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,target-dev = <&cpu4_cpu_llcc_lat>;
|
||||
qcom,cachemiss-ev = <0x2A>;
|
||||
qcom,core-dev-table =
|
||||
< 300000 MHZ_TO_MBPS( 150, 16) >,
|
||||
< 672000 MHZ_TO_MBPS( 300, 16) >,
|
||||
< 1017600 MHZ_TO_MBPS( 466, 16) >,
|
||||
< 1305600 MHZ_TO_MBPS( 600, 16) >,
|
||||
< 1804800 MHZ_TO_MBPS( 806, 16) >,
|
||||
< 2188800 MHZ_TO_MBPS( 933, 16) >,
|
||||
< 2400000 MHZ_TO_MBPS( 1000, 16) >;
|
||||
};
|
||||
|
||||
cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
||||
qcom,target-dev = <&cpu4_llcc_ddr_lat>;
|
||||
qcom,cachemiss-ev = <0x1000>;
|
||||
qcom,core-dev-table =
|
||||
< 300000 MHZ_TO_MBPS( 200, 4) >,
|
||||
< 672000 MHZ_TO_MBPS( 451, 4) >,
|
||||
< 902400 MHZ_TO_MBPS( 547, 4) >,
|
||||
< 1017600 MHZ_TO_MBPS( 768, 4) >,
|
||||
< 1305600 MHZ_TO_MBPS(1017, 4) >,
|
||||
< 1593600 MHZ_TO_MBPS(1353, 4) >,
|
||||
< 1804800 MHZ_TO_MBPS(1555, 4) >,
|
||||
< 2188800 MHZ_TO_MBPS(1708, 4) >,
|
||||
< 2400000 MHZ_TO_MBPS(2133, 4) >;
|
||||
};
|
||||
|
||||
cpu4_computemon: qcom,cpu4-computemon {
|
||||
compatible = "qcom,arm-compute-mon";
|
||||
qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
|
||||
ddr4-map {
|
||||
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
|
||||
qcom,core-dev-table =
|
||||
< 1804800 MHZ_TO_MBPS( 200, 4) >,
|
||||
< 2304000 MHZ_TO_MBPS(1017, 4) >,
|
||||
< 2400000 MHZ_TO_MBPS(2133, 4) >;
|
||||
};
|
||||
|
||||
ddr5-map {
|
||||
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
|
||||
qcom,core-dev-table =
|
||||
< 1804800 MHZ_TO_MBPS( 200, 4) >,
|
||||
< 2303000 MHZ_TO_MBPS(1017, 4) >,
|
||||
< 2400000 MHZ_TO_MBPS(3196, 4) >;
|
||||
};
|
||||
};
|
||||
|
||||
cpu4_qoslatmon: qcom,cpu4-qoslatmon {
|
||||
compatible = "qcom,arm-memlat-mon";
|
||||
qcom,target-dev = <&cpu4_cpu_ddr_qoslat>;
|
||||
qcom,cachemiss-ev = <0x1000>;
|
||||
qcom,core-dev-table =
|
||||
< 300000 1 >,
|
||||
< 3000000 2 >;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "direwolf-pinctrl.dtsi"
|
||||
|
|
|
|||
Loading…
Reference in a new issue