From 2477bc6ba2f74d62510224b949346ef6ad455ad1 Mon Sep 17 00:00:00 2001
From: Dhaval Patel <pdhaval@quicinc.com>
Date: Thu, 4 Jun 2020 10:17:16 -0700
Subject: [PATCH] ARM: dts: msm: enable io coherency on unsecure cb for Lahaina

Enable io coherency for non-secure context bank for lahaina
target. This support is not needed for secure context bank because
secure cb only maps secure buffers which are not cpu accessible.

Change-Id: If693842c68fa714c6eee5c62437432ffbe80f749
---
 display/lahaina-sde.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi
index 24e47646458b..5204abeb9c49 100644
--- a/display/lahaina-sde.dtsi
+++ b/display/lahaina-sde.dtsi
@@ -662,6 +662,7 @@
 		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
 		qcom,iommu-faults = "non-fatal";
 		qcom,iommu-earlymap; /* for cont-splash */
+		dma-coherent-hint-cached;
 	};
 
 	smmu_sde_sec: qcom,smmu_sde_sec_cb {