mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 23:24:22 -04:00
firmware: qcom_scm-64: Add SCM results to descriptor
Remove knowledge of arm_smccc_res struct from client wrappers so that client wrappers only work QCOM SCM data structures. SCM calls may have up to 3 arguments, so qcom_scm_call_smccc is responsible now for filling those 3 arguments accordingly. Change-Id: I9712f75f6bea0a6528ccd5a69bc1602493574e19 Signed-off-by: Elliot Berman <eberman@codeaurora.org>
This commit is contained in:
Elliot Berman
parent
40ea361077
commit
abe9598276
1 changed files with 43 additions and 61 deletions
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@ -50,6 +50,7 @@ struct qcom_scm_desc {
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u32 cmd;
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u32 arginfo;
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u64 args[MAX_QCOM_SCM_ARGS];
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u64 res[MAX_QCOM_SCM_RETS];
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u32 owner;
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};
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@ -115,8 +116,7 @@ static void qcom_scm_call_do_smccc(const struct qcom_scm_desc *desc,
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}
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static int ___qcom_scm_call_smccc(struct device *dev,
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const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res, bool atomic)
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struct qcom_scm_desc *desc, bool atomic)
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{
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int arglen = desc->arginfo & 0xf;
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int i;
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@ -125,6 +125,7 @@ static int ___qcom_scm_call_smccc(struct device *dev,
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void *args_virt = NULL;
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size_t alloc_len;
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gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
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struct arm_smccc_res res;
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if (unlikely(arglen > SMCCC_N_REG_ARGS)) {
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alloc_len = SMCCC_N_EXT_ARGS * sizeof(u64);
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@ -158,17 +159,18 @@ static int ___qcom_scm_call_smccc(struct device *dev,
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x5 = args_phys;
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}
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qcom_scm_call_do_smccc(desc, res, x5, atomic);
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qcom_scm_call_do_smccc(desc, &res, x5, atomic);
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if (args_virt) {
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dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
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kfree(args_virt);
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}
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if (res->a0 < 0)
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return qcom_scm_remap_error(res->a0);
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desc->res[0] = res.a1;
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desc->res[1] = res.a2;
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desc->res[2] = res.a3;
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return 0;
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return res.a0 ? qcom_scm_remap_error(res.a0) : 0;
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}
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/**
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@ -181,11 +183,10 @@ static int ___qcom_scm_call_smccc(struct device *dev,
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* Sends a command to the SCM and waits for the command to finish processing.
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* This should *only* be called in pre-emptible context.
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*/
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static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res)
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static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc)
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{
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might_sleep();
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return ___qcom_scm_call_smccc(dev, desc, res, false);
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return ___qcom_scm_call_smccc(dev, desc, false);
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}
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/**
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@ -199,11 +200,9 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
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* Sends a command to the SCM and waits for the command to finish processing.
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* This can be called in atomic context.
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*/
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static int qcom_scm_call_atomic(struct device *dev,
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const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res)
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static int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc)
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{
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return ___qcom_scm_call_smccc(dev, desc, res, true);
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return ___qcom_scm_call_smccc(dev, desc, true);
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}
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/**
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@ -253,16 +252,15 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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.cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = state;
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desc.args[1] = id;
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desc.arginfo = QCOM_SCM_ARGS(2);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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return ret ? : res.a1;
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return ret ? : desc.res[0];
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}
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int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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@ -272,13 +270,12 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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.cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;
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desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call(dev, &desc, &res);
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return qcom_scm_call(dev, &desc);
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}
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bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
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@ -289,14 +286,13 @@ bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
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.cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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return ret ? false : !!res.a1;
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return ret ? false : !!desc.res[0];
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}
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int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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@ -308,15 +304,14 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = peripheral;
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desc.args[1] = metadata_phys;
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desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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return ret ? : res.a1;
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return ret ? : desc.res[0];
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}
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int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
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@ -328,16 +323,15 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
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.cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = peripheral;
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desc.args[1] = addr;
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desc.args[2] = size;
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desc.arginfo = QCOM_SCM_ARGS(3);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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return ret ? : res.a1;
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return ret ? : desc.res[0];
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}
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int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
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@ -348,14 +342,13 @@ int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
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.cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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return ret ? : res.a1;
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return ret ? : desc.res[0];
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}
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int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
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@ -366,14 +359,13 @@ int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
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.cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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return ret ? : res.a1;
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return ret ? : desc.res[0];
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}
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int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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@ -383,16 +375,15 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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.cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = reset;
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desc.args[1] = 0;
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desc.arginfo = QCOM_SCM_ARGS(2);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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return ret ? : res.a1;
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return ret ? : desc.res[0];
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}
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int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
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@ -403,15 +394,14 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
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.cmd = QCOM_SCM_IO_READ,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = addr;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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if (ret >= 0)
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*val = res.a1;
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*val = desc.res[0];
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return ret < 0 ? ret : 0;
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}
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@ -423,13 +413,12 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
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.cmd = QCOM_SCM_IO_WRITE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = addr;
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desc.args[1] = val;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call(dev, &desc, &res);
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return qcom_scm_call(dev, &desc);
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}
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int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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@ -440,15 +429,14 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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.cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.arginfo = QCOM_SCM_ARGS(1);
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desc.args[0] = SMCCC_FUNCNUM(svc_id, cmd_id) |
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(ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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return ret ? : res.a1;
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return ret ? : desc.res[0];
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}
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int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
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@ -458,16 +446,15 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
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.cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = device_id;
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desc.args[1] = spare;
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desc.arginfo = QCOM_SCM_ARGS(2);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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return ret ? : res.a1;
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return ret ? : desc.res[0];
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}
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int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
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@ -478,18 +465,17 @@ int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
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.cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = spare;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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if (size)
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*size = res.a1;
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*size = desc.res[0];
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return ret ? : res.a2;
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return ret ? : desc.res[1];
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}
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int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
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@ -500,7 +486,6 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
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.cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = addr;
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@ -509,7 +494,7 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
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desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
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QCOM_SCM_VAL);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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/* the pg table has been initialized already, ignore the error */
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if (ret == -EPERM)
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@ -528,7 +513,6 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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.cmd = QCOM_SCM_MP_ASSIGN,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = mem_region;
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desc.args[1] = mem_sz;
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@ -542,9 +526,9 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
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QCOM_SCM_VAL, QCOM_SCM_VAL);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc);
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return ret ? : res.a1;
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return ret ? : desc.res[0];
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}
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int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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@ -556,7 +540,6 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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.cmd = QCOM_SCM_HDCP_INVOKE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
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return -ERANGE;
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@ -573,8 +556,8 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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desc.args[9] = req[4].val;
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desc.arginfo = QCOM_SCM_ARGS(10);
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ret = qcom_scm_call(dev, &desc, &res);
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*resp = res.a1;
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ret = qcom_scm_call(dev, &desc);
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*resp = desc.res[0];
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return ret;
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}
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@ -586,13 +569,12 @@ int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)
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.cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL;
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desc.args[1] = en;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call_atomic(dev, &desc, &res);
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return qcom_scm_call_atomic(dev, &desc);
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}
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void __qcom_scm_init(void)
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