From a868bb9d140088d3b77a2395b97793ac4ce5ffd6 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Thu, 12 Oct 2017 08:24:04 +0530 Subject: [PATCH] ASoC: codecs: sdm660_cdc: Fix HPH CnP issue on sdm660-internal Pop is observed after start playback on hph. This is because both compander channels are not enabled at the same time which differs from ideal sequence. Amplitude of pop gets reduced after corresponding change is made. CRs-Fixed: 2101404 Change-Id: Iba2b8a809fd3b53f0c180ce28ac5668d7635fb24 Signed-off-by: Vatsal Bucha --- asoc/codecs/sdm660_cdc/msm-digital-cdc.c | 32 +++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/asoc/codecs/sdm660_cdc/msm-digital-cdc.c b/asoc/codecs/sdm660_cdc/msm-digital-cdc.c index 00a969935d1a..4b875ccec969 100644 --- a/asoc/codecs/sdm660_cdc/msm-digital-cdc.c +++ b/asoc/codecs/sdm660_cdc/msm-digital-cdc.c @@ -217,6 +217,7 @@ static int msm_dig_cdc_codec_config_compander(struct snd_soc_codec *codec, { struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); int comp_ch_bits_set = 0x03; + int comp_ch_value; dev_dbg(codec->dev, "%s: event %d shift %d, enabled %d\n", __func__, event, interp_n, @@ -236,15 +237,40 @@ static int msm_dig_cdc_codec_config_compander(struct snd_soc_codec *codec, dig_cdc->set_compander_mode(dig_cdc->handle, 0x00); return 0; }; + comp_ch_value = snd_soc_read(codec, + MSM89XX_CDC_CORE_COMP0_B1_CTL); + if (interp_n == 0) { + if (comp_ch_value & 0x02) { + dev_dbg(codec->dev, + "%s comp ch 1 already enabled\n", + __func__); + return 0; + } + } + if (interp_n == 1) { + if (comp_ch_value & 0x01) { + dev_dbg(codec->dev, + "%s comp ch 0 already enabled\n", + __func__); + return 0; + } + } dig_cdc->set_compander_mode(dig_cdc->handle, 0x08); /* Enable Compander Clock */ snd_soc_update_bits(codec, MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x09); snd_soc_update_bits(codec, MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x01); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_COMP0_B1_CTL, - 1 << interp_n, 1 << interp_n); + if (dig_cdc->comp_enabled[MSM89XX_RX1]) { + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_COMP0_B1_CTL, + 0x02, 0x02); + } + if (dig_cdc->comp_enabled[MSM89XX_RX2]) { + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_COMP0_B1_CTL, + 0x01, 0x01); + } snd_soc_update_bits(codec, MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x01); snd_soc_update_bits(codec,