diff --git a/display/shima-sde-display-idp.dtsi b/display/shima-sde-display-idp.dtsi
new file mode 100644
index 000000000000..7fd9d2bc172f
--- /dev/null
+++ b/display/shima-sde-display-idp.dtsi
@@ -0,0 +1,32 @@
+#include "shima-sde-display.dtsi"
+
+&dsi_r66451_amoled_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <255>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 24 0>;
+};
+
+&dsi_r66451_amoled_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <255>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-te-gpio = <&tlmm 82 0>;
+	qcom,platform-reset-gpio = <&tlmm 24 0>;
+};
+
+&dsi_sim_vid {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&tlmm 24 0>;
+};
+
+&sde_dsi {
+	qcom,dsi-default-panel = <&dsi_r66451_amoled_video>;
+};
diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi
new file mode 100644
index 000000000000..03e5cc9147a1
--- /dev/null
+++ b/display/shima-sde-display.dtsi
@@ -0,0 +1,204 @@
+#include "dsi-panel-r66451-dsc-fhd-plus-video.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi"
+#include "dsi-panel-sim-video.dtsi"
+#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
+
+&soc {
+	dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <1800000>;
+			qcom,supply-enable-load = <60700>;
+			qcom,supply-disable-load = <80>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+
+		qcom,panel-supply-entry@1 {
+			reg = <1>;
+			qcom,supply-name = "vdd";
+			qcom,supply-min-voltage = <3000000>;
+			qcom,supply-max-voltage = <3000000>;
+			qcom,supply-enable-load = <10000>;
+			qcom,supply-disable-load = <0>;
+			qcom,supply-post-on-sleep = <0>;
+		};
+
+		qcom,panel-supply-entry@2 {
+			reg = <2>;
+			qcom,supply-name = "lab";
+			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-max-voltage = <6000000>;
+			qcom,supply-enable-load = <0>;
+			qcom,supply-disable-load = <0>;
+		};
+
+		qcom,panel-supply-entry@3 {
+			reg = <3>;
+			qcom,supply-name = "ibb";
+			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-max-voltage = <6000000>;
+			qcom,supply-enable-load = <0>;
+			qcom,supply-disable-load = <0>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+	};
+
+	sde_dsi: qcom,dsi-display-primary {
+		compatible = "qcom,dsi-display";
+		label = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+		clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
+				 <&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
+				 <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
+				 <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
+				 <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>,
+				 <&mdss_dsi_phy0 PCLK_SRC_0_CLK>,
+				 <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
+				 <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
+				 <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
+				 <&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
+				 <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
+				 <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>,
+				 <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>,
+				 <&mdss_dsi_phy1 PCLK_SRC_1_CLK>,
+				 <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>,
+				 <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>;
+		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+				"cphy_byte_clk0", "cphy_pixel_clk0",
+				"src_byte_clk0", "src_pixel_clk0",
+				"shadow_byte_clk0", "shadow_pixel_clk0",
+				"mux_byte_clk1", "mux_pixel_clk1",
+				"cphy_byte_clk1", "cphy_pixel_clk1",
+				"src_byte_clk1", "src_pixel_clk1",
+				"shadow_byte_clk1", "shadow_pixel_clk1";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
+		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
+
+		qcom,platform-te-gpio = <&tlmm 82 0>;
+		qcom,panel-te-source = <0>;
+
+		vddio-supply = <&L12C>;
+		vdd-supply = <&L13C>;
+		lab-supply = <&ab_vreg>;
+		ibb-supply = <&ibb_vreg>;
+
+		qcom,mdp = <&mdss_mdp>;
+		qcom,dsi-default-panel = <&dsi_r66451_amoled_video>;
+	};
+
+	sde_dsi1: qcom,dsi-display-secondary {
+		compatible = "qcom,dsi-display";
+		label = "secondary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+		qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+		clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
+			 <&mdss_dsi_phy0 PCLK_MUX_0_CLK>,
+			 <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,
+			 <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,
+			 <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>,
+			 <&mdss_dsi_phy1 PCLK_MUX_1_CLK>,
+			 <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>,
+			 <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>;
+		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+				"cphy_byte_clk0", "cphy_pixel_clk0",
+				"mux_byte_clk1", "mux_pixel_clk1",
+				"cphy_byte_clk1", "cphy_pixel_clk1";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
+		pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
+
+		qcom,platform-te-gpio = <&tlmm 83 0>;
+		qcom,panel-te-source = <1>;
+
+		vddio-supply = <&L12C>;
+		vdd-supply = <&L13C>;
+
+		qcom,mdp = <&mdss_mdp>;
+	};
+
+	sde_wb: qcom,wb-display@0 {
+		compatible = "qcom,wb-display";
+		cell-index = <0>;
+		label = "wb_display";
+	};
+};
+
+&mdss_mdp {
+	connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi
+		&sde_dsi1>;
+};
+
+&dsi_r66451_amoled_video {
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+	qcom,mdss-dsi-panel-status-value = <0x1c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06
+				06 06 02 04 00 14 0a];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_r66451_amoled_cmd {
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+	qcom,mdss-dsi-panel-status-value = <0x1c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04
+				04 03 02 04 00 0e 09];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+
+		timing@1 {
+			qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06
+				06 06 02 04 00 14 0a];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+
+		timing@2 {
+			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07
+				07 08 02 04 00 19 0c];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_sim_vid {
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
+				01 01 02 04 00 06 06];
+			qcom,display-topology = <1 0 1>,
+						<2 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi
new file mode 100644
index 000000000000..3a2e89c22c39
--- /dev/null
+++ b/display/shima-sde.dtsi
@@ -0,0 +1,491 @@
+#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
+
+&soc {
+	mdss_mdp: qcom,mdss_mdp@ae00000  {
+		compatible = "qcom,sde-kms";
+		reg = <0xae00000 0x84208>,
+		      <0xaeb0000 0x2008>,
+		      <0xaeac000 0x214>,
+		      <0xaf50000 0x038>;
+		reg-names = "mdp_phys",
+			"vbif_phys",
+			"regdma_phys",
+			"swfuse_phys";
+		clocks =
+			<&gcc GCC_DISP_AHB_CLK>,
+			<&gcc GCC_DISP_HF_AXI_CLK>,
+			<&gcc GCC_DISP_SF_AXI_CLK>,
+			<&dispcc DISP_CC_MDSS_AHB_CLK>,
+			<&dispcc DISP_CC_MDSS_MDP_CLK>,
+			<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+			<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
+		clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
+				"iface_clk", "core_clk", "vsync_clk",
+				"lut_clk";
+		clock-rate = <0 0 0 0 460000000 19200000 460000000>;
+		clock-max-rate = <0 0 0 0 460000000 19200000 460000000>;
+
+		/* interrupt config */
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		vdd-supply = <&disp_cc_mdss_core_gdsc>;
+		/* hw blocks */
+		qcom,sde-off = <0x1000>;
+		qcom,sde-len = <0x494>;
+
+		qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>;
+		qcom,sde-ctl-size = <0x1dc>;
+		qcom,sde-ctl-display-pref = "primary", "none", "none", "none";
+
+		qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>;
+		qcom,sde-mixer-size = <0x320>;
+		qcom,sde-mixer-display-pref = "primary", "primary", "none",
+						"none";
+		qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb";
+
+		qcom,sde-dspp-top-off = <0x1300>;
+		qcom,sde-dspp-top-size = <0x80>;
+		qcom,sde-dspp-off = <0x55000 0x57000>;
+		qcom,sde-dspp-size = <0x1800>;
+
+		qcom,sde-dest-scaler-top-off = <0x00061000>;
+		qcom,sde-dest-scaler-top-size = <0x1c>;
+		qcom,sde-dest-scaler-off = <0x800 0x1000>;
+		qcom,sde-dest-scaler-size = <0x800>;
+
+		qcom,sde-wb-off = <0x66000>;
+		qcom,sde-wb-size = <0x2c8>;
+		qcom,sde-wb-xin-id = <6>;
+		qcom,sde-wb-id = <2>;
+		qcom,sde-wb-clk-ctrl = <0x2bc 16>;
+		qcom,sde-wb-clk-status = <0x3bc 20>;
+
+		qcom,sde-intf-off = <0x6b000 0x6b800
+					0x6c000 0x6c800>;
+		qcom,sde-intf-size = <0x2b8>;
+		qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
+		qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>;
+
+		qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>;
+		qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>;
+		qcom,sde-pp-size = <0xd4>;
+		qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>;
+
+		qcom,sde-merge-3d-off = <0x84000 0x84100>;
+		qcom,sde-merge-3d-size = <0x100>;
+
+		qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>;
+
+		qcom,sde-cdm-off = <0x7a200>;
+		qcom,sde-cdm-size = <0x224>;
+
+		qcom,sde-dsc-off = <0x81000 0x81400>;
+		qcom,sde-dsc-size = <0x140>;
+		qcom,sde-dsc-pair-mask = <2 1>;
+
+		qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0
+					0x30e0>;
+		qcom,sde-dither-version = <0x00010000>;
+		qcom,sde-dither-size = <0x20>;
+
+		qcom,sde-sspp-type = "vig", "vig",
+				     "dma", "dma", "dma";
+		qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>;
+		qcom,sde-sspp-src-size = <0x1f8>;
+		qcom,sde-sspp-xin-id = <0 4 1 5 9>;
+		qcom,sde-sspp-excl-rect = <1 1 1 1 1>;
+		qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>;
+		qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+		qcom,sde-mixer-pair-mask = <2 1 4 3>;
+
+		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+						0xb0 0xc8 0xe0>;
+
+		qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000
+						 4300000 4300000
+						 4300000>;
+
+		qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000
+						      4300000 4300000
+						      4300000>;
+
+		/* offsets are relative to "mdp_phys + qcom,sde-off */
+		qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>,
+					 <0x2ac 8>, <0x2b4 8>, <0x2c4 8>;
+		qcom,sde-sspp-clk-status =
+				<0x2b0 0>, <0x2b8 0>, <0x2b0 12>,
+				<0x2b8 12>, <0x2c8 12>;
+		qcom,sde-sspp-csc-off = <0x1a00>;
+		qcom,sde-csc-type = "csc-10bit";
+		qcom,sde-qseed-sw-lib-rev = "qseedv3lite";
+		qcom,sde-qseed-scalar-version = <0x3000>;
+		qcom,sde-sspp-qseed-off = <0xa00>;
+		qcom,sde-mixer-linewidth = <2560>;
+		qcom,sde-sspp-linewidth = <2880>;
+		qcom,sde-vig-sspp-linewidth = <4096>;
+		qcom,sde-scaling-linewidth = <2560>;
+		qcom,sde-wb-linewidth = <4096>;
+		qcom,sde-mixer-blendstages = <0x9>;
+		qcom,sde-highest-bank-bit = <0x7 0x1>,
+					    <0x8 0x2>;
+		qcom,sde-ubwc-version = <0x400>;
+		qcom,sde-ubwc-swizzle = <0x6>;
+		qcom,sde-ubwc-bw-calc-version = <0x1>;
+		qcom,sde-ubwc-static = <0x1>;
+		qcom,sde-macrotile-mode = <0x1>;
+		qcom,sde-smart-panel-align-mode = <0xc>;
+		qcom,sde-panic-per-pipe;
+		qcom,sde-has-cdp;
+		qcom,sde-has-src-split;
+		qcom,sde-pipe-order-version = <0x1>;
+		qcom,sde-has-dim-layer;
+		qcom,sde-has-dest-scaler;
+		qcom,sde-has-idle-pc;
+		qcom,sde-max-dest-scaler-input-linewidth = <2048>;
+		qcom,sde-max-dest-scaler-output-linewidth = <2560>;
+		qcom,sde-max-bw-low-kbps = <5900000>;
+		qcom,sde-max-bw-high-kbps = <13500000>;
+		qcom,sde-min-core-ib-kbps = <2500000>;
+		qcom,sde-min-llcc-ib-kbps = <0>;
+		qcom,sde-min-dram-ib-kbps = <1600000>;
+		qcom,sde-dram-channels = <2>;
+		qcom,sde-num-nrt-paths = <0>;
+		qcom,sde-dspp-ltm-version = <0x00010000>;
+		/* offsets are based off dspp 0 and dspp 1 */
+		qcom,sde-dspp-ltm-off = <0x2a000 0x28100>;
+
+		qcom,sde-uidle-off = <0x80000>;
+		qcom,sde-uidle-size = <0x70>;
+		qcom,sde-vbif-off = <0>;
+		qcom,sde-vbif-size = <0x1040>;
+		qcom,sde-vbif-id = <0>;
+		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
+		qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>;
+		qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;
+
+		/* macrotile & macrotile-qseed has the same configs */
+		qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000
+			0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff
+			0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>;
+
+		qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x3ff 0xff00 0xff00>,
+			<0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>;
+
+		/* creq LUTs */
+		qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
+		qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
+		qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
+		qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
+		qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>;
+		qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>;
+		qcom,sde-qos-refresh-rates = <60 120>;
+
+		qcom,sde-cdp-setting = <1 1>, <1 0>;
+
+		qcom,sde-qos-cpu-mask = <0x3>;
+		qcom,sde-qos-cpu-dma-latency = <300>;
+		qcom,sde-qos-cpu-irq-latency = <300>;
+
+		/* offsets are relative to "mdp_phys + qcom,sde-off */
+
+		qcom,sde-reg-dma-off = <0>;
+		qcom,sde-reg-dma-id = <0>;
+		qcom,sde-reg-dma-version = <0x00010002>;
+		qcom,sde-reg-dma-trigger-off = <0x119c>;
+		qcom,sde-reg-dma-xin-id = <7>;
+		qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
+
+		qcom,sde-secure-sid-mask = <0x801 0xC01>;
+
+		/* data and reg bus scale settings */
+		interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
+				<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
+				<&gem_noc MASTER_APPSS_PROC
+					&config_noc SLAVE_DISPLAY_CFG>;
+		interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1",
+				"qcom,sde-reg-bus";
+		qcom,sde-reg-bus,vectors-KBps = <0 0>,
+				<0 74000>,
+				<0 148000>,
+				<0 265000>;
+
+		qcom,sde-sspp-vig-blocks {
+			qcom,sde-vig-csc-off = <0x1a00>;
+			qcom,sde-vig-qseed-off = <0xa00>;
+			qcom,sde-vig-qseed-size = <0xa0>;
+			qcom,sde-vig-gamut = <0x1d00 0x00060000>;
+			qcom,sde-vig-igc = <0x1d00 0x00060000>;
+			qcom,sde-vig-inverse-pma;
+		};
+
+		qcom,sde-sspp-dma-blocks {
+			dgm@0 {
+				qcom,sde-dma-igc = <0x400 0x00050000>;
+				qcom,sde-dma-gc = <0x600 0x00050000>;
+				qcom,sde-dma-inverse-pma;
+				qcom,sde-dma-csc-off = <0x200>;
+			};
+
+			dgm@1 {
+				qcom,sde-dma-igc = <0x1400 0x00050000>;
+				qcom,sde-dma-gc = <0x600 0x00050000>;
+				qcom,sde-dma-inverse-pma;
+				qcom,sde-dma-csc-off = <0x1200>;
+			};
+		};
+
+		qcom,sde-dspp-blocks {
+			qcom,sde-dspp-igc = <0x0 0x00030001>;
+			qcom,sde-dspp-hsic = <0x800 0x00010007>;
+			qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+			qcom,sde-dspp-hist = <0x800 0x00010007>;
+			qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+			qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+			qcom,sde-dspp-gamut = <0x1000 0x00040002>;
+			qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+			qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+			qcom,sde-dspp-dither = <0x82c 0x00010007>;
+		};
+
+		qcom,platform-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,platform-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdd";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+
+	sde_rscc: qcom,sde_rscc {
+		cell-index = <0>;
+		compatible = "qcom,sde-rsc";
+		status = "disabled";
+		reg = <0xaf20000 0x4d68>,
+			<0xaf30000 0x3fd4>;
+		reg-names = "drv", "wrapper";
+		qcom,sde-rsc-version = <4>;
+
+		qcom,sde-dram-channels = <2>;
+
+		vdd-supply = <&disp_cc_mdss_core_gdsc>;
+		clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
+			<&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
+			<&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
+		clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
+		qcom,msm-bus,active-only;
+		interconnects =
+			<&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>,
+			<&mmss_noc MASTER_MDP1_DISP &gem_noc SLAVE_LLCC_DISP>,
+			<&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>;
+		interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1",
+				"qcom,sde-ebi-bus";
+	};
+
+	smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+		compatible = "qcom,smmu_sde_unsec";
+		iommus = <&apps_smmu 0x800 0x402>;
+		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+		qcom,iommu-faults = "non-fatal";
+		qcom,iommu-earlymap; /* for cont-splash */
+		dma-coherent-hint-cached;
+	};
+
+	smmu_sde_sec: qcom,smmu_sde_sec_cb {
+		compatible = "qcom,smmu_sde_sec";
+		iommus = <&apps_smmu 0x801 0x0>,
+			<&apps_smmu 0xC01 0x0>;
+		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+		qcom,iommu-faults = "non-fatal";
+		qcom,iommu-vmid = <0xa>;
+	};
+
+	mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
+		compatible = "qcom,dsi-ctrl-hw-v2.4";
+		label = "dsi-ctrl-0";
+		cell-index = <0>;
+		frame-threshold-time-us = <800>;
+		reg = <0xae94000 0x400>,
+			<0xaf08000 0x4>;
+		reg-names = "dsi_ctrl", "disp_cc_base";
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <4 0>;
+		vdda-1p2-supply = <&L6B>;
+		refgen-supply = <&refgen>;
+		clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+			<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+			<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+			<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_ESC0_CLK>;
+		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+				"pixel_clk", "pixel_clk_rcg", "esc_clk";
+
+		qcom,ctrl-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,ctrl-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-1p2";
+				qcom,supply-min-voltage = <1200000>;
+				qcom,supply-max-voltage = <1200000>;
+				qcom,supply-enable-load = <8350>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,core-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,core-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "refgen";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+
+	mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
+		compatible = "qcom,dsi-ctrl-hw-v2.4";
+		label = "dsi-ctrl-1";
+		cell-index = <1>;
+		frame-threshold-time-us = <800>;
+		reg = <0xae96000 0x400>,
+			<0xaf08000 0x4>;
+		reg-names = "dsi_ctrl", "disp_cc_base";
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <5 0>;
+		vdda-1p2-supply = <&L6B>;
+		refgen-supply = <&refgen>;
+		clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+			<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+			<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+			<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_ESC1_CLK>;
+		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+				"pixel_clk", "pixel_clk_rcg", "esc_clk";
+		qcom,ctrl-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,ctrl-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-1p2";
+				qcom,supply-min-voltage = <1200000>;
+				qcom,supply-max-voltage = <1200000>;
+				qcom,supply-enable-load = <8350>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,core-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,core-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "refgen";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+
+	mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 {
+		compatible = "qcom,dsi-phy-v4.2";
+		label = "dsi-phy-0";
+		cell-index = <0>;
+		#clock-cells = <1>;
+		reg = <0xae94400 0x800>,
+		      <0xae94900 0x27c>,
+		      <0xaf03000 0x8>,
+		      <0xae94200 0x100>;
+		reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";
+		pll-label = "dsi_pll_5nm";
+		vdda-0p9-supply = <&L10C>;
+		qcom,dsi-pll-ssc-en;
+		qcom,dsi-pll-ssc-mode = "down-spread";
+		qcom,platform-strength-ctrl = [55 03
+						55 03
+						55 03
+						55 03
+						55 00];
+		qcom,platform-lane-config = [00 00 0a 0a
+						00 00 0a 0a
+						00 00 0a 0a
+						00 00 0a 0a
+						00 00 8a 8a];
+		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+		qcom,phy-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			qcom,phy-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-0p9";
+				qcom,supply-min-voltage = <880000>;
+				qcom,supply-max-voltage = <880000>;
+				qcom,supply-enable-load = <37550>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+
+	mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 {
+		compatible = "qcom,dsi-phy-v4.2";
+		label = "dsi-phy-1";
+		cell-index = <1>;
+		#clock-cells = <1>;
+		reg = <0xae96400 0x800>,
+		      <0xae96900 0x27c>,
+		      <0xaf03000 0x8>,
+		      <0xae96200 0x100>;
+		reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";
+		pll-label = "dsi_pll_5nm";
+		vdda-0p9-supply = <&L10C>;
+		qcom,dsi-pll-ssc-en;
+		qcom,dsi-pll-ssc-mode = "down-spread";
+		qcom,platform-strength-ctrl = [55 03
+						55 03
+						55 03
+						55 03
+						55 00];
+		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+		qcom,platform-lane-config = [00 00 0a 0a
+						00 00 0a 0a
+						00 00 0a 0a
+						00 00 0a 0a
+						00 00 8a 8a];
+		qcom,phy-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			qcom,phy-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-0p9";
+				qcom,supply-min-voltage = <880000>;
+				qcom,supply-max-voltage = <880000>;
+				qcom,supply-enable-load = <37550>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+};