From ac5193ab05fe76cbc17370fafaabea144f65b15e Mon Sep 17 00:00:00 2001
From: Krishna Manikandan <mkrishn@qti.qualcomm.com>
Date: Wed, 2 Sep 2020 12:33:59 +0530
Subject: [PATCH] ARM: dts: msm: enable SDE RSC driver on shima

Enable sde rscc v4 driver on shima target

Change-Id: Ib0d930dfc6837f53edbff41970035ec0165586ae
---
 display/shima-sde-display.dtsi |  2 +-
 display/shima-sde.dtsi         | 16 ----------------
 2 files changed, 1 insertion(+), 17 deletions(-)

diff --git a/display/shima-sde-display.dtsi b/display/shima-sde-display.dtsi
index 915fcb443d56..27f33e0b435c 100644
--- a/display/shima-sde-display.dtsi
+++ b/display/shima-sde-display.dtsi
@@ -138,7 +138,7 @@
 
 &mdss_mdp {
 	connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dsi
-		&sde_dsi1>;
+		&sde_dsi1 &sde_rscc>;
 };
 
 &dsi_r66451_amoled_video {
diff --git a/display/shima-sde.dtsi b/display/shima-sde.dtsi
index 6e5e724c7e6e..6cbbb353d36f 100644
--- a/display/shima-sde.dtsi
+++ b/display/shima-sde.dtsi
@@ -147,7 +147,6 @@
 	sde_rscc: qcom,sde_rscc {
 		cell-index = <0>;
 		compatible = "qcom,sde-rsc";
-		status = "disabled";
 		reg = <0xaf20000 0x4d68>,
 			<0xaf30000 0x3fd4>;
 		reg-names = "drv", "wrapper";
@@ -200,7 +199,6 @@
 	clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
 			"iface_clk", "core_clk", "vsync_clk",
 			"lut_clk";
-	vdd-supply = <&disp_cc_mdss_core_gdsc>;
 
 	/* data and reg bus scale settings */
 	interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
@@ -213,20 +211,6 @@
 	qcom,sde-dspp-ltm-version = <0x00010000>;
 	/* offsets are based off dspp 0 and dspp 1 */
 	qcom,sde-dspp-ltm-off = <0x2a000 0x28100>;
-
-	qcom,platform-supply-entries {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		qcom,platform-supply-entry@0 {
-			reg = <0>;
-			qcom,supply-name = "vdd";
-			qcom,supply-min-voltage = <0>;
-			qcom,supply-max-voltage = <0>;
-			qcom,supply-enable-load = <0>;
-			qcom,supply-disable-load = <0>;
-		};
-	};
 };
 
 &mdss_dsi0 {