From ac801eb444d01e7d0c9b5ae4403e86f7ee06bc89 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 17 Mar 2020 16:19:10 +0530 Subject: [PATCH] dt-bindings: clock: Add dt-bindings for SM8150 Add clock controller dt-bindings for SM8150. Change-Id: I5f3cfa965ba3191fd87f1942c200b168f67206f6 Signed-off-by: Veera Vegivada --- include/dt-bindings/clock/qcom,camcc-sm8150.h | 135 +++++ .../dt-bindings/clock/qcom,dispcc-sm8150.h | 79 +++ include/dt-bindings/clock/qcom,gcc-sm8150.h | 475 +++++++++--------- include/dt-bindings/clock/qcom,gpucc-sm8150.h | 34 ++ include/dt-bindings/clock/qcom,npucc-sm8150.h | 39 ++ include/dt-bindings/clock/qcom,scc-sm8150.h | 30 ++ .../dt-bindings/clock/qcom,videocc-sm8150.h | 30 ++ 7 files changed, 591 insertions(+), 231 deletions(-) create mode 100644 include/dt-bindings/clock/qcom,camcc-sm8150.h create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8150.h create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8150.h create mode 100644 include/dt-bindings/clock/qcom,npucc-sm8150.h create mode 100644 include/dt-bindings/clock/qcom,scc-sm8150.h create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8150.h diff --git a/include/dt-bindings/clock/qcom,camcc-sm8150.h b/include/dt-bindings/clock/qcom,camcc-sm8150.h new file mode 100644 index 000000000000..cc4249ddb0b7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,camcc-sm8150.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H + +/* CAM_CC clocks */ +#define CAM_CC_PLL0 0 +#define CAM_CC_PLL0_OUT_EVEN 1 +#define CAM_CC_PLL0_OUT_ODD 2 +#define CAM_CC_PLL1 3 +#define CAM_CC_PLL1_OUT_EVEN 4 +#define CAM_CC_PLL2 5 +#define CAM_CC_PLL2_OUT_MAIN 6 +#define CAM_CC_PLL3 7 +#define CAM_CC_PLL3_OUT_EVEN 8 +#define CAM_CC_PLL4 9 +#define CAM_CC_PLL4_OUT_EVEN 10 +#define CAM_CC_BPS_AHB_CLK 11 +#define CAM_CC_BPS_AREG_CLK 12 +#define CAM_CC_BPS_AXI_CLK 13 +#define CAM_CC_BPS_CLK 14 +#define CAM_CC_BPS_CLK_SRC 15 +#define CAM_CC_CAMNOC_AXI_CLK 16 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 17 +#define CAM_CC_CAMNOC_DCD_XO_CLK 18 +#define CAM_CC_CCI_0_CLK 19 +#define CAM_CC_CCI_0_CLK_SRC 20 +#define CAM_CC_CCI_1_CLK 21 +#define CAM_CC_CCI_1_CLK_SRC 22 +#define CAM_CC_CORE_AHB_CLK 23 +#define CAM_CC_CPAS_AHB_CLK 24 +#define CAM_CC_CPHY_RX_CLK_SRC 25 +#define CAM_CC_CSI0PHYTIMER_CLK 26 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSI1PHYTIMER_CLK 28 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 29 +#define CAM_CC_CSI2PHYTIMER_CLK 30 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 31 +#define CAM_CC_CSI3PHYTIMER_CLK 32 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 33 +#define CAM_CC_CSIPHY0_CLK 34 +#define CAM_CC_CSIPHY1_CLK 35 +#define CAM_CC_CSIPHY2_CLK 36 +#define CAM_CC_CSIPHY3_CLK 37 +#define CAM_CC_FAST_AHB_CLK_SRC 38 +#define CAM_CC_FD_CORE_CLK 39 +#define CAM_CC_FD_CORE_CLK_SRC 40 +#define CAM_CC_FD_CORE_UAR_CLK 41 +#define CAM_CC_GDSC_CLK 42 +#define CAM_CC_ICP_AHB_CLK 43 +#define CAM_CC_ICP_CLK 44 +#define CAM_CC_ICP_CLK_SRC 45 +#define CAM_CC_IFE_0_AXI_CLK 46 +#define CAM_CC_IFE_0_CLK 47 +#define CAM_CC_IFE_0_CLK_SRC 48 +#define CAM_CC_IFE_0_CPHY_RX_CLK 49 +#define CAM_CC_IFE_0_CSID_CLK 50 +#define CAM_CC_IFE_0_CSID_CLK_SRC 51 +#define CAM_CC_IFE_0_DSP_CLK 52 +#define CAM_CC_IFE_1_AXI_CLK 53 +#define CAM_CC_IFE_1_CLK 54 +#define CAM_CC_IFE_1_CLK_SRC 55 +#define CAM_CC_IFE_1_CPHY_RX_CLK 56 +#define CAM_CC_IFE_1_CSID_CLK 57 +#define CAM_CC_IFE_1_CSID_CLK_SRC 58 +#define CAM_CC_IFE_1_DSP_CLK 59 +#define CAM_CC_IFE_LITE_0_CLK 60 +#define CAM_CC_IFE_LITE_0_CLK_SRC 61 +#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 62 +#define CAM_CC_IFE_LITE_0_CSID_CLK 63 +#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 64 +#define CAM_CC_IFE_LITE_1_CLK 65 +#define CAM_CC_IFE_LITE_1_CLK_SRC 66 +#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 67 +#define CAM_CC_IFE_LITE_1_CSID_CLK 68 +#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 69 +#define CAM_CC_IPE_0_AHB_CLK 70 +#define CAM_CC_IPE_0_AREG_CLK 71 +#define CAM_CC_IPE_0_AXI_CLK 72 +#define CAM_CC_IPE_0_CLK 73 +#define CAM_CC_IPE_0_CLK_SRC 74 +#define CAM_CC_IPE_1_AHB_CLK 75 +#define CAM_CC_IPE_1_AREG_CLK 76 +#define CAM_CC_IPE_1_AXI_CLK 77 +#define CAM_CC_IPE_1_CLK 78 +#define CAM_CC_JPEG_CLK 79 +#define CAM_CC_JPEG_CLK_SRC 80 +#define CAM_CC_LRME_CLK 81 +#define CAM_CC_LRME_CLK_SRC 82 +#define CAM_CC_MCLK0_CLK 83 +#define CAM_CC_MCLK0_CLK_SRC 84 +#define CAM_CC_MCLK1_CLK 85 +#define CAM_CC_MCLK1_CLK_SRC 86 +#define CAM_CC_MCLK2_CLK 87 +#define CAM_CC_MCLK2_CLK_SRC 88 +#define CAM_CC_MCLK3_CLK 89 +#define CAM_CC_MCLK3_CLK_SRC 90 +#define CAM_CC_SLOW_AHB_CLK_SRC 91 + +/* CAM_CC power domains */ +#define BPS_GDSC 0 +#define IFE_0_GDSC 1 +#define IFE_1_GDSC 2 +#define IPE_0_GDSC 3 +#define IPE_1_GDSC 4 +#define TITAN_TOP_GDSC 5 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_CAMNOC_BCR 1 +#define CAM_CC_CCI_BCR 2 +#define CAM_CC_CPAS_BCR 3 +#define CAM_CC_CSI0PHY_BCR 4 +#define CAM_CC_CSI1PHY_BCR 5 +#define CAM_CC_CSI2PHY_BCR 6 +#define CAM_CC_CSI3PHY_BCR 7 +#define CAM_CC_FD_BCR 8 +#define CAM_CC_ICP_BCR 9 +#define CAM_CC_IFE_0_BCR 10 +#define CAM_CC_IFE_1_BCR 11 +#define CAM_CC_IFE_LITE_0_BCR 12 +#define CAM_CC_IFE_LITE_1_BCR 13 +#define CAM_CC_IPE_0_BCR 14 +#define CAM_CC_IPE_1_BCR 15 +#define CAM_CC_JPEG_BCR 16 +#define CAM_CC_LRME_BCR 17 +#define CAM_CC_MCLK0_BCR 18 +#define CAM_CC_MCLK1_BCR 19 +#define CAM_CC_MCLK2_BCR 20 +#define CAM_CC_MCLK3_BCR 21 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8150.h b/include/dt-bindings/clock/qcom,dispcc-sm8150.h new file mode 100644 index 000000000000..c5699ae3e409 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8150.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8150_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8150_H + +/* DISP_CC clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_PLL1 1 +#define DISP_CC_MDSS_AHB_CLK 2 +#define DISP_CC_MDSS_AHB_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_CLK 4 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 +#define DISP_CC_MDSS_BYTE1_CLK 8 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 11 +#define DISP_CC_MDSS_DP_AUX1_CLK 12 +#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 13 +#define DISP_CC_MDSS_DP_AUX_CLK 14 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 15 +#define DISP_CC_MDSS_DP_CRYPTO1_CLK 16 +#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC 17 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 18 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 19 +#define DISP_CC_MDSS_DP_LINK1_CLK 20 +#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 21 +#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 22 +#define DISP_CC_MDSS_DP_LINK_CLK 23 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 24 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 25 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 26 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 27 +#define DISP_CC_MDSS_DP_PIXEL2_CLK 28 +#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 29 +#define DISP_CC_MDSS_DP_PIXEL_CLK 30 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 31 +#define DISP_CC_MDSS_EDP_AUX_CLK 32 +#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 33 +#define DISP_CC_MDSS_EDP_GTC_CLK 34 +#define DISP_CC_MDSS_EDP_GTC_CLK_SRC 35 +#define DISP_CC_MDSS_EDP_LINK_CLK 36 +#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 37 +#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 38 +#define DISP_CC_MDSS_EDP_PIXEL_CLK 39 +#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 40 +#define DISP_CC_MDSS_ESC0_CLK 41 +#define DISP_CC_MDSS_ESC0_CLK_SRC 42 +#define DISP_CC_MDSS_ESC1_CLK 43 +#define DISP_CC_MDSS_ESC1_CLK_SRC 44 +#define DISP_CC_MDSS_MDP_CLK 45 +#define DISP_CC_MDSS_MDP_CLK_SRC 46 +#define DISP_CC_MDSS_MDP_LUT_CLK 47 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 48 +#define DISP_CC_MDSS_PCLK0_CLK 49 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 50 +#define DISP_CC_MDSS_PCLK1_CLK 51 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 52 +#define DISP_CC_MDSS_ROT_CLK 53 +#define DISP_CC_MDSS_ROT_CLK_SRC 54 +#define DISP_CC_MDSS_RSCC_AHB_CLK 55 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 56 +#define DISP_CC_MDSS_VSYNC_CLK 57 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 58 +#define DISP_CC_XO_CLK 59 + +/* DISP_CC power domains */ +#define MDSS_CORE_GDSC 0 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 +#define DISP_CC_MDSS_SPDM_BCR 2 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index 90d60ef94c64..cd9083d78004 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -1,243 +1,256 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H #define _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H /* GCC clocks */ -#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 -#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 -#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2 -#define GCC_AGGRE_UFS_PHY_AXI_CLK 3 -#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4 -#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5 -#define GCC_AGGRE_USB3_SEC_AXI_CLK 6 -#define GCC_BOOT_ROM_AHB_CLK 7 -#define GCC_CAMERA_AHB_CLK 8 -#define GCC_CAMERA_HF_AXI_CLK 9 -#define GCC_CAMERA_SF_AXI_CLK 10 -#define GCC_CAMERA_XO_CLK 11 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 -#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 -#define GCC_CPUSS_AHB_CLK 14 -#define GCC_CPUSS_AHB_CLK_SRC 15 -#define GCC_CPUSS_DVM_BUS_CLK 16 -#define GCC_CPUSS_GNOC_CLK 17 -#define GCC_CPUSS_RBCPR_CLK 18 -#define GCC_DDRSS_GPU_AXI_CLK 19 -#define GCC_DISP_AHB_CLK 20 -#define GCC_DISP_HF_AXI_CLK 21 -#define GCC_DISP_SF_AXI_CLK 22 -#define GCC_DISP_XO_CLK 23 -#define GCC_EMAC_AXI_CLK 24 -#define GCC_EMAC_PTP_CLK 25 -#define GCC_EMAC_PTP_CLK_SRC 26 -#define GCC_EMAC_RGMII_CLK 27 -#define GCC_EMAC_RGMII_CLK_SRC 28 -#define GCC_EMAC_SLV_AHB_CLK 29 -#define GCC_GP1_CLK 30 -#define GCC_GP1_CLK_SRC 31 -#define GCC_GP2_CLK 32 -#define GCC_GP2_CLK_SRC 33 -#define GCC_GP3_CLK 34 -#define GCC_GP3_CLK_SRC 35 -#define GCC_GPU_CFG_AHB_CLK 36 -#define GCC_GPU_GPLL0_CLK_SRC 37 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 38 -#define GCC_GPU_IREF_CLK 39 -#define GCC_GPU_MEMNOC_GFX_CLK 40 -#define GCC_GPU_SNOC_DVM_GFX_CLK 41 -#define GCC_NPU_AT_CLK 42 -#define GCC_NPU_AXI_CLK 43 -#define GCC_NPU_CFG_AHB_CLK 44 -#define GCC_NPU_GPLL0_CLK_SRC 45 -#define GCC_NPU_GPLL0_DIV_CLK_SRC 46 -#define GCC_NPU_TRIG_CLK 47 -#define GCC_PCIE0_PHY_REFGEN_CLK 48 -#define GCC_PCIE1_PHY_REFGEN_CLK 49 -#define GCC_PCIE_0_AUX_CLK 50 -#define GCC_PCIE_0_AUX_CLK_SRC 51 -#define GCC_PCIE_0_CFG_AHB_CLK 52 -#define GCC_PCIE_0_CLKREF_CLK 53 -#define GCC_PCIE_0_MSTR_AXI_CLK 54 -#define GCC_PCIE_0_PIPE_CLK 55 -#define GCC_PCIE_0_SLV_AXI_CLK 56 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 -#define GCC_PCIE_1_AUX_CLK 58 -#define GCC_PCIE_1_AUX_CLK_SRC 59 -#define GCC_PCIE_1_CFG_AHB_CLK 60 -#define GCC_PCIE_1_CLKREF_CLK 61 -#define GCC_PCIE_1_MSTR_AXI_CLK 62 -#define GCC_PCIE_1_PIPE_CLK 63 -#define GCC_PCIE_1_SLV_AXI_CLK 64 -#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65 -#define GCC_PCIE_PHY_AUX_CLK 66 -#define GCC_PCIE_PHY_REFGEN_CLK_SRC 67 -#define GCC_PDM2_CLK 68 -#define GCC_PDM2_CLK_SRC 69 -#define GCC_PDM_AHB_CLK 70 -#define GCC_PDM_XO4_CLK 71 -#define GCC_PRNG_AHB_CLK 72 -#define GCC_QMIP_CAMERA_NRT_AHB_CLK 73 -#define GCC_QMIP_CAMERA_RT_AHB_CLK 74 -#define GCC_QMIP_DISP_AHB_CLK 75 -#define GCC_QMIP_VIDEO_CVP_AHB_CLK 76 -#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 77 -#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 78 -#define GCC_QSPI_CORE_CLK 79 -#define GCC_QSPI_CORE_CLK_SRC 80 -#define GCC_QUPV3_WRAP0_S0_CLK 81 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 82 -#define GCC_QUPV3_WRAP0_S1_CLK 83 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 84 -#define GCC_QUPV3_WRAP0_S2_CLK 85 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 86 -#define GCC_QUPV3_WRAP0_S3_CLK 87 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 88 -#define GCC_QUPV3_WRAP0_S4_CLK 89 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 90 -#define GCC_QUPV3_WRAP0_S5_CLK 91 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 92 -#define GCC_QUPV3_WRAP0_S6_CLK 93 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 94 -#define GCC_QUPV3_WRAP0_S7_CLK 95 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 96 -#define GCC_QUPV3_WRAP1_S0_CLK 97 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98 -#define GCC_QUPV3_WRAP1_S1_CLK 99 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100 -#define GCC_QUPV3_WRAP1_S2_CLK 101 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102 -#define GCC_QUPV3_WRAP1_S3_CLK 103 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104 -#define GCC_QUPV3_WRAP1_S4_CLK 105 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106 -#define GCC_QUPV3_WRAP1_S5_CLK 107 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108 -#define GCC_QUPV3_WRAP2_S0_CLK 109 -#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110 -#define GCC_QUPV3_WRAP2_S1_CLK 111 -#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112 -#define GCC_QUPV3_WRAP2_S2_CLK 113 -#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114 -#define GCC_QUPV3_WRAP2_S3_CLK 115 -#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116 -#define GCC_QUPV3_WRAP2_S4_CLK 117 -#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118 -#define GCC_QUPV3_WRAP2_S5_CLK 119 -#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124 -#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125 -#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126 -#define GCC_SDCC2_AHB_CLK 127 -#define GCC_SDCC2_APPS_CLK 128 -#define GCC_SDCC2_APPS_CLK_SRC 129 -#define GCC_SDCC4_AHB_CLK 130 -#define GCC_SDCC4_APPS_CLK 131 -#define GCC_SDCC4_APPS_CLK_SRC 132 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 133 -#define GCC_TSIF_AHB_CLK 134 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 135 -#define GCC_TSIF_REF_CLK 136 -#define GCC_TSIF_REF_CLK_SRC 137 -#define GCC_UFS_CARD_AHB_CLK 138 -#define GCC_UFS_CARD_AXI_CLK 139 -#define GCC_UFS_CARD_AXI_CLK_SRC 140 -#define GCC_UFS_CARD_AXI_HW_CTL_CLK 141 -#define GCC_UFS_CARD_CLKREF_CLK 142 -#define GCC_UFS_CARD_ICE_CORE_CLK 143 -#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 144 -#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 145 -#define GCC_UFS_CARD_PHY_AUX_CLK 146 -#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 147 -#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 148 -#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 149 -#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 150 -#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 151 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK 152 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 153 -#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 154 -#define GCC_UFS_MEM_CLKREF_CLK 155 -#define GCC_UFS_PHY_AHB_CLK 156 -#define GCC_UFS_PHY_AXI_CLK 157 -#define GCC_UFS_PHY_AXI_CLK_SRC 158 -#define GCC_UFS_PHY_AXI_HW_CTL_CLK 159 -#define GCC_UFS_PHY_ICE_CORE_CLK 160 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161 -#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 162 -#define GCC_UFS_PHY_PHY_AUX_CLK 163 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 164 -#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 166 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 167 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 169 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 170 -#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 171 -#define GCC_USB30_PRIM_MASTER_CLK 172 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 173 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 174 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 175 -#define GCC_USB30_PRIM_SLEEP_CLK 176 -#define GCC_USB30_SEC_MASTER_CLK 177 -#define GCC_USB30_SEC_MASTER_CLK_SRC 178 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 179 -#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 180 -#define GCC_USB30_SEC_SLEEP_CLK 181 -#define GCC_USB3_PRIM_CLKREF_CLK 182 -#define GCC_USB3_PRIM_PHY_AUX_CLK 183 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 184 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 185 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 186 -#define GCC_USB3_SEC_CLKREF_CLK 187 -#define GCC_USB3_SEC_PHY_AUX_CLK 188 -#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 189 -#define GCC_USB3_SEC_PHY_COM_AUX_CLK 190 -#define GCC_USB3_SEC_PHY_PIPE_CLK 191 -#define GCC_VIDEO_AHB_CLK 192 -#define GCC_VIDEO_AXI0_CLK 193 -#define GCC_VIDEO_AXI1_CLK 194 -#define GCC_VIDEO_AXIC_CLK 195 -#define GCC_VIDEO_XO_CLK 196 -#define GPLL0 197 -#define GPLL0_OUT_EVEN 198 -#define GPLL7 199 -#define GPLL9 200 +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL4 2 +#define GPLL7 3 +#define GPLL9 4 +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 5 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 6 +#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 7 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 8 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 9 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 10 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 11 +#define GCC_BOOT_ROM_AHB_CLK 12 +#define GCC_CAMERA_AHB_CLK 13 +#define GCC_CAMERA_HF_AXI_CLK 14 +#define GCC_CAMERA_SF_AXI_CLK 15 +#define GCC_CAMERA_XO_CLK 16 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 18 +#define GCC_CPUSS_AHB_CLK 19 +#define GCC_CPUSS_AHB_CLK_SRC 20 +#define GCC_CPUSS_DVM_BUS_CLK 21 +#define GCC_CPUSS_GNOC_CLK 22 +#define GCC_CPUSS_RBCPR_CLK 23 +#define GCC_DDRSS_GPU_AXI_CLK 24 +#define GCC_DISP_AHB_CLK 25 +#define GCC_DISP_HF_AXI_CLK 26 +#define GCC_DISP_SF_AXI_CLK 27 +#define GCC_DISP_XO_CLK 28 +#define GCC_EMAC_AXI_CLK 29 +#define GCC_EMAC_PTP_CLK 30 +#define GCC_EMAC_PTP_CLK_SRC 31 +#define GCC_EMAC_RGMII_CLK 32 +#define GCC_EMAC_RGMII_CLK_SRC 33 +#define GCC_EMAC_SLV_AHB_CLK 34 +#define GCC_GP1_CLK 35 +#define GCC_GP1_CLK_SRC 36 +#define GCC_GP2_CLK 37 +#define GCC_GP2_CLK_SRC 38 +#define GCC_GP3_CLK 39 +#define GCC_GP3_CLK_SRC 40 +#define GCC_GPU_CFG_AHB_CLK 41 +#define GCC_GPU_GPLL0_CLK_SRC 42 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 43 +#define GCC_GPU_IREF_CLK 44 +#define GCC_GPU_MEMNOC_GFX_CLK 45 +#define GCC_GPU_SNOC_DVM_GFX_CLK 46 +#define GCC_NPU_AT_CLK 47 +#define GCC_NPU_AXI_CLK 48 +#define GCC_NPU_CFG_AHB_CLK 49 +#define GCC_NPU_GPLL0_CLK_SRC 50 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 51 +#define GCC_NPU_TRIG_CLK 52 +#define GCC_PCIE0_PHY_REFGEN_CLK 53 +#define GCC_PCIE1_PHY_REFGEN_CLK 54 +#define GCC_PCIE_0_AUX_CLK 55 +#define GCC_PCIE_0_AUX_CLK_SRC 56 +#define GCC_PCIE_0_CFG_AHB_CLK 57 +#define GCC_PCIE_0_CLKREF_CLK 58 +#define GCC_PCIE_0_MSTR_AXI_CLK 59 +#define GCC_PCIE_0_PIPE_CLK 60 +#define GCC_PCIE_0_SLV_AXI_CLK 61 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 62 +#define GCC_PCIE_1_AUX_CLK 63 +#define GCC_PCIE_1_AUX_CLK_SRC 64 +#define GCC_PCIE_1_CFG_AHB_CLK 65 +#define GCC_PCIE_1_CLKREF_CLK 66 +#define GCC_PCIE_1_MSTR_AXI_CLK 67 +#define GCC_PCIE_1_PIPE_CLK 68 +#define GCC_PCIE_1_SLV_AXI_CLK 69 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 70 +#define GCC_PCIE_PHY_AUX_CLK 71 +#define GCC_PCIE_PHY_REFGEN_CLK_SRC 72 +#define GCC_PDM2_CLK 73 +#define GCC_PDM2_CLK_SRC 74 +#define GCC_PDM_AHB_CLK 75 +#define GCC_PDM_XO4_CLK 76 +#define GCC_PRNG_AHB_CLK 77 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 78 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 79 +#define GCC_QMIP_DISP_AHB_CLK 80 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 81 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 82 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 83 +#define GCC_QSPI_CORE_CLK 84 +#define GCC_QSPI_CORE_CLK_SRC 85 +#define GCC_QUPV3_WRAP0_S0_CLK 86 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 87 +#define GCC_QUPV3_WRAP0_S1_CLK 88 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 89 +#define GCC_QUPV3_WRAP0_S2_CLK 90 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 91 +#define GCC_QUPV3_WRAP0_S3_CLK 92 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 93 +#define GCC_QUPV3_WRAP0_S4_CLK 94 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 95 +#define GCC_QUPV3_WRAP0_S5_CLK 96 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 97 +#define GCC_QUPV3_WRAP0_S6_CLK 98 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 99 +#define GCC_QUPV3_WRAP0_S7_CLK 100 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 101 +#define GCC_QUPV3_WRAP1_S0_CLK 102 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 103 +#define GCC_QUPV3_WRAP1_S1_CLK 104 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 105 +#define GCC_QUPV3_WRAP1_S2_CLK 106 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 107 +#define GCC_QUPV3_WRAP1_S3_CLK 108 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 109 +#define GCC_QUPV3_WRAP1_S4_CLK 110 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 111 +#define GCC_QUPV3_WRAP1_S5_CLK 112 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 113 +#define GCC_QUPV3_WRAP2_S0_CLK 114 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 115 +#define GCC_QUPV3_WRAP2_S1_CLK 116 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 117 +#define GCC_QUPV3_WRAP2_S2_CLK 118 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 119 +#define GCC_QUPV3_WRAP2_S3_CLK 120 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 121 +#define GCC_QUPV3_WRAP2_S4_CLK 122 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 123 +#define GCC_QUPV3_WRAP2_S5_CLK 124 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 125 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 126 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 127 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 128 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 129 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 130 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 131 +#define GCC_SDCC2_AHB_CLK 132 +#define GCC_SDCC2_APPS_CLK 133 +#define GCC_SDCC2_APPS_CLK_SRC 134 +#define GCC_SDCC4_AHB_CLK 135 +#define GCC_SDCC4_APPS_CLK 136 +#define GCC_SDCC4_APPS_CLK_SRC 137 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 138 +#define GCC_TSIF_AHB_CLK 139 +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 140 +#define GCC_TSIF_REF_CLK 141 +#define GCC_TSIF_REF_CLK_SRC 142 +#define GCC_UFS_CARD_AHB_CLK 143 +#define GCC_UFS_CARD_AXI_CLK 144 +#define GCC_UFS_CARD_AXI_CLK_SRC 145 +#define GCC_UFS_CARD_AXI_HW_CTL_CLK 146 +#define GCC_UFS_CARD_CLKREF_CLK 147 +#define GCC_UFS_CARD_ICE_CORE_CLK 148 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 149 +#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 150 +#define GCC_UFS_CARD_PHY_AUX_CLK 151 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 152 +#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 153 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 154 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 155 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 156 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 157 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 158 +#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 159 +#define GCC_UFS_MEM_CLKREF_CLK 160 +#define GCC_UFS_PHY_AHB_CLK 161 +#define GCC_UFS_PHY_AXI_CLK 162 +#define GCC_UFS_PHY_AXI_CLK_SRC 163 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 164 +#define GCC_UFS_PHY_ICE_CORE_CLK 165 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 166 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 167 +#define GCC_UFS_PHY_PHY_AUX_CLK 168 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 169 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 170 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 171 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 172 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 173 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 174 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 175 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 176 +#define GCC_USB30_PRIM_MASTER_CLK 177 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 178 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 179 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 180 +#define GCC_USB30_PRIM_SLEEP_CLK 181 +#define GCC_USB30_SEC_MASTER_CLK 182 +#define GCC_USB30_SEC_MASTER_CLK_SRC 183 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 184 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 185 +#define GCC_USB30_SEC_SLEEP_CLK 186 +#define GCC_USB3_PRIM_CLKREF_CLK 187 +#define GCC_USB3_PRIM_PHY_AUX_CLK 188 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 189 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 190 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 191 +#define GCC_USB3_SEC_CLKREF_CLK 192 +#define GCC_USB3_SEC_PHY_AUX_CLK 193 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 194 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 195 +#define GCC_USB3_SEC_PHY_PIPE_CLK 196 +#define GCC_VIDEO_AHB_CLK 197 +#define GCC_VIDEO_AXI0_CLK 198 +#define GCC_VIDEO_AXI1_CLK 199 +#define GCC_VIDEO_AXIC_CLK 200 +#define GCC_VIDEO_XO_CLK 201 + +/* GCC power domains */ +#define EMAC_GDSC 0 +#define PCIE_0_GDSC 1 +#define PCIE_1_GDSC 2 +#define UFS_CARD_GDSC 3 +#define UFS_PHY_GDSC 4 +#define USB30_PRIM_GDSC 5 +#define USB30_SEC_GDSC 6 /* Reset clocks */ -#define GCC_EMAC_BCR 0 -#define GCC_GPU_BCR 1 -#define GCC_MMSS_BCR 2 -#define GCC_NPU_BCR 3 -#define GCC_PCIE_0_BCR 4 -#define GCC_PCIE_0_PHY_BCR 5 -#define GCC_PCIE_1_BCR 6 -#define GCC_PCIE_1_PHY_BCR 7 -#define GCC_PCIE_PHY_BCR 8 -#define GCC_PDM_BCR 9 -#define GCC_PRNG_BCR 10 -#define GCC_QSPI_BCR 11 -#define GCC_QUPV3_WRAPPER_0_BCR 12 -#define GCC_QUPV3_WRAPPER_1_BCR 13 -#define GCC_QUPV3_WRAPPER_2_BCR 14 -#define GCC_QUSB2PHY_PRIM_BCR 15 -#define GCC_QUSB2PHY_SEC_BCR 16 -#define GCC_USB3_PHY_PRIM_BCR 17 -#define GCC_USB3_DP_PHY_PRIM_BCR 18 -#define GCC_USB3_PHY_SEC_BCR 19 -#define GCC_USB3PHY_PHY_SEC_BCR 20 -#define GCC_SDCC2_BCR 21 -#define GCC_SDCC4_BCR 22 -#define GCC_TSIF_BCR 23 -#define GCC_UFS_CARD_BCR 24 -#define GCC_UFS_PHY_BCR 25 -#define GCC_USB30_PRIM_BCR 26 -#define GCC_USB30_SEC_BCR 27 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 +#define GCC_EMAC_BCR 0 +#define GCC_GPU_BCR 1 +#define GCC_MMSS_BCR 2 +#define GCC_NPU_BCR 3 +#define GCC_PCIE_0_BCR 4 +#define GCC_PCIE_0_PHY_BCR 5 +#define GCC_PCIE_1_BCR 6 +#define GCC_PCIE_1_PHY_BCR 7 +#define GCC_PCIE_PHY_BCR 8 +#define GCC_PDM_BCR 9 +#define GCC_PRNG_BCR 10 +#define GCC_QSPI_BCR 11 +#define GCC_QUPV3_WRAPPER_0_BCR 12 +#define GCC_QUPV3_WRAPPER_1_BCR 13 +#define GCC_QUPV3_WRAPPER_2_BCR 14 +#define GCC_QUSB2PHY_PRIM_BCR 15 +#define GCC_QUSB2PHY_SEC_BCR 16 +#define GCC_USB3_PHY_PRIM_BCR 17 +#define GCC_USB3_DP_PHY_PRIM_BCR 18 +#define GCC_USB3_PHY_SEC_BCR 19 +#define GCC_USB3PHY_PHY_SEC_BCR 20 +#define GCC_SDCC2_BCR 21 +#define GCC_SDCC4_BCR 22 +#define GCC_TSIF_BCR 23 +#define GCC_UFS_CARD_BCR 24 +#define GCC_UFS_PHY_BCR 25 +#define GCC_USB30_PRIM_BCR 26 +#define GCC_USB30_SEC_BCR 27 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 +#define GCC_VIDEO_AXIC_CLK_BCR 29 +#define GCC_VIDEO_AXI0_CLK_BCR 30 +#define GCC_VIDEO_AXI1_CLK_BCR 31 #endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8150.h b/include/dt-bindings/clock/qcom,gpucc-sm8150.h new file mode 100644 index 000000000000..6c9ab7c00abc --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8150.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL1 0 +#define GPU_CC_AHB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CX_SNOC_DVM_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_GMU_CLK_SRC 7 +#define GPU_CC_GX_GMU_CLK 8 +#define GPU_CC_SLEEP_CLK 9 + +/* GPU_CC power domains */ +#define CX_GDSC 0 +#define GX_GDSC 1 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 2 +#define GPUCC_GPU_CC_GMU_BCR 3 +#define GPUCC_GPU_CC_GX_BCR 4 +#define GPUCC_GPU_CC_SPDM_BCR 5 +#define GPUCC_GPU_CC_XO_BCR 6 + +#endif diff --git a/include/dt-bindings/clock/qcom,npucc-sm8150.h b/include/dt-bindings/clock/qcom,npucc-sm8150.h new file mode 100644 index 000000000000..eba659b07a93 --- /dev/null +++ b/include/dt-bindings/clock/qcom,npucc-sm8150.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NPU_CC_SM8150_H +#define _DT_BINDINGS_CLK_QCOM_NPU_CC_SM8150_H + +/* NPU_CC clocks */ +#define NPU_CC_PLL0 0 +#define NPU_CC_PLL1 1 +#define NPU_CC_ARMWIC_CORE_CLK 2 +#define NPU_CC_BTO_CORE_CLK 3 +#define NPU_CC_BWMON_CLK 4 +#define NPU_CC_CAL_DP_CDC_CLK 5 +#define NPU_CC_CAL_DP_CLK 6 +#define NPU_CC_CAL_DP_CLK_SRC 7 +#define NPU_CC_COMP_NOC_AXI_CLK 8 +#define NPU_CC_CONF_NOC_AHB_CLK 9 +#define NPU_CC_NPU_CORE_APB_CLK 10 +#define NPU_CC_NPU_CORE_ATB_CLK 11 +#define NPU_CC_NPU_CORE_CLK 12 +#define NPU_CC_NPU_CORE_CLK_SRC 13 +#define NPU_CC_NPU_CORE_CTI_CLK 14 +#define NPU_CC_NPU_CPC_CLK 15 +#define NPU_CC_NPU_CPC_TIMER_CLK 16 +#define NPU_CC_PERF_CNT_CLK 17 +#define NPU_CC_QTIMER_CORE_CLK 18 +#define NPU_CC_SLEEP_CLK 19 +#define NPU_CC_XO_CLK 20 + +/* NPU_CC power domains */ +#define NPU_CORE_GDSC 0 + +/* NPU_CC resets */ +#define NPU_CC_CAL_DP_BCR 0 +#define NPU_CC_NPU_CORE_BCR 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,scc-sm8150.h b/include/dt-bindings/clock/qcom,scc-sm8150.h new file mode 100644 index 000000000000..99ca3e1a9a2d --- /dev/null +++ b/include/dt-bindings/clock/qcom,scc-sm8150.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SCC_SM8150_H +#define _DT_BINDINGS_CLK_QCOM_SCC_SM8150_H + +/* SCC clocks */ +#define SCC_PLL 0 +#define SCC_PLL_OUT_EVEN 1 +#define SCC_MAIN_RCG_CLK_SRC 2 +#define SCC_QUPV3_2XCORE_CLK 3 +#define SCC_QUPV3_CORE_CLK 4 +#define SCC_QUPV3_M_HCLK_CLK 5 +#define SCC_QUPV3_S_HCLK_CLK 6 +#define SCC_QUPV3_SE0_CLK 7 +#define SCC_QUPV3_SE0_CLK_SRC 8 +#define SCC_QUPV3_SE1_CLK 9 +#define SCC_QUPV3_SE1_CLK_SRC 10 +#define SCC_QUPV3_SE2_CLK 11 +#define SCC_QUPV3_SE2_CLK_SRC 12 +#define SCC_QUPV3_SE3_CLK 13 +#define SCC_QUPV3_SE3_CLK_SRC 14 +#define SCC_QUPV3_SE4_CLK 15 +#define SCC_QUPV3_SE4_CLK_SRC 16 +#define SCC_QUPV3_SE5_CLK 17 +#define SCC_QUPV3_SE5_CLK_SRC 18 + +#endif diff --git a/include/dt-bindings/clock/qcom,videocc-sm8150.h b/include/dt-bindings/clock/qcom,videocc-sm8150.h new file mode 100644 index 000000000000..cbf12c325342 --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sm8150.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H + +/* VIDEO_CC clocks */ +#define VIDEO_PLL0 0 +#define VIDEO_CC_IRIS_AHB_CLK 1 +#define VIDEO_CC_IRIS_CLK_SRC 2 +#define VIDEO_CC_MVS0_CORE_CLK 3 +#define VIDEO_CC_MVS1_CORE_CLK 4 +#define VIDEO_CC_MVSC_CORE_CLK 5 +#define VIDEO_CC_XO_CLK 6 + +/* VIDEO_CC power domains */ +#define MVS0_GDSC 0 +#define MVS1_GDSC 1 +#define MVSC_GDSC 2 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS1_BCR 2 +#define VIDEO_CC_MVSC_BCR 3 +#define VIDEO_CC_MVSC_CORE_CLK_BCR 4 + +#endif