mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-14 00:24:41 -04:00
regulator: separated slg51000 driver
Racer use slg5bm43670 driver, it should be separated from others. Racer_turbo/Smith use slg51000 folder, and Racer use slg5bm43670 folder. slg5bm43670 driver is provided by FAE, it has interrupt issue, it will be fixed by updated driver later. Change-Id: Ibf87d63d02621bf6fb3dfbd6bc16fa437ef6935f Signed-off-by: liuwang2 <liuwang2@lenovo.com> Reviewed-on: https://gerrit.mot.com/1476364 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Jian Zhang <zhangjo@motorola.com> Reviewed-by: Long Cheng <chengl1@motorola.com> Reviewed-by: Zhenxin Xi <xizx@motorola.com> Submit-Approved: Jira Key
This commit is contained in:
liuwang2
parent
4745d227ce
commit
acf273cda1
11 changed files with 1070 additions and 6 deletions
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@ -1,9 +1,4 @@
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DLKM_DIR := motorola/kernel/modules
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LOCAL_PATH := $(call my-dir)
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include $(CLEAR_VARS)
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LOCAL_MODULE := slg51000.ko
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LOCAL_MODULE_TAGS := optional
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LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
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include $(DLKM_DIR)/AndroidKernelModule.mk
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include $(call first-makefiles-under,$(LOCAL_PATH))
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9
drivers/regulator/slg51000/Android.mk
Normal file
9
drivers/regulator/slg51000/Android.mk
Normal file
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@ -0,0 +1,9 @@
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DLKM_DIR := motorola/kernel/modules
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LOCAL_PATH := $(call my-dir)
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include $(CLEAR_VARS)
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LOCAL_MODULE := slg51000.ko
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LOCAL_MODULE_TAGS := optional
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LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
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include $(DLKM_DIR)/AndroidKernelModule.mk
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9
drivers/regulator/slg5bm43670/Android.mk
Normal file
9
drivers/regulator/slg5bm43670/Android.mk
Normal file
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@ -0,0 +1,9 @@
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DLKM_DIR := motorola/kernel/modules
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LOCAL_PATH := $(call my-dir)
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include $(CLEAR_VARS)
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LOCAL_MODULE := slg5bm43670.ko
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LOCAL_MODULE_TAGS := optional
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LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
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include $(DLKM_DIR)/AndroidKernelModule.mk
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5
drivers/regulator/slg5bm43670/Kbuild
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5
drivers/regulator/slg5bm43670/Kbuild
Normal file
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@ -0,0 +1,5 @@
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EXTRA_CFLAGS += -Wall
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EXTRA_CFLAGS += -I$(TOP)/motorola/kernel/modules/include
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slg5bm43670-objs += slg5bm43670-regulator.o
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obj-m += slg5bm43670.o
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10
drivers/regulator/slg5bm43670/Makefile
Normal file
10
drivers/regulator/slg5bm43670/Makefile
Normal file
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@ -0,0 +1,10 @@
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KERNEL_SRC ?= /lib/modules/$(shell uname -r)/build
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all:
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$(MAKE) -C $(KERNEL_SRC) M=$(shell pwd) modules $(KBUILD_OPTIONS)
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modules_install:
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$(MAKE) INSTALL_MOD_STRIP=1 -C $(KERNEL_SRC) M=$(shell pwd) modules_install
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clean:
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$(MAKE) -C $(KERNEL_SRC) M=$(PWD) clean
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543
drivers/regulator/slg5bm43670/slg5bm43670-regulator.c
Normal file
543
drivers/regulator/slg5bm43670/slg5bm43670-regulator.c
Normal file
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@ -0,0 +1,543 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* SLG51000 High PSRR, Multi-Output Regulators
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* Copyright (C) 2019 Dialog Semiconductor
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*
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* Author: Eric Jeong, Dialog Semiconductor
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*/
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#include <linux/err.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/of_regulator.h>
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#include "slg5bm43670-regulator.h"
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#define SLG51000_SCTL_EVT 7
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#define SLG51000_MAX_EVT_REGISTER 8
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enum slg51000_regulators {
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SLG51000_REGULATOR_LDO1 = 0,
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SLG51000_REGULATOR_LDO2,
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SLG51000_REGULATOR_LDO3,
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SLG51000_REGULATOR_LDO4,
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SLG51000_REGULATOR_LDO5,
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SLG51000_REGULATOR_LDO6,
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SLG51000_REGULATOR_LDO7,
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SLG51000_MAX_REGULATORS,
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};
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struct slg51000 {
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struct device *dev;
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struct regmap *regmap;
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struct regulator_desc *rdesc[SLG51000_MAX_REGULATORS];
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struct regulator_dev *rdev[SLG51000_MAX_REGULATORS];
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int chip_irq;
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int chip_cs_pin;
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};
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struct slg51000_evt_sta {
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unsigned int ereg;
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unsigned int sreg;
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};
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static const struct slg51000_evt_sta es_reg[SLG51000_MAX_EVT_REGISTER] = {
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{SLG51000_LDO1_EVENT, SLG51000_LDO1_STATUS},
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{SLG51000_LDO2_EVENT, SLG51000_LDO2_STATUS},
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{SLG51000_LDO3_EVENT, SLG51000_LDO3_STATUS},
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{SLG51000_LDO4_EVENT, SLG51000_LDO4_STATUS},
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{SLG51000_LDO5_EVENT, SLG51000_LDO5_STATUS},
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{SLG51000_LDO6_EVENT, SLG51000_LDO6_STATUS},
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{SLG51000_LDO7_EVENT, SLG51000_LDO7_STATUS},
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{SLG51000_SYSCTL_EVENT, SLG51000_SYSCTL_STATUS},
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};
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static const struct regmap_range slg51000_writeable_ranges[] = {
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regmap_reg_range(SLG51000_SYSCTL_MATRIX_CONF_A,
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SLG51000_SYSCTL_MATRIX_CONF_A),
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regmap_reg_range(SLG51000_LDO1_VSEL, SLG51000_LDO1_VSEL),
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regmap_reg_range(SLG51000_LDO1_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO1_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO1_IRQ_MASK, SLG51000_LDO1_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO2_VSEL, SLG51000_LDO2_VSEL),
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regmap_reg_range(SLG51000_LDO2_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO2_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO2_IRQ_MASK, SLG51000_LDO2_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO3_VSEL, SLG51000_LDO3_VSEL),
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regmap_reg_range(SLG51000_LDO3_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO3_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO3_IRQ_MASK, SLG51000_LDO3_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO4_VSEL, SLG51000_LDO4_VSEL),
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regmap_reg_range(SLG51000_LDO4_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO4_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO4_IRQ_MASK, SLG51000_LDO4_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO5_VSEL, SLG51000_LDO5_VSEL),
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regmap_reg_range(SLG51000_LDO5_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO5_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO5_IRQ_MASK, SLG51000_LDO5_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO6_VSEL, SLG51000_LDO6_VSEL),
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regmap_reg_range(SLG51000_LDO6_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO6_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO6_IRQ_MASK, SLG51000_LDO6_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO7_VSEL, SLG51000_LDO7_VSEL),
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regmap_reg_range(SLG51000_LDO7_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO7_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO7_IRQ_MASK, SLG51000_LDO7_IRQ_MASK),
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};
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static const struct regmap_range slg51000_readable_ranges[] = {
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regmap_reg_range(SLG51000_SYSCTL_PATN_ID_B0,
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SLG51000_SYSCTL_PATN_ID_B2),
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regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_A,
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SLG51000_SYSCTL_SYS_CONF_A),
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regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_D,
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SLG51000_SYSCTL_MATRIX_CONF_B),
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regmap_reg_range(SLG51000_SYSCTL_REFGEN_CONF_C,
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SLG51000_SYSCTL_UVLO_CONF_A),
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regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1, SLG51000_SYSCTL_IRQ_MASK),
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regmap_reg_range(SLG51000_IO_GPIO1_CONF, SLG51000_IO_GPIO_STATUS),
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regmap_reg_range(SLG51000_LUTARRAY_LUT_VAL_0,
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SLG51000_LUTARRAY_LUT_VAL_11),
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regmap_reg_range(SLG51000_MUXARRAY_INPUT_SEL_0,
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SLG51000_MUXARRAY_INPUT_SEL_63),
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regmap_reg_range(SLG51000_PWRSEQ_RESOURCE_EN_0,
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SLG51000_PWRSEQ_INPUT_SENSE_CONF_B),
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regmap_reg_range(SLG51000_LDO1_VSEL, SLG51000_LDO1_VSEL),
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regmap_reg_range(SLG51000_LDO1_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO1_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO1_TRIM2, SLG51000_LDO1_TRIM2),
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regmap_reg_range(SLG51000_LDO1_VSEL_ACTUAL, SLG51000_LDO1_VSEL_ACTUAL),
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regmap_reg_range(SLG51000_LDO1_EVENT, SLG51000_LDO1_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO2_VSEL, SLG51000_LDO2_VSEL),
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regmap_reg_range(SLG51000_LDO2_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO2_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO2_TRIM2, SLG51000_LDO2_TRIM2),
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regmap_reg_range(SLG51000_LDO2_VSEL_ACTUAL, SLG51000_LDO2_VSEL_ACTUAL),
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regmap_reg_range(SLG51000_LDO2_EVENT, SLG51000_LDO2_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO3_VSEL, SLG51000_LDO3_VSEL),
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regmap_reg_range(SLG51000_LDO3_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO3_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO3_TRIM2, SLG51000_LDO3_VSEL_ACTUAL),
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regmap_reg_range(SLG51000_LDO3_EVENT, SLG51000_LDO3_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO4_VSEL, SLG51000_LDO4_VSEL),
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regmap_reg_range(SLG51000_LDO4_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO4_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO4_TRIM2, SLG51000_LDO4_VSEL_ACTUAL),
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regmap_reg_range(SLG51000_LDO4_EVENT, SLG51000_LDO4_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO5_VSEL, SLG51000_LDO5_VSEL),
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regmap_reg_range(SLG51000_LDO5_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO5_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO5_TRIM2, SLG51000_LDO5_VSEL_ACTUAL),
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regmap_reg_range(SLG51000_LDO5_EVENT, SLG51000_LDO5_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO6_VSEL, SLG51000_LDO6_VSEL),
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regmap_reg_range(SLG51000_LDO6_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO6_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO6_TRIM2, SLG51000_LDO6_VSEL_ACTUAL),
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regmap_reg_range(SLG51000_LDO6_EVENT, SLG51000_LDO6_IRQ_MASK),
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regmap_reg_range(SLG51000_LDO7_VSEL, SLG51000_LDO7_VSEL),
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regmap_reg_range(SLG51000_LDO7_VSEL_RANGE_MASK_MIN,
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SLG51000_LDO7_VSEL_RANGE_MASK_MAX),
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regmap_reg_range(SLG51000_LDO7_TRIM2, SLG51000_LDO7_VSEL_ACTUAL),
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regmap_reg_range(SLG51000_LDO7_EVENT, SLG51000_LDO7_IRQ_MASK),
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regmap_reg_range(SLG51000_LOCK_GLOBAL_LOCK_CTRL1,
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SLG51000_LOCK_GLOBAL_LOCK_CTRL1),
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};
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static const struct regmap_range slg51000_volatile_ranges[] = {
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regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1, SLG51000_SYSCTL_STATUS),
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regmap_reg_range(SLG51000_IO_GPIO_STATUS, SLG51000_IO_GPIO_STATUS),
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regmap_reg_range(SLG51000_LDO1_EVENT, SLG51000_LDO1_STATUS),
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regmap_reg_range(SLG51000_LDO2_EVENT, SLG51000_LDO2_STATUS),
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regmap_reg_range(SLG51000_LDO3_EVENT, SLG51000_LDO3_STATUS),
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regmap_reg_range(SLG51000_LDO4_EVENT, SLG51000_LDO4_STATUS),
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regmap_reg_range(SLG51000_LDO5_EVENT, SLG51000_LDO5_STATUS),
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regmap_reg_range(SLG51000_LDO6_EVENT, SLG51000_LDO6_STATUS),
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regmap_reg_range(SLG51000_LDO7_EVENT, SLG51000_LDO7_STATUS),
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};
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static const struct regmap_access_table slg51000_writeable_table = {
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.yes_ranges = slg51000_writeable_ranges,
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.n_yes_ranges = ARRAY_SIZE(slg51000_writeable_ranges),
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};
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static const struct regmap_access_table slg51000_readable_table = {
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.yes_ranges = slg51000_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(slg51000_readable_ranges),
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};
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static const struct regmap_access_table slg51000_volatile_table = {
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.yes_ranges = slg51000_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(slg51000_volatile_ranges),
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};
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static const struct regmap_config slg51000_regmap_config = {
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0x8000,
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.wr_table = &slg51000_writeable_table,
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.rd_table = &slg51000_readable_table,
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.volatile_table = &slg51000_volatile_table,
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};
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static int slg51000_get_status(struct regulator_dev *rdev)
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{
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struct slg51000 *chip = rdev_get_drvdata(rdev);
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int ret, id = rdev_get_id(rdev);
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unsigned int status;
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ret = regulator_is_enabled_regmap(rdev);
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if (ret < 0) {
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dev_err(chip->dev, "Failed to read enable register(%d)\n",
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ret);
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return ret;
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}
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if (!ret)
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return REGULATOR_STATUS_OFF;
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ret = regmap_read(chip->regmap, es_reg[id].sreg, &status);
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if (ret < 0) {
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dev_err(chip->dev, "Failed to read status register(%d)\n",
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ret);
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return ret;
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}
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if (!(status & SLG51000_STA_ILIM_FLAG_MASK) &&
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(status & SLG51000_STA_VOUT_OK_FLAG_MASK)) {
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if (rdev->desc->n_voltages == 0 &&
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(id == SLG51000_REGULATOR_LDO5 ||
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id == SLG51000_REGULATOR_LDO6))
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return REGULATOR_STATUS_BYPASS;
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else
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return REGULATOR_STATUS_ON;
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} else {
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return REGULATOR_STATUS_ERROR;
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}
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}
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static const struct regulator_ops slg51000_regl_ops = {
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.enable = regulator_enable_regmap,
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.disable = regulator_disable_regmap,
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.is_enabled = regulator_is_enabled_regmap,
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.list_voltage = regulator_list_voltage_linear,
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.map_voltage = regulator_map_voltage_linear,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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.get_status = slg51000_get_status,
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};
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static const struct regulator_ops slg51000_switch_ops = {
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.enable = regulator_enable_regmap,
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.disable = regulator_disable_regmap,
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.is_enabled = regulator_is_enabled_regmap,
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.get_status = slg51000_get_status,
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};
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static int slg51000_of_parse_cb(struct device_node *np,
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const struct regulator_desc *desc,
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struct regulator_config *config)
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{
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int ena_gpio;
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ena_gpio = of_get_named_gpio(np, "enable-gpios", 0);
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if (ena_gpio)
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config->ena_gpio = ena_gpio;
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return 0;
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}
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#define SLG51000_REGL_DESC(_id, _name, _s_name, _min, _step) \
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[SLG51000_REGULATOR_##_id] = { \
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.name = #_name, \
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.supply_name = _s_name, \
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.id = SLG51000_REGULATOR_##_id, \
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.of_match = of_match_ptr(#_name), \
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.of_parse_cb = slg51000_of_parse_cb, \
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.ops = &slg51000_regl_ops, \
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.regulators_node = of_match_ptr("regulators"), \
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.n_voltages = 256, \
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.min_uV = _min, \
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.uV_step = _step, \
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.linear_min_sel = 0, \
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.vsel_mask = SLG51000_VSEL_MASK, \
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.vsel_reg = SLG51000_##_id##_VSEL, \
|
||||
.enable_reg = SLG51000_SYSCTL_MATRIX_CONF_A, \
|
||||
.enable_mask = BIT(SLG51000_REGULATOR_##_id), \
|
||||
.type = REGULATOR_VOLTAGE, \
|
||||
.owner = THIS_MODULE, \
|
||||
}
|
||||
|
||||
static struct regulator_desc regls_desc[SLG51000_MAX_REGULATORS] = {
|
||||
SLG51000_REGL_DESC(LDO1, ldo1, NULL, 2200000, 5000),
|
||||
SLG51000_REGL_DESC(LDO2, ldo2, NULL, 2200000, 5000),
|
||||
SLG51000_REGL_DESC(LDO3, ldo3, "vin3", 1200000, 10000),
|
||||
SLG51000_REGL_DESC(LDO4, ldo4, "vin4", 1200000, 10000),
|
||||
SLG51000_REGL_DESC(LDO5, ldo5, "vin5", 400000, 5000),
|
||||
SLG51000_REGL_DESC(LDO6, ldo6, "vin6", 400000, 5000),
|
||||
SLG51000_REGL_DESC(LDO7, ldo7, "vin7", 1200000, 10000),
|
||||
};
|
||||
|
||||
static int slg51000_regulator_init(struct slg51000 *chip)
|
||||
{
|
||||
struct regulator_config config = { };
|
||||
struct regulator_desc *rdesc;
|
||||
unsigned int reg, val;
|
||||
u8 vsel_range[2];
|
||||
int id, ret = 0;
|
||||
const unsigned int min_regs[SLG51000_MAX_REGULATORS] = {
|
||||
SLG51000_LDO1_VSEL_RANGE_MASK_MIN,
|
||||
SLG51000_LDO2_VSEL_RANGE_MASK_MIN,
|
||||
SLG51000_LDO3_VSEL_RANGE_MASK_MIN,
|
||||
SLG51000_LDO4_VSEL_RANGE_MASK_MIN,
|
||||
SLG51000_LDO5_VSEL_RANGE_MASK_MIN,
|
||||
SLG51000_LDO6_VSEL_RANGE_MASK_MIN,
|
||||
SLG51000_LDO7_VSEL_RANGE_MASK_MIN,
|
||||
};
|
||||
|
||||
for (id = 0; id < SLG51000_MAX_REGULATORS; id++) {
|
||||
chip->rdesc[id] = ®ls_desc[id];
|
||||
rdesc = chip->rdesc[id];
|
||||
config.regmap = chip->regmap;
|
||||
config.dev = chip->dev;
|
||||
config.driver_data = chip;
|
||||
|
||||
ret = regmap_bulk_read(chip->regmap, min_regs[id],
|
||||
vsel_range, 2);
|
||||
if (ret < 0) {
|
||||
dev_err(chip->dev,
|
||||
"Failed to read the MIN register\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
switch (id) {
|
||||
case SLG51000_REGULATOR_LDO5:
|
||||
case SLG51000_REGULATOR_LDO6:
|
||||
if (id == SLG51000_REGULATOR_LDO5)
|
||||
reg = SLG51000_LDO5_TRIM2;
|
||||
else
|
||||
reg = SLG51000_LDO6_TRIM2;
|
||||
|
||||
ret = regmap_read(chip->regmap, reg, &val);
|
||||
if (ret < 0) {
|
||||
dev_err(chip->dev,
|
||||
"Failed to read LDO mode register\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (val & SLG51000_SEL_BYP_MODE_MASK) {
|
||||
rdesc->ops = &slg51000_switch_ops;
|
||||
rdesc->n_voltages = 0;
|
||||
rdesc->min_uV = 0;
|
||||
rdesc->uV_step = 0;
|
||||
rdesc->linear_min_sel = 0;
|
||||
break;
|
||||
}
|
||||
/* Fall through - to the check below.*/
|
||||
|
||||
default:
|
||||
rdesc->linear_min_sel = vsel_range[0];
|
||||
rdesc->n_voltages = vsel_range[1] + 1;
|
||||
rdesc->min_uV = rdesc->min_uV
|
||||
+ (vsel_range[0] * rdesc->uV_step);
|
||||
break;
|
||||
}
|
||||
|
||||
chip->rdev[id] = devm_regulator_register(chip->dev, rdesc,
|
||||
&config);
|
||||
if (IS_ERR(chip->rdev[id])) {
|
||||
ret = PTR_ERR(chip->rdev[id]);
|
||||
dev_err(chip->dev,
|
||||
"Failed to register regulator(%s):%d\n",
|
||||
chip->rdesc[id]->name, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t slg51000_irq_handler(int irq, void *data)
|
||||
{
|
||||
struct slg51000 *chip = data;
|
||||
struct regmap *regmap = chip->regmap;
|
||||
enum { R0 = 0, R1, R2, REG_MAX };
|
||||
u8 evt[SLG51000_MAX_EVT_REGISTER][REG_MAX];
|
||||
int ret, i, handled = IRQ_NONE;
|
||||
|
||||
/* Read event[R0], status[R1] and mask[R2] register */
|
||||
for (i = 0; i < SLG51000_MAX_EVT_REGISTER; i++) {
|
||||
ret = regmap_bulk_read(regmap, es_reg[i].ereg, evt[i], REG_MAX);
|
||||
if (ret < 0) {
|
||||
dev_err(chip->dev,
|
||||
"Failed to read event registers(%d)\n", ret);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < SLG51000_MAX_REGULATORS; i++) {
|
||||
if (!(evt[i][R2] & SLG51000_IRQ_ILIM_FLAG_MASK) &&
|
||||
(evt[i][R0] & SLG51000_EVT_ILIM_FLAG_MASK)) {
|
||||
mutex_lock(&chip->rdev[i]->mutex);
|
||||
regulator_notifier_call_chain(chip->rdev[i],
|
||||
REGULATOR_EVENT_OVER_CURRENT,
|
||||
NULL);
|
||||
mutex_unlock(&chip->rdev[i]->mutex);
|
||||
|
||||
if (evt[i][R1] & SLG51000_STA_ILIM_FLAG_MASK)
|
||||
dev_warn(chip->dev,
|
||||
"Over-current limit(ldo%d)\n", i + 1);
|
||||
handled = IRQ_HANDLED;
|
||||
}
|
||||
}
|
||||
|
||||
if (!(evt[SLG51000_SCTL_EVT][R2] & SLG51000_IRQ_HIGH_TEMP_WARN_MASK) &&
|
||||
(evt[SLG51000_SCTL_EVT][R0] & SLG51000_EVT_HIGH_TEMP_WARN_MASK)) {
|
||||
for (i = 0; i < SLG51000_MAX_REGULATORS; i++) {
|
||||
if (!(evt[i][R1] & SLG51000_STA_ILIM_FLAG_MASK) &&
|
||||
(evt[i][R1] & SLG51000_STA_VOUT_OK_FLAG_MASK)) {
|
||||
mutex_lock(&chip->rdev[i]->mutex);
|
||||
regulator_notifier_call_chain(chip->rdev[i],
|
||||
REGULATOR_EVENT_OVER_TEMP,
|
||||
NULL);
|
||||
mutex_unlock(&chip->rdev[i]->mutex);
|
||||
}
|
||||
}
|
||||
handled = IRQ_HANDLED;
|
||||
if (evt[SLG51000_SCTL_EVT][R1] &
|
||||
SLG51000_STA_HIGH_TEMP_WARN_MASK)
|
||||
dev_warn(chip->dev, "High temperature warning!\n");
|
||||
}
|
||||
|
||||
return handled;
|
||||
}
|
||||
|
||||
static void slg51000_clear_fault_log(struct slg51000 *chip)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
int ret = 0;
|
||||
|
||||
ret = regmap_read(chip->regmap, SLG51000_SYSCTL_FAULT_LOG1, &val);
|
||||
if (ret < 0) {
|
||||
dev_err(chip->dev, "Failed to read Fault log register\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (val & SLG51000_FLT_OVER_TEMP_MASK)
|
||||
dev_dbg(chip->dev, "Fault log: FLT_OVER_TEMP\n");
|
||||
if (val & SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK)
|
||||
dev_dbg(chip->dev, "Fault log: FLT_POWER_SEQ_CRASH_REQ\n");
|
||||
if (val & SLG51000_FLT_RST_MASK)
|
||||
dev_dbg(chip->dev, "Fault log: FLT_RST\n");
|
||||
if (val & SLG51000_FLT_POR_MASK)
|
||||
dev_dbg(chip->dev, "Fault log: FLT_POR\n");
|
||||
}
|
||||
|
||||
static int slg51000_i2c_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct device *dev = &client->dev;
|
||||
struct slg51000 *chip;
|
||||
int error, cs_gpio, ret;
|
||||
|
||||
chip = devm_kzalloc(dev, sizeof(struct slg51000), GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
|
||||
cs_gpio = of_get_named_gpio(dev->of_node, "dlg,cs-gpios", 0);
|
||||
if (cs_gpio > 0) {
|
||||
if (!gpio_is_valid(cs_gpio)) {
|
||||
dev_err(dev, "Invalid chip select pin\n");
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
ret = devm_gpio_request_one(dev, cs_gpio, GPIOF_OUT_INIT_HIGH,
|
||||
"slg51000_cs_pin");
|
||||
if (ret) {
|
||||
dev_err(dev, "GPIO(%d) request failed(%d)\n",
|
||||
cs_gpio, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
chip->chip_cs_pin = cs_gpio;
|
||||
}
|
||||
|
||||
i2c_set_clientdata(client, chip);
|
||||
chip->chip_irq = client->irq;
|
||||
chip->dev = dev;
|
||||
chip->regmap = devm_regmap_init_i2c(client, &slg51000_regmap_config);
|
||||
if (IS_ERR(chip->regmap)) {
|
||||
error = PTR_ERR(chip->regmap);
|
||||
dev_err(dev, "Failed to allocate register map: %d\n",
|
||||
error);
|
||||
return error;
|
||||
}
|
||||
|
||||
mdelay(10);
|
||||
ret = slg51000_regulator_init(chip);
|
||||
if (ret < 0) {
|
||||
dev_err(chip->dev, "Failed to init regulator(%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
slg51000_clear_fault_log(chip);
|
||||
|
||||
if (chip->chip_irq) {
|
||||
ret = devm_request_threaded_irq(dev, chip->chip_irq, NULL,
|
||||
slg51000_irq_handler,
|
||||
(IRQF_TRIGGER_LOW |
|
||||
IRQF_ONESHOT),
|
||||
"slg51000-irq", chip);
|
||||
if (ret != 0) {
|
||||
dev_err(dev, "Failed to request IRQ: %d\n",
|
||||
chip->chip_irq);
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
dev_warn(dev, "No IRQ configured\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int slg51000_i2c_remove(struct i2c_client *client)
|
||||
{
|
||||
struct slg51000 *chip = i2c_get_clientdata(client);
|
||||
struct gpio_desc *desc;
|
||||
int ret = 0;
|
||||
|
||||
if (chip->chip_cs_pin > 0) {
|
||||
desc = gpio_to_desc(chip->chip_cs_pin);
|
||||
ret = gpiod_direction_output_raw(desc, GPIOF_INIT_LOW);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id slg51000_i2c_id[] = {
|
||||
{"slg51000", 0},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, slg51000_i2c_id);
|
||||
|
||||
static struct i2c_driver slg51000_regulator_driver = {
|
||||
.driver = {
|
||||
.name = "slg51000-regulator",
|
||||
},
|
||||
.probe = slg51000_i2c_probe,
|
||||
.remove = slg51000_i2c_remove,
|
||||
.id_table = slg51000_i2c_id,
|
||||
};
|
||||
|
||||
module_i2c_driver(slg51000_regulator_driver);
|
||||
|
||||
MODULE_AUTHOR("Eric Jeong <eric.jeong.opensource@diasemi.com>");
|
||||
MODULE_DESCRIPTION("SLG51000 regulator driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
493
drivers/regulator/slg5bm43670/slg5bm43670-regulator.h
Normal file
493
drivers/regulator/slg5bm43670/slg5bm43670-regulator.h
Normal file
|
|
@ -0,0 +1,493 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* SLG51000 High PSRR, Multi-Output Regulators
|
||||
* Copyright (C) 2019 Dialog Semiconductor
|
||||
*
|
||||
* Author: Eric Jeong, Dialog Semiconductor
|
||||
*/
|
||||
|
||||
#ifndef __SLG51000_REGISTERS_H__
|
||||
#define __SLG51000_REGISTERS_H__
|
||||
|
||||
/* Registers */
|
||||
|
||||
#define SLG51000_SYSCTL_PATN_ID_B0 0x1105
|
||||
#define SLG51000_SYSCTL_PATN_ID_B1 0x1106
|
||||
#define SLG51000_SYSCTL_PATN_ID_B2 0x1107
|
||||
#define SLG51000_SYSCTL_SYS_CONF_A 0x1109
|
||||
#define SLG51000_SYSCTL_SYS_CONF_D 0x110c
|
||||
#define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d
|
||||
#define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e
|
||||
#define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111
|
||||
#define SLG51000_SYSCTL_UVLO_CONF_A 0x1112
|
||||
#define SLG51000_SYSCTL_FAULT_LOG1 0x1115
|
||||
#define SLG51000_SYSCTL_EVENT 0x1116
|
||||
#define SLG51000_SYSCTL_STATUS 0x1117
|
||||
#define SLG51000_SYSCTL_IRQ_MASK 0x1118
|
||||
#define SLG51000_IO_GPIO1_CONF 0x1500
|
||||
#define SLG51000_IO_GPIO2_CONF 0x1501
|
||||
#define SLG51000_IO_GPIO3_CONF 0x1502
|
||||
#define SLG51000_IO_GPIO4_CONF 0x1503
|
||||
#define SLG51000_IO_GPIO5_CONF 0x1504
|
||||
#define SLG51000_IO_GPIO6_CONF 0x1505
|
||||
#define SLG51000_IO_GPIO_STATUS 0x1506
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_0 0x1600
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_1 0x1601
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_2 0x1602
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_3 0x1603
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_4 0x1604
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_5 0x1605
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_6 0x1606
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_7 0x1607
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_8 0x1608
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_9 0x1609
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_10 0x160a
|
||||
#define SLG51000_LUTARRAY_LUT_VAL_11 0x160b
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_0 0x1700
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_1 0x1701
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_2 0x1702
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_3 0x1703
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_4 0x1704
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_5 0x1705
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_6 0x1706
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_7 0x1707
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_8 0x1708
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_9 0x1709
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_10 0x170a
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_11 0x170b
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_12 0x170c
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_13 0x170d
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_14 0x170e
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_15 0x170f
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_16 0x1710
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_17 0x1711
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_18 0x1712
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_19 0x1713
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_20 0x1714
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_21 0x1715
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_22 0x1716
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_23 0x1717
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_24 0x1718
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_25 0x1719
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_26 0x171a
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_27 0x171b
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_28 0x171c
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_29 0x171d
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_30 0x171e
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_31 0x171f
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_32 0x1720
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_33 0x1721
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_34 0x1722
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_35 0x1723
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_36 0x1724
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_37 0x1725
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_38 0x1726
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_39 0x1727
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_40 0x1728
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_41 0x1729
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_42 0x172a
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_43 0x172b
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_44 0x172c
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_45 0x172d
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_46 0x172e
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_47 0x172f
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_48 0x1730
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_49 0x1731
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_50 0x1732
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_51 0x1733
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_52 0x1734
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_53 0x1735
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_54 0x1736
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_55 0x1737
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_56 0x1738
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_57 0x1739
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_58 0x173a
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_59 0x173b
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_60 0x173c
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_61 0x173d
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_62 0x173e
|
||||
#define SLG51000_MUXARRAY_INPUT_SEL_63 0x173f
|
||||
#define SLG51000_PWRSEQ_RESOURCE_EN_0 0x1900
|
||||
#define SLG51000_PWRSEQ_RESOURCE_EN_1 0x1901
|
||||
#define SLG51000_PWRSEQ_RESOURCE_EN_2 0x1902
|
||||
#define SLG51000_PWRSEQ_RESOURCE_EN_3 0x1903
|
||||
#define SLG51000_PWRSEQ_RESOURCE_EN_4 0x1904
|
||||
#define SLG51000_PWRSEQ_RESOURCE_EN_5 0x1905
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 0x1906
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 0x1907
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP1 0x1908
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN1 0x1909
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP2 0x190a
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN2 0x190b
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP3 0x190c
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN3 0x190d
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP4 0x190e
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN4 0x190f
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5 0x1910
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5 0x1911
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A 0x1912
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_B 0x1913
|
||||
#define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C 0x1914
|
||||
#define SLG51000_PWRSEQ_INPUT_SENSE_CONF_A 0x1915
|
||||
#define SLG51000_PWRSEQ_INPUT_SENSE_CONF_B 0x1916
|
||||
#define SLG51000_LDO1_VSEL 0x2000
|
||||
#define SLG51000_LDO1_VSEL_RANGE_MASK_MIN 0x2060
|
||||
#define SLG51000_LDO1_VSEL_RANGE_MASK_MAX 0x2061
|
||||
#define SLG51000_LDO1_TRIM2 0x2063
|
||||
#define SLG51000_LDO1_VSEL_ACTUAL 0x2065
|
||||
#define SLG51000_LDO1_EVENT 0x20c0
|
||||
#define SLG51000_LDO1_STATUS 0x20c1
|
||||
#define SLG51000_LDO1_IRQ_MASK 0x20c2
|
||||
#define SLG51000_LDO2_VSEL 0x2200
|
||||
#define SLG51000_LDO2_VSEL_RANGE_MASK_MIN 0x2260
|
||||
#define SLG51000_LDO2_VSEL_RANGE_MASK_MAX 0x2261
|
||||
#define SLG51000_LDO2_TRIM2 0x2263
|
||||
#define SLG51000_LDO2_VSEL_ACTUAL 0x2265
|
||||
#define SLG51000_LDO2_EVENT 0x22c0
|
||||
#define SLG51000_LDO2_STATUS 0x22c1
|
||||
#define SLG51000_LDO2_IRQ_MASK 0x22c2
|
||||
#define SLG51000_LDO3_VSEL 0x2300
|
||||
#define SLG51000_LDO3_VSEL_RANGE_MASK_MIN 0x2360
|
||||
#define SLG51000_LDO3_VSEL_RANGE_MASK_MAX 0x2361
|
||||
#define SLG51000_LDO3_TRIM2 0x2363
|
||||
#define SLG51000_LDO3_CONF1 0x2364
|
||||
#define SLG51000_LDO3_CONF2 0x2365
|
||||
#define SLG51000_LDO3_VSEL_ACTUAL 0x2366
|
||||
#define SLG51000_LDO3_EVENT 0x23c0
|
||||
#define SLG51000_LDO3_STATUS 0x23c1
|
||||
#define SLG51000_LDO3_IRQ_MASK 0x23c2
|
||||
#define SLG51000_LDO4_VSEL 0x2500
|
||||
#define SLG51000_LDO4_VSEL_RANGE_MASK_MIN 0x2560
|
||||
#define SLG51000_LDO4_VSEL_RANGE_MASK_MAX 0x2561
|
||||
#define SLG51000_LDO4_TRIM2 0x2563
|
||||
#define SLG51000_LDO4_CONF1 0x2564
|
||||
#define SLG51000_LDO4_CONF2 0x2565
|
||||
#define SLG51000_LDO4_VSEL_ACTUAL 0x2566
|
||||
#define SLG51000_LDO4_EVENT 0x25c0
|
||||
#define SLG51000_LDO4_STATUS 0x25c1
|
||||
#define SLG51000_LDO4_IRQ_MASK 0x25c2
|
||||
#define SLG51000_LDO5_VSEL 0x2700
|
||||
#define SLG51000_LDO5_VSEL_RANGE_MASK_MIN 0x2760
|
||||
#define SLG51000_LDO5_VSEL_RANGE_MASK_MAX 0x2761
|
||||
#define SLG51000_LDO5_TRIM2 0x2763
|
||||
#define SLG51000_LDO5_TRIM3 0x2764
|
||||
#define SLG51000_LDO5_CONF1 0x2765
|
||||
#define SLG51000_LDO5_CONF2 0x2766
|
||||
#define SLG51000_LDO5_VSEL_ACTUAL 0x2767
|
||||
#define SLG51000_LDO5_EVENT 0x27c0
|
||||
#define SLG51000_LDO5_STATUS 0x27c1
|
||||
#define SLG51000_LDO5_IRQ_MASK 0x27c2
|
||||
#define SLG51000_LDO6_VSEL 0x2900
|
||||
#define SLG51000_LDO6_VSEL_RANGE_MASK_MIN 0x2960
|
||||
#define SLG51000_LDO6_VSEL_RANGE_MASK_MAX 0x2961
|
||||
#define SLG51000_LDO6_TRIM2 0x2963
|
||||
#define SLG51000_LDO6_TRIM3 0x2964
|
||||
#define SLG51000_LDO6_CONF1 0x2965
|
||||
#define SLG51000_LDO6_CONF2 0x2966
|
||||
#define SLG51000_LDO6_VSEL_ACTUAL 0x2967
|
||||
#define SLG51000_LDO6_EVENT 0x29c0
|
||||
#define SLG51000_LDO6_STATUS 0x29c1
|
||||
#define SLG51000_LDO6_IRQ_MASK 0x29c2
|
||||
#define SLG51000_LDO7_VSEL 0x3100
|
||||
#define SLG51000_LDO7_VSEL_RANGE_MASK_MIN 0x3160
|
||||
#define SLG51000_LDO7_VSEL_RANGE_MASK_MAX 0x3161
|
||||
#define SLG51000_LDO7_TRIM2 0x3163
|
||||
#define SLG51000_LDO7_CONF1 0x3164
|
||||
#define SLG51000_LDO7_CONF2 0x3165
|
||||
#define SLG51000_LDO7_VSEL_ACTUAL 0x3166
|
||||
#define SLG51000_LDO7_EVENT 0x31c0
|
||||
#define SLG51000_LDO7_STATUS 0x31c1
|
||||
#define SLG51000_LDO7_IRQ_MASK 0x31c2
|
||||
#define SLG51000_LOCK_GLOBAL_LOCK_CTRL1 0x8000
|
||||
|
||||
/* Register Bit Fields */
|
||||
|
||||
/* SLG51000_SYSCTL_PATN_ID_B0 = 0x1105 */
|
||||
#define SLG51000_PROGRAMMING_CODE_NUMBER_SHIFT 0
|
||||
#define SLG51000_PROGRAMMING_CODE_NUMBER_MASK (0xff << 0)
|
||||
|
||||
/* SLG51000_SYSCTL_PATN_ID_B1 = 0x1106 */
|
||||
#define SLG51000_PART_NUMBER_BYTE0_SHIFT 0
|
||||
#define SLG51000_PART_NUMBER_BYTE0_MASK (0xff << 0)
|
||||
|
||||
/* SLG51000_SYSCTL_PATN_ID_B2 = 0x1107 */
|
||||
#define SLG51000_PART_NUMBER_BYTE1_SHIFT 0
|
||||
#define SLG51000_PART_NUMBER_BYTE1_MASK (0xff << 0)
|
||||
|
||||
/* SLG51000_SYSCTL_SYS_CONF_A = 0x1109 */
|
||||
#define SLG51000_I2C_ADDRESS_SHIFT 0
|
||||
#define SLG51000_I2C_ADDRESS_MASK (0x7f << 0)
|
||||
#define SLG51000_I2C_DISABLE_SHIFT 7
|
||||
#define SLG51000_I2C_DISABLE_MASK (0x01 << 7)
|
||||
|
||||
/* SLG51000_SYSCTL_SYS_CONF_D = 0x110c */
|
||||
#define SLG51000_CS_T_DEB_SHIFT 6
|
||||
#define SLG51000_CS_T_DEB_MASK (0x03 << 6)
|
||||
#define SLG51000_I2C_CLR_MODE_SHIFT 5
|
||||
#define SLG51000_I2C_CLR_MODE_MASK (0x01 << 5)
|
||||
|
||||
/* SLG51000_SYSCTL_MATRIX_CONF_A = 0x110d */
|
||||
#define SLG51000_RESOURCE_CTRL_SHIFT 0
|
||||
#define SLG51000_RESOURCE_CTRL_MASK (0xff << 0)
|
||||
|
||||
/* SLG51000_SYSCTL_MATRIX_CONF_B = 0x110e */
|
||||
#define SLG51000_MATRIX_EVENT_SENSE_SHIFT 0
|
||||
#define SLG51000_MATRIX_EVENT_SENSE_MASK (0x07 << 0)
|
||||
|
||||
/* SLG51000_SYSCTL_REFGEN_CONF_C = 0x1111 */
|
||||
#define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_SHIFT 2
|
||||
#define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_MASK (0x03 << 2)
|
||||
#define SLG51000_REFGEN_SEL_TEMP_WARN_THR_SHIFT 0
|
||||
#define SLG51000_REFGEN_SEL_TEMP_WARN_THR_MASK (0x03 << 0)
|
||||
|
||||
/* SLG51000_SYSCTL_UVLO_CONF_A = 0x1112 */
|
||||
#define SLG51000_VMON_UVLO_SEL_THR_SHIFT 0
|
||||
#define SLG51000_VMON_UVLO_SEL_THR_MASK (0x1f << 0)
|
||||
|
||||
/* SLG51000_SYSCTL_FAULT_LOG1 = 0x1115 */
|
||||
#define SLG51000_FLT_POR_SHIFT 5
|
||||
#define SLG51000_FLT_POR_MASK (0x01 << 5)
|
||||
#define SLG51000_FLT_RST_SHIFT 4
|
||||
#define SLG51000_FLT_RST_MASK (0x01 << 4)
|
||||
#define SLG51000_FLT_POWER_SEQ_CRASH_REQ_SHIFT 2
|
||||
#define SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK (0x01 << 2)
|
||||
#define SLG51000_FLT_OVER_TEMP_SHIFT 1
|
||||
#define SLG51000_FLT_OVER_TEMP_MASK (0x01 << 1)
|
||||
|
||||
/* SLG51000_SYSCTL_EVENT = 0x1116 */
|
||||
#define SLG51000_EVT_MATRIX_SHIFT 1
|
||||
#define SLG51000_EVT_MATRIX_MASK (0x01 << 1)
|
||||
#define SLG51000_EVT_HIGH_TEMP_WARN_SHIFT 0
|
||||
#define SLG51000_EVT_HIGH_TEMP_WARN_MASK (0x01 << 0)
|
||||
|
||||
/* SLG51000_SYSCTL_STATUS = 0x1117 */
|
||||
#define SLG51000_STA_MATRIX_SHIFT 1
|
||||
#define SLG51000_STA_MATRIX_MASK (0x01 << 1)
|
||||
#define SLG51000_STA_HIGH_TEMP_WARN_SHIFT 0
|
||||
#define SLG51000_STA_HIGH_TEMP_WARN_MASK (0x01 << 0)
|
||||
|
||||
/* SLG51000_SYSCTL_IRQ_MASK = 0x1118 */
|
||||
#define SLG51000_IRQ_MATRIX_SHIFT 1
|
||||
#define SLG51000_IRQ_MATRIX_MASK (0x01 << 1)
|
||||
#define SLG51000_IRQ_HIGH_TEMP_WARN_SHIFT 0
|
||||
#define SLG51000_IRQ_HIGH_TEMP_WARN_MASK (0x01 << 0)
|
||||
|
||||
/* SLG51000_IO_GPIO1_CONF ~ SLG51000_IO_GPIO5_CONF =
|
||||
* 0x1500, 0x1501, 0x1502, 0x1503, 0x1504
|
||||
*/
|
||||
#define SLG51000_GPIO_DIR_SHIFT 7
|
||||
#define SLG51000_GPIO_DIR_MASK (0x01 << 7)
|
||||
#define SLG51000_GPIO_SENS_SHIFT 5
|
||||
#define SLG51000_GPIO_SENS_MASK (0x03 << 5)
|
||||
#define SLG51000_GPIO_INVERT_SHIFT 4
|
||||
#define SLG51000_GPIO_INVERT_MASK (0x01 << 4)
|
||||
#define SLG51000_GPIO_BYP_SHIFT 3
|
||||
#define SLG51000_GPIO_BYP_MASK (0x01 << 3)
|
||||
#define SLG51000_GPIO_T_DEB_SHIFT 1
|
||||
#define SLG51000_GPIO_T_DEB_MASK (0x03 << 1)
|
||||
#define SLG51000_GPIO_LEVEL_SHIFT 0
|
||||
#define SLG51000_GPIO_LEVEL_MASK (0x01 << 0)
|
||||
|
||||
/* SLG51000_IO_GPIO6_CONF = 0x1505 */
|
||||
#define SLG51000_GPIO6_SENS_SHIFT 5
|
||||
#define SLG51000_GPIO6_SENS_MASK (0x03 << 5)
|
||||
#define SLG51000_GPIO6_INVERT_SHIFT 4
|
||||
#define SLG51000_GPIO6_INVERT_MASK (0x01 << 4)
|
||||
#define SLG51000_GPIO6_T_DEB_SHIFT 1
|
||||
#define SLG51000_GPIO6_T_DEB_MASK (0x03 << 1)
|
||||
#define SLG51000_GPIO6_LEVEL_SHIFT 0
|
||||
#define SLG51000_GPIO6_LEVEL_MASK (0x01 << 0)
|
||||
|
||||
/* SLG51000_IO_GPIO_STATUS = 0x1506 */
|
||||
#define SLG51000_GPIO6_STATUS_SHIFT 5
|
||||
#define SLG51000_GPIO6_STATUS_MASK (0x01 << 5)
|
||||
#define SLG51000_GPIO5_STATUS_SHIFT 4
|
||||
#define SLG51000_GPIO5_STATUS_MASK (0x01 << 4)
|
||||
#define SLG51000_GPIO4_STATUS_SHIFT 3
|
||||
#define SLG51000_GPIO4_STATUS_MASK (0x01 << 3)
|
||||
#define SLG51000_GPIO3_STATUS_SHIFT 2
|
||||
#define SLG51000_GPIO3_STATUS_MASK (0x01 << 2)
|
||||
#define SLG51000_GPIO2_STATUS_SHIFT 1
|
||||
#define SLG51000_GPIO2_STATUS_MASK (0x01 << 1)
|
||||
#define SLG51000_GPIO1_STATUS_SHIFT 0
|
||||
#define SLG51000_GPIO1_STATUS_MASK (0x01 << 0)
|
||||
|
||||
/* SLG51000_LUTARRAY_LUT_VAL_0 ~ SLG51000_LUTARRAY_LUT_VAL_11
|
||||
* 0x1600, 0x1601, 0x1602, 0x1603, 0x1604, 0x1605,
|
||||
* 0x1606, 0x1607, 0x1608, 0x1609, 0x160a, 0x160b
|
||||
*/
|
||||
#define SLG51000_LUT_VAL_SHIFT 0
|
||||
#define SLG51000_LUT_VAL_MASK (0xff << 0)
|
||||
|
||||
/* SLG51000_MUXARRAY_INPUT_SEL_0 ~ SLG51000_MUXARRAY_INPUT_SEL_63
|
||||
* 0x1700, 0x1701, 0x1702, 0x1703, 0x1704, 0x1705,
|
||||
* 0x1706, 0x1707, 0x1708, 0x1709, 0x170a, 0x170b,
|
||||
* 0x170c, 0x170d, 0x170e, 0x170f, 0x1710, 0x1711,
|
||||
* 0x1712, 0x1713, 0x1714, 0x1715, 0x1716, 0x1717,
|
||||
* 0x1718, 0x1719, 0x171a, 0x171b, 0x171c, 0x171d,
|
||||
* 0x171e, 0x171f, 0x1720, 0x1721, 0x1722, 0x1723,
|
||||
* 0x1724, 0x1725, 0x1726, 0x1727, 0x1728, 0x1729,
|
||||
* 0x173a, 0x173b, 0x173c, 0x173d, 0x173e, 0x173f,
|
||||
*/
|
||||
#define SLG51000_INPUT_SEL_SHIFT 0
|
||||
#define SLG51000_INPUT_SEL_MASK (0x3f << 0)
|
||||
|
||||
/* SLG51000_PWRSEQ_RESOURCE_EN_0 ~ SLG51000_PWRSEQ_RESOURCE_EN_5
|
||||
* 0x1900, 0x1901, 0x1902, 0x1903, 0x1904, 0x1905
|
||||
*/
|
||||
#define SLG51000_RESOURCE_EN_DOWN0_SHIFT 4
|
||||
#define SLG51000_RESOURCE_EN_DOWN0_MASK (0x07 << 4)
|
||||
#define SLG51000_RESOURCE_EN_UP0_SHIFT 0
|
||||
#define SLG51000_RESOURCE_EN_UP0_MASK (0x07 << 0)
|
||||
|
||||
/* SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5
|
||||
* 0x1906, 0x1908, 0x190a, 0x190c, 0x190e, 0x1910
|
||||
*/
|
||||
#define SLG51000_SLOT_TIME_MIN_UP_SHIFT 0
|
||||
#define SLG51000_SLOT_TIME_MIN_UP_MASK (0xff << 0)
|
||||
|
||||
/* SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5
|
||||
* 0x1907, 0x1909, 0x190b, 0x190d, 0x190f, 0x1911
|
||||
*/
|
||||
#define SLG51000_SLOT_TIME_MIN_DOWN_SHIFT 0
|
||||
#define SLG51000_SLOT_TIME_MIN_DOWN_MASK (0xff << 0)
|
||||
|
||||
/* SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A ~ SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C
|
||||
* 0x1912, 0x1913, 0x1914
|
||||
*/
|
||||
#define SLG51000_SLOT_TIME_MAX_DOWN1_SHIFT 6
|
||||
#define SLG51000_SLOT_TIME_MAX_DOWN1_MASK (0x03 << 6)
|
||||
#define SLG51000_SLOT_TIME_MAX_UP1_SHIFT 4
|
||||
#define SLG51000_SLOT_TIME_MAX_UP1_MASK (0x03 << 4)
|
||||
#define SLG51000_SLOT_TIME_MAX_DOWN0_SHIFT 2
|
||||
#define SLG51000_SLOT_TIME_MAX_DOWN0_MASK (0x03 << 2)
|
||||
#define SLG51000_SLOT_TIME_MAX_UP0_SHIFT 0
|
||||
#define SLG51000_SLOT_TIME_MAX_UP0_MASK (0x03 << 0)
|
||||
|
||||
/* SLG51000_PWRSEQ_INPUT_SENSE_CONF_A = 0x1915 */
|
||||
#define SLG51000_TRIG_UP_SENSE_SHIFT 6
|
||||
#define SLG51000_TRIG_UP_SENSE_MASK (0x01 << 6)
|
||||
#define SLG51000_UP_EN_SENSE5_SHIFT 5
|
||||
#define SLG51000_UP_EN_SENSE5_MASK (0x01 << 5)
|
||||
#define SLG51000_UP_EN_SENSE4_SHIFT 4
|
||||
#define SLG51000_UP_EN_SENSE4_MASK (0x01 << 4)
|
||||
#define SLG51000_UP_EN_SENSE3_SHIFT 3
|
||||
#define SLG51000_UP_EN_SENSE3_MASK (0x01 << 3)
|
||||
#define SLG51000_UP_EN_SENSE2_SHIFT 2
|
||||
#define SLG51000_UP_EN_SENSE2_MASK (0x01 << 2)
|
||||
#define SLG51000_UP_EN_SENSE1_SHIFT 1
|
||||
#define SLG51000_UP_EN_SENSE1_MASK (0x01 << 1)
|
||||
#define SLG51000_UP_EN_SENSE0_SHIFT 0
|
||||
#define SLG51000_UP_EN_SENSE0_MASK (0x01 << 0)
|
||||
|
||||
/* SLG51000_PWRSEQ_INPUT_SENSE_CONF_B = 0x1916 */
|
||||
#define SLG51000_CRASH_DETECT_SENSE_SHIFT 7
|
||||
#define SLG51000_CRASH_DETECT_SENSE_MASK (0x01 << 7)
|
||||
#define SLG51000_TRIG_DOWN_SENSE_SHIFT 6
|
||||
#define SLG51000_TRIG_DOWN_SENSE_MASK (0x01 << 6)
|
||||
#define SLG51000_DOWN_EN_SENSE5_SHIFT 5
|
||||
#define SLG51000_DOWN_EN_SENSE5_MASK (0x01 << 5)
|
||||
#define SLG51000_DOWN_EN_SENSE4_SHIFT 4
|
||||
#define SLG51000_DOWN_EN_SENSE4_MASK (0x01 << 4)
|
||||
#define SLG51000_DOWN_EN_SENSE3_SHIFT 3
|
||||
#define SLG51000_DOWN_EN_SENSE3_MASK (0x01 << 3)
|
||||
#define SLG51000_DOWN_EN_SENSE2_SHIFT 2
|
||||
#define SLG51000_DOWN_EN_SENSE2_MASK (0x01 << 2)
|
||||
#define SLG51000_DOWN_EN_SENSE1_SHIFT 1
|
||||
#define SLG51000_DOWN_EN_SENSE1_MASK (0x01 << 1)
|
||||
#define SLG51000_DOWN_EN_SENSE0_SHIFT 0
|
||||
#define SLG51000_DOWN_EN_SENSE0_MASK (0x01 << 0)
|
||||
|
||||
/* SLG51000_LDO1_VSEL ~ SLG51000_LDO7_VSEL =
|
||||
* 0x2000, 0x2200, 0x2300, 0x2500, 0x2700, 0x2900, 0x3100
|
||||
*/
|
||||
#define SLG51000_VSEL_SHIFT 0
|
||||
#define SLG51000_VSEL_MASK (0xff << 0)
|
||||
|
||||
/* SLG51000_LDO1_VSEL_RANGE_MASK_MIN ~ SLG51000_LDO7_VSEL_RANGE_MASK_MIN =
|
||||
* 0x2060, 0x2260, 0x2360, 0x2560, 0x2760, 0x2960, 0x3160
|
||||
*/
|
||||
#define SLG51000_VSEL_RANGE_MASK_MIN_SHIFT 0
|
||||
#define SLG51000_VSEL_RANGE_MASK_MIN_MASK (0xff << 0)
|
||||
|
||||
/* SLG51000_LDO1_VSEL_RANGE_MASK_MAX ~ SLG51000_LDO7_VSEL_RANGE_MASK_MAX =
|
||||
* 0x2061, 0x2261, 0x2361, 0x2561, 0x2761, 0x2961, 0x3161
|
||||
*/
|
||||
#define SLG51000_VSEL_RANGE_MASK_MAX_SHIFT 0
|
||||
#define SLG51000_VSEL_RANGE_MASK_MAX_MASK (0xff << 0)
|
||||
|
||||
/* SLG51000_LDO1_VSEL_ACTUAL ~ SLG51000_LDO7_VSEL_ACTUAL =
|
||||
* 0x2065, 0x2265, 0x2366, 0x2566, 0x2767, 0x2967, 0x3166
|
||||
*/
|
||||
#define SLG51000_VSEL_ACTUAL_SHIFT 0
|
||||
#define SLG51000_VSEL_ACTUAL_MASK (0xff << 0)
|
||||
|
||||
/* SLG51000_LDO1_EVENT ~ SLG51000_LDO7_EVENT =
|
||||
* 0x20c0, 0x22c0, 0x23c0, 0x25c0, 0x27c0, 0x29c0, 0x31c0
|
||||
*/
|
||||
#define SLG51000_EVT_ILIM_FLAG_SHIFT 0
|
||||
#define SLG51000_EVT_ILIM_FLAG_MASK (0x01 << 0)
|
||||
#define SLG51000_EVT_VOUT_OK_FLAG_SHIFT 1
|
||||
#define SLG51000_EVT_VOUT_OK_FLAG_MASK (0x01 << 1)
|
||||
|
||||
/* SLG51000_LDO1_STATUS ~ SLG51000_LDO7_STATUS =
|
||||
* 0x20c1, 0x22c1, 0x23c1, 0x25c1, 0x27c1, 0x29c1, 0x31c1
|
||||
*/
|
||||
#define SLG51000_STA_ILIM_FLAG_SHIFT 0
|
||||
#define SLG51000_STA_ILIM_FLAG_MASK (0x01 << 0)
|
||||
#define SLG51000_STA_VOUT_OK_FLAG_SHIFT 1
|
||||
#define SLG51000_STA_VOUT_OK_FLAG_MASK (0x01 << 1)
|
||||
|
||||
/* SLG51000_LDO1_IRQ_MASK ~ SLG51000_LDO7_IRQ_MASK =
|
||||
* 0x20c2, 0x22c2, 0x23c2, 0x25c2, 0x27c2, 0x29c2, 0x31c2
|
||||
*/
|
||||
#define SLG51000_IRQ_ILIM_FLAG_SHIFT 0
|
||||
#define SLG51000_IRQ_ILIM_FLAG_MASK (0x01 << 0)
|
||||
|
||||
/* SLG51000_LDO3_CONF1 ~ SLG51000_LDO7_CONF1 =
|
||||
* 0x2364, 0x2564, 0x2765, 0x2965, 0x3164
|
||||
*/
|
||||
#define SLG51000_SEL_START_ILIM_SHIFT 0
|
||||
#define SLG51000_SEL_START_ILIM_MASK (0x7f << 0)
|
||||
|
||||
/* SLG51000_LDO3_CONF2 ~ SLG51000_LDO7_CONF2 =
|
||||
* 0x2365, 0x2565, 0x2766, 0x2966, 0x3165
|
||||
*/
|
||||
#define SLG51000_SEL_FUNC_ILIM_SHIFT 0
|
||||
#define SLG51000_SEL_FUNC_ILIM_MASK (0x7f << 0)
|
||||
|
||||
/* SLG51000_LDO5_TRIM2 = 0x2763, SLG51000_LDO6_TRIM2 = 0x2963 */
|
||||
#define SLG51000_SEL_BYP_SLEW_RATE_SHIFT 2
|
||||
#define SLG51000_SEL_BYP_SLEW_RATE_MASK (0x03 << 2)
|
||||
#define SLG51000_SEL_BYP_VGATE_SHIFT 1
|
||||
#define SLG51000_SEL_BYP_VGATE_MASK (0x01 << 1)
|
||||
#define SLG51000_SEL_BYP_MODE_SHIFT 0
|
||||
#define SLG51000_SEL_BYP_MODE_MASK (0x01 << 0)
|
||||
|
||||
/* SLG51000_LDO1_TRIM2 = 0x2063, SLG51000_LDO2_TRIM2 = 0x2263,
|
||||
* SLG51000_LDO3_TRIM2 = 0x2363, SLG51000_LDO4_TRIM2 = 0x2563,
|
||||
* SLG51000_LDO5_TRIM3 = 0x2764, SLG51000_LDO6_TRIM3 = 0x2964,
|
||||
* SLG51000_LDO7_TRIM2 = 0x3163
|
||||
*/
|
||||
#define SLG51000_ILIM_FLAG_DEB_SHIFT 3
|
||||
#define SLG51000_ILIM_FLAG_DEB_MASK (0x03 << 3)
|
||||
#define SLG51000_VOUT_OK_DEB_SHIFT 1
|
||||
#define SLG51000_VOUT_OK_DEB_MASK (0x03 << 1)
|
||||
|
||||
/* SLG51000_LOCK_GLOBAL_LOCK_CTRL1 = 0x8000 */
|
||||
#define SLG51000_LDO7_LOCK_SHIFT 7
|
||||
#define SLG51000_LDO7_LOCK_MASK (0x01 << 7)
|
||||
#define SLG51000_LDO6_LOCK_SHIFT 6
|
||||
#define SLG51000_LDO6_LOCK_MASK (0x01 << 6)
|
||||
#define SLG51000_LDO5_LOCK_SHIFT 5
|
||||
#define SLG51000_LDO5_LOCK_MASK (0x01 << 5)
|
||||
#define SLG51000_LDO4_LOCK_SHIFT 4
|
||||
#define SLG51000_LDO4_LOCK_MASK (0x01 << 4)
|
||||
#define SLG51000_LDO3_LOCK_SHIFT 3
|
||||
#define SLG51000_LDO3_LOCK_MASK (0x01 << 3)
|
||||
#define SLG51000_LDO2_LOCK_SHIFT 2
|
||||
#define SLG51000_LDO2_LOCK_MASK (0x01 << 2)
|
||||
#define SLG51000_LDO1_LOCK_SHIFT 1
|
||||
#define SLG51000_LDO1_LOCK_MASK (0x01 << 1)
|
||||
|
||||
#endif /* __SLG51000_REGISTERS_H__ */
|
||||
Loading…
Reference in a new issue