From ad5cf39cb5645aec40b998c111def35f89fa4565 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Tue, 12 Nov 2019 12:35:36 -0800 Subject: [PATCH] ARM: dts: msm: Add USB PHY devices and related resources on Lahaina This change adds USB PHYs device node and related required resources for USB ports on Lahaina. Change-Id: I20a838fe555c776d4a5336ac9bef9cd15ac5f11d --- qcom/lahaina-rumi.dtsi | 12 +++ qcom/lahaina-usb.dtsi | 234 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 245 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-rumi.dtsi b/qcom/lahaina-rumi.dtsi index 8b7bca6dc028..f918f4c65b03 100644 --- a/qcom/lahaina-rumi.dtsi +++ b/qcom/lahaina-rumi.dtsi @@ -66,6 +66,18 @@ }; }; +&usb2_phy0 { + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + &usb0 { /delete-property/ extcon; dwc3@a600000 { diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index 1d39f56e176c..ad2778f3400b 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -1,3 +1,6 @@ +#include +#include + &soc { usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; @@ -48,6 +51,7 @@ compatible = "snps,dwc3"; reg = <0xa600000 0xcd00>; interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; @@ -92,6 +96,214 @@ }; }; + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x114>, + <0x088e2000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&pm8350_l5>; + vdda18-supply = <&pm8350c_l1>; + vdda33-supply = <&pm8350_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* Primary USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&pm8350_l1>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8350_l6>; + + clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&clock_gcc USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "com_aux_clk"; + + resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&clock_gcc GCC_USB3PHY_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; + usb1: ssusb@a800000 { compatible = "qcom,dwc-usb3-msm"; reg = <0xa800000 0x100000>; @@ -142,6 +354,7 @@ compatible = "snps,dwc3"; reg = <0xa800000 0xcd00>; interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_nop_phy>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; @@ -152,11 +365,30 @@ snps,dis_enblslpm_quirk; usb-core-id = <1>; tx-fifo-resize; - maximum-speed = "super-speed-plus"; + maximum-speed = "high-speed"; dr_mode = "drd"; }; }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e4000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e4000 0x114>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&pm8350_l5>; + vdda18-supply = <&pm8350c_l1>; + vdda33-supply = <&pm8350_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&clock_gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy_reset"; + }; + usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; };