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Merge "ARM: dts: msm: Add HWSPINLOCK, SMEM and SMP2P for Lahaina"

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qctecmdr 2019-08-13 15:21:24 -07:00 • committed by Gerrit - the friendly Code Review server
commit adced57543
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25
bindings/net/qrtr-fifo-xprt.txt Normal file
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Qualcomm Technologies, Inc. IPC Router FIFO Transport
Required properties:
- compatible: should be "qcom,ipcr-fifo-xprt"
- reg: the irq register to raise an interrupt
- interrupts: the receiving interrupt line
- qcom,ipc-shm: reference to shared memory phandle
Example:
fifo_vipc_irq@176 {
compatible = "qcom,ipcr-fifo-xprt";
reg = <0x176>;
interrupts = <0x0 0x142 0x1>;
qcom,ipc-shm = <&ipc-shm>;
};
ipc-shm: shared-buffer@85af7000 {
compatible = "qcom,hypervisor-shared-memory";
phandle = <0x1e4>;
reg = <0x0 0x85af7000 0x0 0x9000>;
label = "ipc_shm";
qcom,tx-is-first;
};

82
qcom/lahaina-smp2p.dtsi Normal file
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#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
&soc {
qcom,smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-dsps {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
dsps_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
dsps_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
sleepstate_smp2p_out: sleepstate-out {
qcom,entry-name = "sleepstate";
#qcom,smem-state-cells = <1>;
};
sleepstate_smp2p_in: qcom,sleepstate-in {
qcom,entry-name = "sleepstate_see";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-nsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

18
qcom/lahaina.dtsi
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@ -667,8 +667,26 @@
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
};
tcsr_mutex_block: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x1000>;
#hwlock-cells = <1>;
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
};
#include "lahaina-pinctrl.dtsi"
#include "lahaina-smp2p.dtsi"
#include "msm-arm-smmu-lahaina.dtsi"
#include "lahaina-usb.dtsi"