mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 21:54:34 -04:00
Merge branch 'for-linus' of git://git.o-hand.com/linux-mfd
* 'for-linus' of git://git.o-hand.com/linux-mfd: mfd: let asic3 use mem resource instead of bus_shift mfd: remove DS1WM register definitions from asic3.h mfd: add ASIC3_CONFIG_GPIO templates mfd: fix the asic3 irq demux code mfd: asic3 should depend on gpiolib mfd: fix asic3 config array initialisation mfd: move asic3 probe functions into __init section mfd: Use uppercase only for asic3 macros and defines mfd: use dev_* macros for asic3 debugging mfd: New asic3 gpio configuration code mfd: asic3 children platform data removal mfd: asic3 gpiolib support
This commit is contained in:
Linus Torvalds
commit
ae0645a451
3 changed files with 319 additions and 256 deletions
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@ -8,7 +8,7 @@
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* published by the Free Software Foundation.
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*
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* Copyright 2001 Compaq Computer Corporation.
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* Copyright 2007 OpendHand.
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* Copyright 2007-2008 OpenedHand Ltd.
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*/
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#ifndef __ASIC3_H__
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@ -16,43 +16,22 @@
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#include <linux/types.h>
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struct asic3 {
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void __iomem *mapping;
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unsigned int bus_shift;
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unsigned int irq_nr;
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unsigned int irq_base;
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spinlock_t lock;
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u16 irq_bothedge[4];
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struct device *dev;
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};
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struct asic3_platform_data {
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struct {
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u32 dir;
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u32 init;
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u32 sleep_mask;
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u32 sleep_out;
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u32 batt_fault_out;
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u32 sleep_conf;
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u32 alt_function;
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} gpio_a, gpio_b, gpio_c, gpio_d;
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unsigned int bus_shift;
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u16 *gpio_config;
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unsigned int gpio_config_num;
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unsigned int irq_base;
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struct platform_device **children;
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unsigned int n_children;
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unsigned int gpio_base;
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};
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int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio);
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void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
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#define ASIC3_NUM_GPIO_BANKS 4
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#define ASIC3_GPIOS_PER_BANK 16
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#define ASIC3_NUM_GPIOS 64
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#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
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#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
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#define ASIC3_GPIO_BANK_A 0
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#define ASIC3_GPIO_BANK_B 1
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#define ASIC3_GPIO_BANK_C 2
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@ -64,32 +43,89 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
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/* All offsets below are specified with this address bus shift */
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#define ASIC3_DEFAULT_ADDR_SHIFT 2
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#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg)
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#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
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#define ASIC3_GPIO_OFFSET(base, reg) \
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(ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg)
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(ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
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#define ASIC3_GPIO_A_Base 0x0000
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#define ASIC3_GPIO_B_Base 0x0100
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#define ASIC3_GPIO_C_Base 0x0200
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#define ASIC3_GPIO_D_Base 0x0300
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#define ASIC3_GPIO_A_BASE 0x0000
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#define ASIC3_GPIO_B_BASE 0x0100
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#define ASIC3_GPIO_C_BASE 0x0200
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#define ASIC3_GPIO_D_BASE 0x0300
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#define ASIC3_GPIO_Mask 0x00 /* R/W 0:don't mask */
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#define ASIC3_GPIO_Direction 0x04 /* R/W 0:input */
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#define ASIC3_GPIO_Out 0x08 /* R/W 0:output low */
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#define ASIC3_GPIO_TriggerType 0x0c /* R/W 0:level */
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#define ASIC3_GPIO_EdgeTrigger 0x10 /* R/W 0:falling */
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#define ASIC3_GPIO_LevelTrigger 0x14 /* R/W 0:low level detect */
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#define ASIC3_GPIO_SleepMask 0x18 /* R/W 0:don't mask in sleep mode */
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#define ASIC3_GPIO_SleepOut 0x1c /* R/W level 0:low in sleep mode */
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#define ASIC3_GPIO_BattFaultOut 0x20 /* R/W level 0:low in batt_fault */
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#define ASIC3_GPIO_IntStatus 0x24 /* R/W 0:none, 1:detect */
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#define ASIC3_GPIO_AltFunction 0x28 /* R/W 1:LED register control */
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#define ASIC3_GPIO_SleepConf 0x2c /*
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#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
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#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
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(ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
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#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
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#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
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#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
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#define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */
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#define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */
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#define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */
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#define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */
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#define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */
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#define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */
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#define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */
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#define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */
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#define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */
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#define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */
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#define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */
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#define ASIC3_GPIO_SLEEP_CONF 0x2c /*
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* R/W bit 1: autosleep
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* 0: disable gposlpout in normal mode,
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* enable gposlpout in sleep mode.
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*/
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#define ASIC3_GPIO_Status 0x30 /* R Pin status */
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#define ASIC3_GPIO_STATUS 0x30 /* R Pin status */
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/*
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* ASIC3 GPIO config
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*
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* Bits 0..6 gpio number
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* Bits 7..13 Alternate function
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* Bit 14 Direction
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* Bit 15 Initial value
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*
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*/
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#define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
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#define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7)
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#define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14)
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#define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
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#define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
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| (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
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| (((init) & 0x1) << 15))
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#define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
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ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
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#define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
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ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
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/*
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* Alternate functions
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*/
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#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0)
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#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0)
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#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0)
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#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 1, 0)
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#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 1, 0)
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#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 1, 0)
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#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0)
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#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0)
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#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0)
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#define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0)
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#define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0)
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#define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0)
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#define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0)
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#define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0)
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#define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0)
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#define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0)
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#define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0)
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#define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0)
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#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0)
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#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0)
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#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0)
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#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0)
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#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0)
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#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0)
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#define ASIC3_SPI_Base 0x0400
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#define ASIC3_SPI_Control 0x0000
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@ -128,7 +164,7 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
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#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
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#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
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#define ASIC3_CLOCK_Base 0x0A00
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#define ASIC3_CLOCK_BASE 0x0A00
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#define ASIC3_CLOCK_CDEX 0x00
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#define ASIC3_CLOCK_SEL 0x04
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@ -159,12 +195,12 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
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#define CLOCK_SEL_CX (1 << 2)
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#define ASIC3_INTR_Base 0x0B00
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#define ASIC3_INTR_BASE 0x0B00
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#define ASIC3_INTR_IntMask 0x00 /* Interrupt mask control */
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#define ASIC3_INTR_PIntStat 0x04 /* Peripheral interrupt status */
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#define ASIC3_INTR_IntCPS 0x08 /* Interrupt timer clock pre-scale */
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#define ASIC3_INTR_IntTBS 0x0c /* Interrupt timer set */
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#define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */
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#define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */
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#define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */
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#define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */
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#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
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#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
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@ -227,44 +263,12 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
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#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
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/*********************************************
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* The Onewire interface registers
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*
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* OWM_CMD
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* OWM_DAT
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* OWM_INTR
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* OWM_INTEN
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* OWM_CLKDIV
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* The Onewire interface (DS1WM) is handled
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* by the ds1wm driver.
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*
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*********************************************/
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#define ASIC3_OWM_Base 0xC00
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#define ASIC3_OWM_CMD 0x00
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#define ASIC3_OWM_DAT 0x04
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#define ASIC3_OWM_INTR 0x08
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#define ASIC3_OWM_INTEN 0x0C
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#define ASIC3_OWM_CLKDIV 0x10
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#define ASIC3_OWM_CMD_ONEWR (1 << 0)
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#define ASIC3_OWM_CMD_SRA (1 << 1)
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#define ASIC3_OWM_CMD_DQO (1 << 2)
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#define ASIC3_OWM_CMD_DQI (1 << 3)
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#define ASIC3_OWM_INTR_PD (1 << 0)
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#define ASIC3_OWM_INTR_PDR (1 << 1)
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#define ASIC3_OWM_INTR_TBE (1 << 2)
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#define ASIC3_OWM_INTR_TEMP (1 << 3)
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#define ASIC3_OWM_INTR_RBF (1 << 4)
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#define ASIC3_OWM_INTEN_EPD (1 << 0)
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#define ASIC3_OWM_INTEN_IAS (1 << 1)
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#define ASIC3_OWM_INTEN_ETBE (1 << 2)
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#define ASIC3_OWM_INTEN_ETMT (1 << 3)
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#define ASIC3_OWM_INTEN_ERBF (1 << 4)
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#define ASIC3_OWM_CLKDIV_PRE (3 << 0) /* two bits wide at bit 0 */
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#define ASIC3_OWM_CLKDIV_DIV (7 << 2) /* 3 bits wide at bit 2 */
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#define ASIC3_OWM_BASE 0xC00
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/*****************************************************************************
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* The SD configuration registers are at a completely different location
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@ -492,6 +496,7 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
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#define ASIC3_SDIO_CTRL_LEDCtrl 0x7C
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#define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0
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#define ASIC3_MAP_SIZE 0x2000
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#define ASIC3_MAP_SIZE_32BIT 0x2000
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#define ASIC3_MAP_SIZE_16BIT 0x1000
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#endif /* __ASIC3_H__ */
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