From 77323830f17d07b27cca6c2e3631cbe7af522d09 Mon Sep 17 00:00:00 2001
From: Taniya Das <tdas@qti.qualcomm.com>
Date: Fri, 8 May 2020 13:09:54 +0530
Subject: [PATCH] ARM: dts: msm: Add support clock AOP for SHIMA

QDSS clocks uses the qmp mailbox phandle to register the clock.
Thus add the phandle and also update RUMI to use dummy clocks.

Change-Id: I9d3a913fbaf76ffe132b59403e50c05e9d797ef4
---
 qcom/shima-rumi.dtsi | 5 +++++
 qcom/shima.dtsi      | 6 +++---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/qcom/shima-rumi.dtsi b/qcom/shima-rumi.dtsi
index ac7084807882..da35118a0fde 100644
--- a/qcom/shima-rumi.dtsi
+++ b/qcom/shima-rumi.dtsi
@@ -102,3 +102,8 @@
 &gcc {
 	clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>;
 };
+
+&aopcc {
+	compatible = "qcom,dummycc";
+	clock-output-names = "qdss_clocks";
+};
diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 31850578f540..98a43d5a1e19 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -560,10 +560,10 @@
 	};
 
 	aopcc: qcom,aopcc {
-		compatible = "qcom,dummycc";
-		clock-output-names = "aopcc_clocks";
+		compatible = "qcom,aop-qmp-clk";
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "qdss_clk";
 		#clock-cells = <1>;
-		#reset-cells = <1>;
 	};
 
 	gcc: clock-controller@100000 {