From ca84a522e6e8e2529696337b509b39f639a99555 Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Wed, 23 Jun 2021 20:01:13 +0530 Subject: [PATCH] ARM: dts: msm: Correct csid clock rate in Blair Camera This change is to correct csid clock rate in Blair camera. CRs-Fixed: 2944976 Change-Id: Ifb7dc37eac2df5530a9a7c7fec6dc6f69e067b97 --- blair-camera.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/blair-camera.dtsi b/blair-camera.dtsi index 5fced0e6fc48..f2537858db28 100644 --- a/blair-camera.dtsi +++ b/blair-camera.dtsi @@ -724,7 +724,7 @@ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = - <266570000 0 0 0 300000000 0>, + <266571429 0 0 0 300000000 0>, <426400000 0 0 0 460800000 0>, <466500000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; @@ -788,7 +788,7 @@ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = - <266570000 0 0 0 300000000 0>, + <266571429 0 0 0 300000000 0>, <426400000 0 0 0 460800000 0>, <466500000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; @@ -852,7 +852,7 @@ <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, <&gcc GCC_CAMSS_TFE_2_CLK>; clock-rates = - <266570000 0 0 0 300000000 0>, + <266571429 0 0 0 300000000 0>, <426400000 0 0 0 460800000 0>, <466500000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo";