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clk/samsung updates for v4.15, part 2

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- An addition of separate driver for the Exynos 4412 ISP CMU, needed
    to model and properly handle the clock controller's dependencies
    on the ISP power domain.
  - Adding __maybe_unused attributes to the exynos5433_cmu_{suspend,
    resume} ops to suppress compiler warnings with CONFIG_PM disabled.
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Merge tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next

Pull Samsung clk driver updates from Sylwester Nawrocki:

 - An addition of separate driver for the Exynos 4412 ISP CMU, needed
   to model and properly handle the clock controller's dependencies
   on the ISP power domain.
 - Adding __maybe_unused attributes to the exynos5433_cmu_{suspend,
   resume} ops to suppress compiler warnings with CONFIG_PM disabled.

* tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: Add a separate driver for Exynos4412 ISP clocks
  clk: samsung: Add dt bindings for Exynos4412 ISP clock controller
  clk: samsung: Instantiate Exynos4412 ISP clocks only when available
  clk: samsung: exynos5433: mark PM functions as __maybe_unused
This commit is contained in:
Stephen Boyd 2017-10-30 17:59:10 -07:00
commit ae74ac0828
6 changed files with 284 additions and 9 deletions
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35
include/dt-bindings/clock/exynos4.h
View file

@ -272,4 +272,39 @@
/* must be greater than maximal clock id */
#define CLK_NR_CLKS 461
/* Exynos4x12 ISP clocks */
#define CLK_ISP_FIMC_ISP 1
#define CLK_ISP_FIMC_DRC 2
#define CLK_ISP_FIMC_FD 3
#define CLK_ISP_FIMC_LITE0 4
#define CLK_ISP_FIMC_LITE1 5
#define CLK_ISP_MCUISP 6
#define CLK_ISP_GICISP 7
#define CLK_ISP_SMMU_ISP 8
#define CLK_ISP_SMMU_DRC 9
#define CLK_ISP_SMMU_FD 10
#define CLK_ISP_SMMU_LITE0 11
#define CLK_ISP_SMMU_LITE1 12
#define CLK_ISP_PPMUISPMX 13
#define CLK_ISP_PPMUISPX 14
#define CLK_ISP_MCUCTL_ISP 15
#define CLK_ISP_MPWM_ISP 16
#define CLK_ISP_I2C0_ISP 17
#define CLK_ISP_I2C1_ISP 18
#define CLK_ISP_MTCADC_ISP 19
#define CLK_ISP_PWM_ISP 20
#define CLK_ISP_WDT_ISP 21
#define CLK_ISP_UART_ISP 22
#define CLK_ISP_ASYNCAXIM 23
#define CLK_ISP_SMMU_ISPCX 24
#define CLK_ISP_SPI0_ISP 25
#define CLK_ISP_SPI1_ISP 26
#define CLK_ISP_DIV_ISP0 27
#define CLK_ISP_DIV_ISP1 28
#define CLK_ISP_DIV_MCUISP0 29
#define CLK_ISP_DIV_MCUISP1 30
#define CLK_NR_ISP_CLKS 31
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */