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clk: qcom: gcc-blair: Add support for AHB clocks

Browse source 
Add support for Camera, Display, GPU and Video
AHB clocks.

Change-Id: I1c60f2f720b57659ab92e770448c1ce1c27a359e
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
This commit is contained in:
Jagadeesh Kona 2021-05-10 14:09:41 +05:30
commit ae78a04c5f
1 changed files with 69 additions and 7 deletions
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76
drivers/clk/qcom/gcc-blair.c
View file

@ -2293,6 +2293,22 @@ static struct clk_branch gcc_cam_throttle_rt_clk = {
},
};
static struct clk_branch gcc_camera_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_axi_clk = {
.halt_reg = 0x58044,
.halt_check = BRANCH_HALT,
@ -2843,6 +2859,22 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
},
};
static struct clk_branch gcc_disp_ahb_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
.reg = 0x17058,
.shift = 0,
@ -2972,6 +3004,22 @@ static struct clk_branch gcc_gp3_clk = {
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
@ -3935,6 +3983,22 @@ static struct clk_branch gcc_venus_ctl_axi_clk = {
},
};
static struct clk_branch gcc_video_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x17004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x1701c,
.halt_check = BRANCH_HALT_VOTED,
@ -4023,6 +4087,7 @@ static struct clk_regmap *gcc_blair_clocks[] = {
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
[GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
[GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
[GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,
@ -4078,6 +4143,7 @@ static struct clk_regmap *gcc_blair_clocks[] = {
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
@ -4089,6 +4155,7 @@ static struct clk_regmap *gcc_blair_clocks[] = {
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
@ -4171,6 +4238,7 @@ static struct clk_regmap *gcc_blair_clocks[] = {
[GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
[GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,
[GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
[GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
@ -4270,17 +4338,11 @@ static int gcc_blair_probe(struct platform_device *pdev)
/*
* Keep the clocks always-ON
* GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK,
* GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK,
* GCC_VIDEO_AHB_CLK
* GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK
*/
regmap_update_bits(regmap, 0x17008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x1700c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x17004, BIT(0), BIT(0));
clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config);
clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config);