diff --git a/hw/qca8074/v1/HALhwio.h b/hw/qca8074/v1/HALhwio.h index 4e51df01439f..f5e6bab429f9 100644 --- a/hw/qca8074/v1/HALhwio.h +++ b/hw/qca8074/v1/HALhwio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -22,10 +22,10 @@ =========================================================================== */ /** - @file HALhwio.h - + @file HALhwio.h + Public interface include file for accessing the HWIO HAL definitions. - + The HALhwio.h file is the public API interface to the HW I/O (HWIO) register access definitions. */ @@ -46,10 +46,10 @@ ** Macros ** ----------------------------------------------------------------------- */ -/** +/** @addtogroup macros - @{ -*/ + @{ +*/ /** * Map a base name to the pointer to access the base. @@ -61,6 +61,8 @@ #define HWIO_BASE_PTR(base) base##_BASE_PTR + + /** * Declare a HWIO base pointer. * @@ -79,10 +81,10 @@ */ -/** +/** @addtogroup hwio_macros - @{ -*/ + @{ +*/ /** * @name Address Macros @@ -282,7 +284,7 @@ /** * @name Shadow Register Macros * - * These macros are used for directly reading the value stored in a + * These macros are used for directly reading the value stored in a * shadow register. * Shadow registers are defined for write-only registers. Generally these * macros should not be necessary as HWIO_OUTM* macros will automatically use @@ -294,7 +296,7 @@ #define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) /** @} */ -/** +/** @} */ /* end_group */ @@ -302,7 +304,7 @@ /** @cond */ /* - * Map to final symbols. This remapping is done to allow register + * Map to final symbols. This remapping is done to allow register * redefinitions. If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN * then remappings like "#define xreg xregnew" do not work as expected. */ @@ -330,7 +332,7 @@ #define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) #define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) #define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) -#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS #define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) #define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) #define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) @@ -364,13 +366,13 @@ HWIO_##hwiosym##_OUTM(base, mask1, val1); \ HWIO_##hwiosym##_OUTM(base, mask2, val2); \ HWIO_##hwiosym##_OUTM(base, mask3, val3); \ - } + } #define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ HWIO_##hwiosym##_OUTM(base, mask1, val1); \ HWIO_##hwiosym##_OUTM(base, mask2, val2); \ HWIO_##hwiosym##_OUTM(base, mask3, val3); \ HWIO_##hwiosym##_OUTM(base, mask4, val4); \ - } + } #define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) @@ -397,16 +399,82 @@ #define HWIO_INTFREE() +#if defined(VISUAL_STUDIO) || defined(TEST_FRAMEWORK) +extern unsigned int registerRead(unsigned int port); +extern void registerWrite(unsigned int port, unsigned int val); +#define __inp(port) registerRead(port) +#define __inpw(port) registerRead(port) +#define __inpdw(port) registerRead(port) +#define __outp(port, val) registerWrite(port, val) +#define __outpw(port, val) registerWrite(port, val) +#define __outpdw(port, val) registerWrite(port, val) + +#else +#if defined(CONFIG_SIMHW) +extern unsigned char * simhw_get_mac_addr(void); +extern uint8 __sim_inp(uint32 addr); +extern uint16 __sim_inpw(uint32 addr); +extern uint32 __sim_inpdw(uint32 addr); +extern void __sim_outp(uint32 addr, uint8 data); +extern void __sim_outpw(uint32 addr, uint16 data); +extern void __sim_outpdw(uint32 addr, uint32 data); + +#define __inp(port) __sim_inp((unsigned int)port) +#define __inpw(port) __sim_inpw((unsigned int)port) +#define __inpdw(port) __sim_inpdw((unsigned int)port) +#define __outp(port, val) __sim_outp((unsigned int)port, val) +#define __outpw(port, val) __sim_outpw((unsigned int)port, val) +#define __outpdw(port, val) __sim_outpdw((unsigned int)port, val) + +#define registerRead(port) __sim_inpdw(port) +#define registerWrite(port, val) __sim_outpdw(port, val) + +#else // CONFIG_SIMHW + +#ifdef FPGA +#define MAC_ADDRESS_POWER_CHECK +#else +#undef MAC_ADDRESS_POWER_CHECK +#endif +#ifdef MAC_ADDRESS_POWER_CHECK +extern void whal_pwr_debug_register_address_check(uint32 addr, int is_write); +#endif + + /* * Input/output port macros for memory mapped IO. */ -#define __inp(port) (*((volatile uint8 *) (port))) -#define __inpw(port) (*((volatile uint16 *) (port))) -#define __inpdw(port) (*((volatile uint32 *) (port))) -#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) -#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) -#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) +#define __inp(port) (*((volatile uint8 *) ((uint32)(port)))) +#define __inpw(port) (*((volatile uint16 *) ((uint32)(port)))) +#ifdef MAC_ADDRESS_POWER_CHECK +static inline uint32 __inpdw(uint32 port){ + whal_pwr_debug_register_address_check(port, FALSE); + return (*((volatile uint32 *) (port))); +} +#else +#define __inpdw(port) (*((volatile uint32 *) ((uint32)(port)))) +#endif +extern void busywait(uint32 pause_time_us); + +#define __outp(port, val) (*((volatile uint8 *) ((uint32)(port))) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) ((uint32)(port))) = ((uint16) (val))) +#ifdef MAC_ADDRESS_POWER_CHECK +static inline void __outpdw(uint32 port ,uint32 val){ + whal_pwr_debug_register_address_check(port, TRUE); + (*((volatile uint32 *) (port)) = ((uint32) (val))); +} +#else +static inline void __outpdw(uint32 port ,uint32 val){ + (*((volatile uint32 *) (port)) = ((uint32) (val))); + busywait(1); +} +#endif + +#define registerRead(port) (*((volatile uint32 *) ((uint32)(port) ))) +#define registerWrite(port, val) (*((volatile uint32 *) ((uint32)(port) )) = ((uint32) (val))) +#endif // CONFIG_SIMHW +#endif #ifdef HAL_HWIO_EXTERNAL @@ -420,7 +488,7 @@ #undef __outpw #undef __outpdw -#define __inp(port) __inp_extern(port) +#define __inp(port) __inp_extern(port) #define __inpw(port) __inpw_extern(port) #define __inpdw(port) __inpdw_extern(port) #define __outp(port, val) __outp_extern(port, val) @@ -441,7 +509,7 @@ extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); * Base 8-bit byte accessing macros. */ #define in_byte(addr) (__inp(addr)) -#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) #define out_byte(addr, val) __outp(addr,val) #define out_byte_masked(io, mask, val, shadow) \ HWIO_INTLOCK(); \ @@ -472,9 +540,15 @@ extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); /* * Base 32-bit double-word accessing macros. */ +#ifdef MAC_ADDRESS_POWER_CHECK +#define in_dword(addr) (__inpdw((uint32)addr)) +#define in_dword_masked(addr, mask) (__inpdw((uint32)addr) & (mask)) +#define out_dword(addr, val) __outpdw((uint32)addr,val) +#else #define in_dword(addr) (__inpdw(addr)) #define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) -#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword(addr, val) __outpdw((uint32)addr,val) +#endif #define out_dword_masked(io, mask, val, shadow) \ HWIO_INTLOCK(); \ shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ @@ -484,6 +558,9 @@ extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ ((uint32)((val) & (mask)))) ) +#define out_dword_masked_ns_shift(io, mask, val, current_reg_content, shift) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + (((uint32)((val) & (mask))) << shift )) ) /** @endcond */ #endif /* HAL_HWIO_H */ diff --git a/hw/qca8074/v1/com_dtypes.h b/hw/qca8074/v1/com_dtypes.h index a1c0edccc566..ebf2f286afdd 100644 --- a/hw/qca8074/v1/com_dtypes.h +++ b/hw/qca8074/v1/com_dtypes.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -21,28 +21,28 @@ /** @file com_dtypes.h - @brief This header file contains general data types that are of use to all - modules. + @brief This header file contains general data types that are of use to all + modules. */ /*=========================================================================== -NOTE: The @brief description and any detailed descriptions above do not appear - in the PDF. +NOTE: The @brief description and any detailed descriptions above do not appear + in the PDF. - The Utility_Services_API_mainpage.dox file contains all file/group - descriptions that are in the output PDF generated using Doxygen and - Latex. To edit or update any of the file/group text in the PDF, edit + The Utility_Services_API_mainpage.dox file contains all file/group + descriptions that are in the output PDF generated using Doxygen and + Latex. To edit or update any of the file/group text in the PDF, edit the Utility_Services_API_mainpage.dox file or contact Tech Pubs. - The above description for this file is part of the "utils_services" - group description in the Utility_Services_API_mainpage.dox file. + The above description for this file is part of the "utils_services" + group description in the Utility_Services_API_mainpage.dox file. ===========================================================================*/ /*=========================================================================== S T A N D A R D D E C L A R A T I O N S DESCRIPTION - This header file contains general data types that are of use to all modules. + This header file contains general data types that are of use to all modules. The values or definitions are dependent on the specified target. T_WINNT specifies Windows NT based targets, otherwise the default is for ARM targets. @@ -61,7 +61,7 @@ DESCRIPTION This section contains comments describing changes made to this file. Notice that changes are listed in reverse chronological order. -$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/com_dtypes.h,v 1.1.1.1 2012/09/19 22:33:30 rjindal Exp $ +$Header: //depot/prj/qca/lithium/ip/wmac/wmac_recipes/xml/autoseq/com_dtypes.h#2 $ when who what, where, why -------- --- ---------------------------------------------------------- @@ -91,7 +91,7 @@ extern "C" { #endif #include #endif - +#include /* ------------------------------------------------------------------------ ** Constants ** ------------------------------------------------------------------------ */ @@ -116,7 +116,7 @@ extern "C" { #define OFF 0 /**< OFF value. */ #ifndef NULL - #define NULL 0 /**< NULL value. */ + #define NULL 0 /**< NULL value. */ #endif /** @} */ /* end_name_group Macros for Common Data Types */ @@ -134,15 +134,15 @@ extern "C" { /** @addtogroup utils_services @{ */ -/** Boolean value type. +/** Boolean value type. */ -typedef unsigned char boolean; +typedef unsigned char boolean; #define _BOOLEAN_DEFINED #endif -/** @cond +/** @cond */ -#if defined(DALSTDDEF_H) /* guards against a known re-definer */ +//#if defined(DALSTDDEF_H) /* guards against a known re-definer */ #define _BOOLEAN_DEFINED #define _UINT32_DEFINED #define _UINT16_DEFINED @@ -153,48 +153,48 @@ typedef unsigned char boolean; #define _UINT64_DEFINED #define _INT64_DEFINED #define _BYTE_DEFINED -#endif /* #if !defined(DALSTDDEF_H) */ +//#endif /* #if !defined(DALSTDDEF_H) */ /** @endcond */ #ifndef _UINT32_DEFINED /** Unsigned 32-bit value. */ -typedef unsigned long int uint32; +typedef unsigned int uint32_t; #define _UINT32_DEFINED #endif #ifndef _UINT16_DEFINED /** Unsigned 16-bit value. */ -typedef unsigned short uint16; +typedef unsigned short uint16_t; #define _UINT16_DEFINED #endif #ifndef _UINT8_DEFINED -/** Unsigned 8-bit value. +/** Unsigned 8-bit value. */ -typedef unsigned char uint8; +typedef unsigned char uint8_t; #define _UINT8_DEFINED #endif #ifndef _INT32_DEFINED /** Signed 32-bit value. */ -typedef signed long int int32; +typedef signed int int32_t; #define _INT32_DEFINED #endif #ifndef _INT16_DEFINED /** Signed 16-bit value. */ -typedef signed short int16; +typedef signed short int16_t; #define _INT16_DEFINED #endif #ifndef _INT8_DEFINED /** Signed 8-bit value. */ -typedef signed char int8; +typedef signed char int8_t; #define _INT8_DEFINED #endif @@ -206,7 +206,7 @@ typedef signed char int8; #ifndef _BYTE_DEFINED /** DEPRECATED: Unsigned 8 bit value type. */ -typedef unsigned char byte; +typedef unsigned char byte; #define _BYTE_DEFINED #endif @@ -215,7 +215,7 @@ typedef unsigned char byte; typedef unsigned short word; /** DEPRECATED: Unsigned 32 bit value type. */ -typedef unsigned long dword; +typedef unsigned int dword; /** DEPRECATED: Unsigned 8 bit value type. */ @@ -225,35 +225,35 @@ typedef unsigned char uint1; typedef unsigned short uint2; /** DEPRECATED: Unsigned 32 bit value type. */ -typedef unsigned long uint4; +typedef unsigned int uint4; -/** DEPRECATED: Signed 8 bit value type. +/** DEPRECATED: Signed 8 bit value type. */ typedef signed char int1; /** DEPRECATED: Signed 16 bit value type. -*/ +*/ typedef signed short int2; -/** DEPRECATED: Signed 32 bit value type. -*/ -typedef long int int4; +/** DEPRECATED: Signed 32 bit value type. +*/ +typedef long int int4; /** DEPRECATED: Signed 32 bit value. */ typedef signed long sint31; -/** DEPRECATED: Signed 16 bit value. -*/ +/** DEPRECATED: Signed 16 bit value. +*/ typedef signed short sint15; /** DEPRECATED: Signed 8 bit value. -*/ -typedef signed char sint7; +*/ +typedef signed char sint7; -typedef uint16 UWord16 ; -typedef uint32 UWord32 ; -typedef int32 Word32 ; -typedef int16 Word16 ; -typedef uint8 UWord8 ; -typedef int8 Word8 ; -typedef int32 Vect32 ; +typedef uint16_t UWord16 ; +typedef uint32_t UWord32 ; +typedef int32_t Word32 ; +typedef int16_t Word16 ; +typedef uint8_t UWord8 ; +typedef int8_t Word8 ; +typedef int32_t Vect32 ; /** @endcond */ #if (! defined T_WINNT) && (! defined __GNUC__) @@ -261,18 +261,18 @@ typedef int32 Vect32 ; #ifndef _INT64_DEFINED /** Signed 64-bit value. */ - typedef long long int64; + typedef long long int64; #define _INT64_DEFINED #endif #ifndef _UINT64_DEFINED /** Unsigned 64-bit value. */ - typedef unsigned long long uint64; + typedef unsigned long long uint64; #define _UINT64_DEFINED #endif #else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */ /* WINNT or SOLARIS based targets */ - #if (defined __GNUC__) + #if (defined __GNUC__) #ifndef _INT64_DEFINED typedef long long int64; #define _INT64_DEFINED diff --git a/hw/qca8074/v1/mac_tcl_reg_seq_hwioreg.h b/hw/qca8074/v1/mac_tcl_reg_seq_hwioreg.h index 73f4cc2b369a..52910ae391b7 100644 --- a/hw/qca8074/v1/mac_tcl_reg_seq_hwioreg.h +++ b/hw/qca8074/v1/mac_tcl_reg_seq_hwioreg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,7 +18,7 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 2/3/2017 // User Name:pgohil // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. @@ -45,12 +45,12 @@ #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0007ffe1 -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 5 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \ @@ -58,10 +58,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 @@ -69,19 +66,16 @@ #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_BMSK 0x00000001 -#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_SHFT 0x0 - //// Register TCL_R0_SW2TCL2_RING_CTRL //// #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0007ffe1 -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 5 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \ @@ -89,10 +83,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 @@ -100,19 +91,16 @@ #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_BMSK 0x00000001 -#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_SHFT 0x0 - //// Register TCL_R0_SW2TCL3_RING_CTRL //// #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0007ffe1 -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 5 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \ @@ -120,10 +108,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 @@ -131,19 +116,16 @@ #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_BMSK 0x00000001 -#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_SHFT 0x0 - //// Register TCL_R0_FW2TCL1_RING_CTRL //// #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0007ffe1 -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 5 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \ @@ -151,10 +133,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 @@ -162,19 +141,16 @@ #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_BMSK 0x00000001 -#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_SHFT 0x0 - //// Register TCL_R0_SW2TCL_CMD_RING_CTRL //// #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x) (x+0x00000010) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_PHYS(x) (x+0x00000010) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK 0x0007ffe1 -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT 5 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUTM(x, mask, val) \ @@ -182,10 +158,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_BMSK 0x00040000 -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_SHFT 0x12 + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 @@ -193,19 +166,16 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_SHFT 0x5 -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_BMSK 0x00000001 -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_SHFT 0x0 - //// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x00000007 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x00001fff #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \ out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val) #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \ @@ -213,7 +183,37 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_BMSK 0x00001000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_SHFT 0xc + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x00000800 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 0xb + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x00000400 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 0xa + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x00000200 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 0x9 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x00000100 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 0x8 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_BMSK 0x00000080 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_SHFT 0x7 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x00000040 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 0x6 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x00000020 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 0x5 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x00000010 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 0x4 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x00000008 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 0x3 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 @@ -233,7 +233,7 @@ #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \ @@ -241,7 +241,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 @@ -255,7 +255,7 @@ #define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \ @@ -263,7 +263,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 @@ -277,7 +277,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \ @@ -285,7 +285,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 @@ -299,7 +299,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \ @@ -307,7 +307,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 @@ -316,12 +316,12 @@ #define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) #define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) -#define HWIO_TCL_R0_GEN_CTRL_RMSK 0xffff7e1d +#define HWIO_TCL_R0_GEN_CTRL_RMSK 0xffff7ffd #define HWIO_TCL_R0_GEN_CTRL_SHFT 0 #define HWIO_TCL_R0_GEN_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) #define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val) #define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \ @@ -329,7 +329,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10 @@ -346,6 +346,18 @@ #define HWIO_TCL_R0_GEN_CTRL_MAC_ID_BMSK 0x00000e00 #define HWIO_TCL_R0_GEN_CTRL_MAC_ID_SHFT 0x9 +#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x00000100 +#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 0x8 + +#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x00000080 +#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 0x7 + +#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x00000040 +#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 0x6 + +#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x00000020 +#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 0x5 + #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 @@ -367,7 +379,7 @@ #define HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK) #define HWIO_TCL_R0_DSCP_TID1_MAP_0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUTM(x, mask, val) \ @@ -375,7 +387,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_SHFT 0x1b @@ -416,7 +428,7 @@ #define HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK) #define HWIO_TCL_R0_DSCP_TID1_MAP_1_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUTM(x, mask, val) \ @@ -424,7 +436,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_SHFT 0x1b @@ -465,7 +477,7 @@ #define HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK) #define HWIO_TCL_R0_DSCP_TID1_MAP_2_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUTM(x, mask, val) \ @@ -473,7 +485,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_SHFT 0x1b @@ -514,7 +526,7 @@ #define HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK) #define HWIO_TCL_R0_DSCP_TID1_MAP_3_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUTM(x, mask, val) \ @@ -522,7 +534,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_SHFT 0x1b @@ -563,7 +575,7 @@ #define HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK) #define HWIO_TCL_R0_DSCP_TID1_MAP_4_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUTM(x, mask, val) \ @@ -571,7 +583,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_SHFT 0x1b @@ -612,7 +624,7 @@ #define HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK) #define HWIO_TCL_R0_DSCP_TID1_MAP_5_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUTM(x, mask, val) \ @@ -620,7 +632,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_SHFT 0x1b @@ -661,7 +673,7 @@ #define HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK) #define HWIO_TCL_R0_DSCP_TID1_MAP_6_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUTM(x, mask, val) \ @@ -669,7 +681,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_BMSK 0x00000e00 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_SHFT 0x9 @@ -692,7 +704,7 @@ #define HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK) #define HWIO_TCL_R0_DSCP_TID2_MAP_0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUTM(x, mask, val) \ @@ -700,7 +712,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_SHFT 0x1b @@ -741,7 +753,7 @@ #define HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK) #define HWIO_TCL_R0_DSCP_TID2_MAP_1_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUTM(x, mask, val) \ @@ -749,7 +761,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_SHFT 0x1b @@ -790,7 +802,7 @@ #define HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK) #define HWIO_TCL_R0_DSCP_TID2_MAP_2_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUTM(x, mask, val) \ @@ -798,7 +810,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_SHFT 0x1b @@ -839,7 +851,7 @@ #define HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK) #define HWIO_TCL_R0_DSCP_TID2_MAP_3_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUTM(x, mask, val) \ @@ -847,7 +859,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_SHFT 0x1b @@ -888,7 +900,7 @@ #define HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK) #define HWIO_TCL_R0_DSCP_TID2_MAP_4_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUTM(x, mask, val) \ @@ -896,7 +908,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_SHFT 0x1b @@ -937,7 +949,7 @@ #define HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK) #define HWIO_TCL_R0_DSCP_TID2_MAP_5_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUTM(x, mask, val) \ @@ -945,7 +957,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_BMSK 0x38000000 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_SHFT 0x1b @@ -986,7 +998,7 @@ #define HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x) \ in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK) #define HWIO_TCL_R0_DSCP_TID2_MAP_6_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask) #define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUT(x, val) \ out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), val) #define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUTM(x, mask, val) \ @@ -994,7 +1006,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_BMSK 0x00000e00 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_SHFT 0x9 @@ -1017,7 +1029,7 @@ #define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK) #define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) #define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \ out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val) #define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \ @@ -1025,7 +1037,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15 @@ -1060,7 +1072,7 @@ #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK) #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \ out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val) #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \ @@ -1068,7 +1080,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0 @@ -1082,7 +1094,7 @@ #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK) #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \ out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val) #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \ @@ -1090,7 +1102,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0 @@ -1104,7 +1116,7 @@ #define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK) #define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \ out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val) #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \ @@ -1112,7 +1124,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0 @@ -1126,7 +1138,7 @@ #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK) #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask) #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), val) #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUTM(x, mask, val) \ @@ -1134,7 +1146,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_SHFT 0x0 @@ -1148,7 +1160,7 @@ #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK) #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask) #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), val) #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUTM(x, mask, val) \ @@ -1156,7 +1168,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_SHFT 0x0 @@ -1170,7 +1182,7 @@ #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK) #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask) #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), val) #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUTM(x, mask, val) \ @@ -1178,7 +1190,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_SHFT 0x0 @@ -1192,7 +1204,7 @@ #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK) #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask) #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), val) #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUTM(x, mask, val) \ @@ -1200,7 +1212,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_SHFT 0x0 @@ -1214,7 +1226,7 @@ #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK) #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask) #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), val) #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUTM(x, mask, val) \ @@ -1222,7 +1234,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_SHFT 0x0 @@ -1236,7 +1248,7 @@ #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK) #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask) #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), val) #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUTM(x, mask, val) \ @@ -1244,7 +1256,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_SHFT 0x0 @@ -1258,7 +1270,7 @@ #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK) #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask) #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), val) #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUTM(x, mask, val) \ @@ -1266,7 +1278,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_SHFT 0x0 @@ -1280,7 +1292,7 @@ #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK) #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask) #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), val) #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUTM(x, mask, val) \ @@ -1288,7 +1300,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_SHFT 0x0 @@ -1302,7 +1314,7 @@ #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK) #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask) #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), val) #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUTM(x, mask, val) \ @@ -1310,7 +1322,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_SHFT 0x0 @@ -1324,7 +1336,7 @@ #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK) #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask) #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), val) #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUTM(x, mask, val) \ @@ -1332,7 +1344,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_BMSK 0x07ffffff #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_SHFT 0x0 @@ -1346,7 +1358,7 @@ #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK) #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \ out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val) #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \ @@ -1354,7 +1366,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd @@ -1386,7 +1398,7 @@ #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK) #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ @@ -1394,7 +1406,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 @@ -1408,7 +1420,7 @@ #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK) #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ @@ -1416,7 +1428,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 @@ -1430,7 +1442,7 @@ #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK) #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ @@ -1438,7 +1450,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 @@ -1452,7 +1464,7 @@ #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK) #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ @@ -1460,7 +1472,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 @@ -1474,7 +1486,7 @@ #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK) #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \ out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val) #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \ @@ -1482,7 +1494,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10 @@ -1499,7 +1511,7 @@ #define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK) #define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) #define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \ out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val) #define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \ @@ -1507,7 +1519,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5 @@ -1524,7 +1536,7 @@ #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK) #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ @@ -1532,7 +1544,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0 @@ -1546,7 +1558,7 @@ #define HWIO_TCL_R0_WATCHDOG_IN(x) \ in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK) #define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) #define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \ out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val) #define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \ @@ -1554,7 +1566,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000 #define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10 @@ -1571,7 +1583,7 @@ #define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \ in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK) #define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) #define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \ out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val) #define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \ @@ -1579,7 +1591,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_SHFT 0x0 @@ -1593,7 +1605,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -1601,7 +1613,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -1615,7 +1627,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -1623,7 +1635,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -1635,12 +1647,12 @@ #define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x000000cc) #define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x000000cc) -#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \ @@ -1648,10 +1660,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1665,7 +1674,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \ @@ -1673,7 +1682,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -1690,7 +1699,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \ @@ -1698,7 +1707,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -1727,7 +1736,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -1735,7 +1744,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -1749,7 +1758,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -1757,7 +1766,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -1771,7 +1780,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -1779,7 +1788,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -1799,7 +1808,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -1807,7 +1816,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -1821,7 +1830,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -1829,7 +1838,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -1844,12 +1853,12 @@ #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000100) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000100) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -1857,9 +1866,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// @@ -1871,7 +1880,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -1879,7 +1888,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -1893,7 +1902,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -1901,7 +1910,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -1918,7 +1927,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -1926,7 +1935,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -1940,7 +1949,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -1948,7 +1957,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -1965,7 +1974,7 @@ #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -1973,7 +1982,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -1982,12 +1991,12 @@ #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000118) #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000118) -#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -1995,9 +2004,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// @@ -2009,7 +2018,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -2017,7 +2026,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -2031,7 +2040,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -2039,7 +2048,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -2051,12 +2060,12 @@ #define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x00000124) #define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x00000124) -#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \ @@ -2064,10 +2073,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2081,7 +2087,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \ @@ -2089,7 +2095,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -2106,7 +2112,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \ @@ -2114,7 +2120,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -2143,7 +2149,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -2151,7 +2157,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -2165,7 +2171,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -2173,7 +2179,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -2187,7 +2193,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -2195,7 +2201,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -2215,7 +2221,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -2223,7 +2229,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -2237,7 +2243,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -2245,7 +2251,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -2260,12 +2266,12 @@ #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000158) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000158) -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -2273,9 +2279,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// @@ -2287,7 +2293,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -2295,7 +2301,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -2309,7 +2315,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -2317,7 +2323,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -2334,7 +2340,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -2342,7 +2348,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -2356,7 +2362,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -2364,7 +2370,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -2381,7 +2387,7 @@ #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -2389,7 +2395,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -2398,12 +2404,12 @@ #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000170) #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000170) -#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -2411,9 +2417,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// @@ -2425,7 +2431,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -2433,7 +2439,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -2447,7 +2453,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -2455,7 +2461,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -2467,12 +2473,12 @@ #define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x0000017c) #define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x0000017c) -#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \ @@ -2480,10 +2486,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2497,7 +2500,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \ @@ -2505,7 +2508,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -2522,7 +2525,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \ @@ -2530,7 +2533,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -2559,7 +2562,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -2567,7 +2570,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -2581,7 +2584,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -2589,7 +2592,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -2603,7 +2606,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -2611,7 +2614,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -2631,7 +2634,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -2639,7 +2642,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -2653,7 +2656,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -2661,7 +2664,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -2676,12 +2679,12 @@ #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001b0) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001b0) -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -2689,9 +2692,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// @@ -2703,7 +2706,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -2711,7 +2714,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -2725,7 +2728,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -2733,7 +2736,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -2750,7 +2753,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -2758,7 +2761,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -2772,7 +2775,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -2780,7 +2783,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -2797,7 +2800,7 @@ #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -2805,7 +2808,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -2814,12 +2817,12 @@ #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001c8) #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001c8) -#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -2827,9 +2830,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_LSB //// @@ -2841,7 +2844,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -2849,7 +2852,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -2863,7 +2866,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -2871,7 +2874,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -2883,12 +2886,12 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x) (x+0x000001d4) #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_PHYS(x) (x+0x000001d4) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUTM(x, mask, val) \ @@ -2896,10 +2899,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2913,7 +2913,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUTM(x, mask, val) \ @@ -2921,7 +2921,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -2938,7 +2938,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUTM(x, mask, val) \ @@ -2946,7 +2946,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -2975,7 +2975,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -2983,7 +2983,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -2997,7 +2997,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -3005,7 +3005,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -3019,7 +3019,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -3027,7 +3027,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -3047,7 +3047,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -3055,7 +3055,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -3069,7 +3069,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -3077,7 +3077,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -3092,12 +3092,12 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000208) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000208) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -3105,9 +3105,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER //// @@ -3119,7 +3119,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -3127,7 +3127,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -3141,7 +3141,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -3149,7 +3149,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -3166,7 +3166,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -3174,7 +3174,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -3188,7 +3188,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -3196,7 +3196,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -3213,7 +3213,7 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -3221,7 +3221,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -3230,12 +3230,12 @@ #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000220) #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000220) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -3243,9 +3243,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// @@ -3257,7 +3257,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -3265,7 +3265,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -3279,7 +3279,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -3287,7 +3287,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -3299,12 +3299,12 @@ #define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x0000022c) #define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x0000022c) -#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff #define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \ @@ -3312,10 +3312,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -3329,7 +3326,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \ @@ -3337,7 +3334,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -3354,7 +3351,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \ @@ -3362,7 +3359,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -3391,7 +3388,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -3399,7 +3396,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -3413,7 +3410,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -3421,7 +3418,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -3435,7 +3432,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -3443,7 +3440,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -3463,7 +3460,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -3471,7 +3468,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -3485,7 +3482,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -3493,7 +3490,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -3508,12 +3505,12 @@ #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000260) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000260) -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -3521,9 +3518,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// @@ -3535,7 +3532,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -3543,7 +3540,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -3557,7 +3554,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -3565,7 +3562,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -3582,7 +3579,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -3590,7 +3587,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -3604,7 +3601,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -3612,7 +3609,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -3629,7 +3626,7 @@ #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -3637,7 +3634,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -3646,12 +3643,12 @@ #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000278) #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000278) -#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -3659,9 +3656,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// @@ -3673,7 +3670,7 @@ #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -3681,7 +3678,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -3695,7 +3692,7 @@ #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -3703,7 +3700,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -3720,7 +3717,7 @@ #define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \ @@ -3728,7 +3725,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8 @@ -3745,7 +3742,7 @@ #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \ @@ -3753,7 +3750,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -3770,7 +3767,7 @@ #define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \ @@ -3778,7 +3775,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -3807,7 +3804,7 @@ #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -3815,7 +3812,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -3829,7 +3826,7 @@ #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -3837,7 +3834,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -3851,7 +3848,7 @@ #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -3859,7 +3856,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -3879,7 +3876,7 @@ #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -3887,7 +3884,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -3902,12 +3899,12 @@ #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002a8) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002a8) -#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -3915,21 +3912,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002d0) #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002d0) -#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -3937,9 +3934,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// @@ -3951,7 +3948,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -3959,7 +3956,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -3973,7 +3970,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -3981,7 +3978,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -3998,7 +3995,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \ @@ -4006,7 +4003,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8 @@ -4023,7 +4020,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \ @@ -4031,7 +4028,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -4048,7 +4045,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \ @@ -4056,7 +4053,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -4085,7 +4082,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -4093,7 +4090,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -4107,7 +4104,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -4115,7 +4112,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -4129,7 +4126,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -4137,7 +4134,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -4157,7 +4154,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -4165,7 +4162,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -4180,12 +4177,12 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000300) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000300) -#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -4193,9 +4190,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// @@ -4207,7 +4204,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -4215,7 +4212,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -4229,7 +4226,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -4237,7 +4234,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -4254,7 +4251,7 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -4262,7 +4259,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -4271,12 +4268,12 @@ #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000328) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000328) -#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -4284,9 +4281,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// @@ -4298,7 +4295,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -4306,7 +4303,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -4320,7 +4317,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -4328,7 +4325,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -4345,7 +4342,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \ @@ -4353,7 +4350,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8 @@ -4370,7 +4367,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \ @@ -4378,7 +4375,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -4395,7 +4392,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \ @@ -4403,7 +4400,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -4432,7 +4429,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -4440,7 +4437,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -4454,7 +4451,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -4462,7 +4459,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -4476,7 +4473,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -4484,7 +4481,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -4504,7 +4501,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -4512,7 +4509,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -4527,12 +4524,12 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000358) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000358) -#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -4540,9 +4537,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// @@ -4554,7 +4551,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -4562,7 +4559,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -4576,7 +4573,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -4584,7 +4581,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -4601,7 +4598,7 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -4609,7 +4606,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -4618,12 +4615,12 @@ #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000380) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000380) -#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -4631,9 +4628,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_TCL2FW_RING_BASE_LSB //// @@ -4645,7 +4642,7 @@ #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -4653,7 +4650,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -4667,7 +4664,7 @@ #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -4675,7 +4672,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -4692,7 +4689,7 @@ #define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \ @@ -4700,7 +4697,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8 @@ -4717,7 +4714,7 @@ #define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \ @@ -4725,7 +4722,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -4742,7 +4739,7 @@ #define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \ @@ -4750,7 +4747,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -4779,7 +4776,7 @@ #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -4787,7 +4784,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -4801,7 +4798,7 @@ #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -4809,7 +4806,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -4823,7 +4820,7 @@ #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -4831,7 +4828,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -4851,7 +4848,7 @@ #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -4859,7 +4856,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -4874,12 +4871,12 @@ #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003b0) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003b0) -#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -4887,21 +4884,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003d8) #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003d8) -#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -4909,9 +4906,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register TCL_R0_GXI_TESTBUS_LOWER //// @@ -4923,7 +4920,7 @@ #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK) #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val) #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ @@ -4931,7 +4928,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 @@ -4945,7 +4942,7 @@ #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK) #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val) #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ @@ -4953,7 +4950,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 @@ -4967,7 +4964,7 @@ #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK) #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val) #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ @@ -4975,7 +4972,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 @@ -4995,7 +4992,7 @@ #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK) #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ @@ -5003,7 +5000,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 @@ -5017,7 +5014,7 @@ #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK) #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ @@ -5025,7 +5022,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f @@ -5042,7 +5039,7 @@ #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK) #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val) #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ @@ -5050,7 +5047,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 @@ -5073,7 +5070,7 @@ #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK) #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val) #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ @@ -5081,7 +5078,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 @@ -5101,7 +5098,7 @@ #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ @@ -5109,7 +5106,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 @@ -5132,7 +5129,7 @@ #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK) #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ @@ -5140,7 +5137,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 @@ -5163,7 +5160,7 @@ #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK) #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ @@ -5171,7 +5168,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 @@ -5197,7 +5194,7 @@ #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK) #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ @@ -5205,7 +5202,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 @@ -5222,7 +5219,7 @@ #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK) #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ @@ -5230,7 +5227,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 @@ -5244,7 +5241,7 @@ #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK) #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ @@ -5252,7 +5249,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 @@ -5269,7 +5266,7 @@ #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK) #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \ out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val) #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ @@ -5277,7 +5274,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 @@ -5291,7 +5288,7 @@ #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK) #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \ out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val) #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ @@ -5299,7 +5296,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 @@ -5313,7 +5310,7 @@ #define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK) #define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) #define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \ out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val) #define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \ @@ -5321,7 +5318,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0 @@ -5335,7 +5332,7 @@ #define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK) #define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val) #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \ @@ -5343,7 +5340,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 @@ -5366,7 +5363,7 @@ #define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK) #define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) #define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \ out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val) #define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \ @@ -5374,7 +5371,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10 @@ -5391,7 +5388,7 @@ #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK) #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \ out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val) #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \ @@ -5399,7 +5396,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_SHFT 0x0 @@ -5413,7 +5410,7 @@ #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK) #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \ out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val) #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ @@ -5421,7 +5418,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 @@ -5435,7 +5432,7 @@ #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK) #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask) #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), val) #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ @@ -5443,7 +5440,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 @@ -5457,7 +5454,7 @@ #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK) #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask) #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), val) #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ @@ -5465,7 +5462,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 @@ -5479,7 +5476,7 @@ #define HWIO_TCL_R0_FSE_GST_SIZE_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), HWIO_TCL_R0_FSE_GST_SIZE_RMSK) #define HWIO_TCL_R0_FSE_GST_SIZE_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask) #define HWIO_TCL_R0_FSE_GST_SIZE_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), val) #define HWIO_TCL_R0_FSE_GST_SIZE_OUTM(x, mask, val) \ @@ -5487,7 +5484,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_SIZE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_GST_SIZE_VAL_BMSK 0x000fffff #define HWIO_TCL_R0_FSE_GST_SIZE_VAL_SHFT 0x0 @@ -5501,7 +5498,7 @@ #define HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK) #define HWIO_TCL_R0_FSE_SEARCH_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask) #define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), val) #define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUTM(x, mask, val) \ @@ -5509,7 +5506,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 @@ -5532,7 +5529,7 @@ #define HWIO_TCL_R0_FSE_WATCHDOG_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), HWIO_TCL_R0_FSE_WATCHDOG_RMSK) #define HWIO_TCL_R0_FSE_WATCHDOG_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask) #define HWIO_TCL_R0_FSE_WATCHDOG_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), val) #define HWIO_TCL_R0_FSE_WATCHDOG_OUTM(x, mask, val) \ @@ -5540,7 +5537,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WATCHDOG_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_BMSK 0xffff0000 #define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_SHFT 0x10 @@ -5557,7 +5554,7 @@ #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK) #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask) #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), val) #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUTM(x, mask, val) \ @@ -5565,7 +5562,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_BMSK 0xffffffff #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_SHFT 0x0 @@ -5579,7 +5576,7 @@ #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x) \ in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK) #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask) #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUT(x, val) \ out_dword( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), val) #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ @@ -5587,7 +5584,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 @@ -5601,7 +5598,7 @@ #define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) #define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) #define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \ out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val) #define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ @@ -5609,7 +5606,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x07000000 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x18 @@ -5647,7 +5644,7 @@ #define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) #define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) #define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \ out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val) #define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ @@ -5655,7 +5652,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc @@ -5681,7 +5678,7 @@ #define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK) #define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \ out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val) #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \ @@ -5689,7 +5686,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17 @@ -5718,7 +5715,7 @@ #define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK) #define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) #define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \ out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val) #define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \ @@ -5726,7 +5723,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff #define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0 @@ -5740,7 +5737,7 @@ #define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK) #define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) #define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \ out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val) #define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ @@ -5748,7 +5745,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0 @@ -5762,7 +5759,7 @@ #define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK) #define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) #define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \ out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val) #define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ @@ -5770,7 +5767,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0 @@ -5784,7 +5781,7 @@ #define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK) #define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) #define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \ out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val) #define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ @@ -5792,7 +5789,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0 @@ -5806,7 +5803,7 @@ #define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK) #define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) #define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \ out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val) #define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ @@ -5814,7 +5811,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0 @@ -5828,7 +5825,7 @@ #define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK) #define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) #define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \ out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val) #define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ @@ -5836,7 +5833,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0 @@ -5850,7 +5847,7 @@ #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ @@ -5858,7 +5855,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 @@ -5881,7 +5878,7 @@ #define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK) #define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \ out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val) #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ @@ -5889,7 +5886,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 @@ -5903,7 +5900,7 @@ #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK) #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \ out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val) #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ @@ -5911,7 +5908,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 @@ -5925,7 +5922,7 @@ #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK) #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ @@ -5933,7 +5930,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 @@ -5947,7 +5944,7 @@ #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ @@ -5955,7 +5952,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 @@ -5969,7 +5966,7 @@ #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ @@ -5977,7 +5974,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 @@ -5991,7 +5988,7 @@ #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ @@ -5999,7 +5996,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa @@ -6016,7 +6013,7 @@ #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK) #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ @@ -6024,7 +6021,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa @@ -6044,7 +6041,7 @@ #define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK) #define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) #define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \ out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val) #define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \ @@ -6052,7 +6049,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 @@ -6090,7 +6087,7 @@ #define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \ out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \ @@ -6098,7 +6095,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0 @@ -6112,7 +6109,7 @@ #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ @@ -6120,7 +6117,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 @@ -6144,7 +6141,7 @@ #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ - in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ @@ -6152,7 +6149,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 @@ -6166,7 +6163,7 @@ #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x) \ in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK) #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask) #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUT(x, val) \ out_dword( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), val) #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ @@ -6174,7 +6171,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 @@ -6188,7 +6185,7 @@ #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x) \ in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK) #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ out_dword( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ @@ -6196,7 +6193,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 @@ -6210,7 +6207,7 @@ #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ @@ -6218,7 +6215,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 @@ -6232,7 +6229,7 @@ #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ @@ -6240,7 +6237,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 @@ -6254,7 +6251,7 @@ #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ @@ -6262,7 +6259,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa @@ -6279,7 +6276,7 @@ #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK) #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ out_dword( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ @@ -6287,7 +6284,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa @@ -6307,7 +6304,7 @@ #define HWIO_TCL_R1_FSE_SM_STATES_IN(x) \ in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), HWIO_TCL_R1_FSE_SM_STATES_RMSK) #define HWIO_TCL_R1_FSE_SM_STATES_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask) #define HWIO_TCL_R1_FSE_SM_STATES_OUT(x, val) \ out_dword( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), val) #define HWIO_TCL_R1_FSE_SM_STATES_OUTM(x, mask, val) \ @@ -6315,7 +6312,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_FSE_SM_STATES_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 #define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 @@ -6353,7 +6350,7 @@ #define HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x) \ in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUT(x, val) \ out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), val) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUTM(x, mask, val) \ @@ -6361,7 +6358,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff #define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_SHFT 0x0 @@ -6375,7 +6372,7 @@ #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ @@ -6383,7 +6380,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 @@ -6407,7 +6404,7 @@ #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ - in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) + in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ @@ -6415,7 +6412,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 @@ -6429,7 +6426,7 @@ #define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK) #define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \ out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val) #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \ @@ -6437,7 +6434,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 @@ -6451,7 +6448,7 @@ #define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK) #define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \ out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val) #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \ @@ -6459,7 +6456,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 @@ -6473,7 +6470,7 @@ #define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK) #define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \ out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val) #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \ @@ -6481,7 +6478,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0 @@ -6495,7 +6492,7 @@ #define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK) #define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \ out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val) #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \ @@ -6503,7 +6500,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0 @@ -6517,7 +6514,7 @@ #define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK) #define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \ out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val) #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \ @@ -6525,7 +6522,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0 @@ -6539,7 +6536,7 @@ #define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK) #define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \ out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val) #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \ @@ -6547,7 +6544,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0 @@ -6561,7 +6558,7 @@ #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK) #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask) #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUT(x, val) \ out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), val) #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUTM(x, mask, val) \ @@ -6569,7 +6566,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_SHFT 0x0 @@ -6583,7 +6580,7 @@ #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK) #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask) #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUT(x, val) \ out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), val) #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUTM(x, mask, val) \ @@ -6591,7 +6588,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_SHFT 0x0 @@ -6605,7 +6602,7 @@ #define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK) #define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \ out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val) #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \ @@ -6613,7 +6610,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 @@ -6627,7 +6624,7 @@ #define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK) #define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \ out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val) #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \ @@ -6635,7 +6632,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 @@ -6649,7 +6646,7 @@ #define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK) #define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \ out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val) #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \ @@ -6657,7 +6654,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0 @@ -6671,7 +6668,7 @@ #define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK) #define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \ out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val) #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \ @@ -6679,7 +6676,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0 @@ -6693,7 +6690,7 @@ #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK) #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \ out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val) #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \ @@ -6701,7 +6698,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0 @@ -6715,7 +6712,7 @@ #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK) #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \ out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val) #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \ @@ -6723,7 +6720,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0 @@ -6737,7 +6734,7 @@ #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK) #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \ out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val) #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \ @@ -6745,7 +6742,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0 @@ -6759,7 +6756,7 @@ #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK) #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \ out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val) #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \ @@ -6767,7 +6764,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0 @@ -6781,7 +6778,7 @@ #define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK) #define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) #define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \ out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val) #define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \ @@ -6789,7 +6786,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0 @@ -6803,7 +6800,7 @@ #define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK) #define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) #define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \ out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val) #define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \ @@ -6811,7 +6808,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0 diff --git a/hw/qca8074/v1/reo_reg_seq_hwioreg.h b/hw/qca8074/v1/reo_reg_seq_hwioreg.h index 263123e3a540..acdef8a39d6d 100644 --- a/hw/qca8074/v1/reo_reg_seq_hwioreg.h +++ b/hw/qca8074/v1/reo_reg_seq_hwioreg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,7 +18,7 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 2/3/2017 // User Name:pgohil // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. @@ -50,7 +50,7 @@ #define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK) #define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) #define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val) \ out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val) #define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ @@ -58,7 +58,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x10000000 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 0x1c @@ -132,7 +132,7 @@ #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ @@ -140,7 +140,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xe0000000 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 0x1d @@ -175,7 +175,7 @@ #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ @@ -183,7 +183,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xe0000000 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 0x1d @@ -218,7 +218,7 @@ #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ @@ -226,7 +226,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xe0000000 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 0x1d @@ -261,7 +261,7 @@ #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ @@ -269,7 +269,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xe0000000 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 0x1d @@ -304,7 +304,7 @@ #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ @@ -312,7 +312,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0xe0000000 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 0x1d @@ -347,7 +347,7 @@ #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ @@ -355,7 +355,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0xe0000000 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 0x1d @@ -390,7 +390,7 @@ #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ @@ -398,7 +398,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0xe0000000 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 0x1d @@ -433,7 +433,7 @@ #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ @@ -441,7 +441,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0xe0000000 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 0x1d @@ -476,7 +476,7 @@ #define HWIO_REO_R0_TIMESTAMP_IN(x) \ in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK) #define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) #define HWIO_REO_R0_TIMESTAMP_OUT(x, val) \ out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val) #define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ @@ -484,7 +484,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0x0 @@ -498,7 +498,7 @@ #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK) #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val) #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ @@ -506,7 +506,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_BMSK 0x38000000 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_SHFT 0x1b @@ -547,7 +547,7 @@ #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK) #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val) #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ @@ -555,7 +555,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0x00038000 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 0xf @@ -584,7 +584,7 @@ #define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK) #define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) #define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val) \ out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val) #define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ @@ -592,7 +592,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x00000002 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 0x1 @@ -609,7 +609,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -617,7 +617,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -631,7 +631,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -639,7 +639,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -651,12 +651,12 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c) #define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c) -#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ @@ -664,10 +664,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -681,7 +678,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ @@ -689,7 +686,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -706,7 +703,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ @@ -714,7 +711,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -743,7 +740,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -751,7 +748,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -765,7 +762,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -773,7 +770,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -787,7 +784,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -795,7 +792,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -815,7 +812,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -823,7 +820,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -837,7 +834,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -845,7 +842,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -860,12 +857,12 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070) -#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -873,9 +870,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER //// @@ -887,7 +884,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -895,7 +892,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -909,7 +906,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -917,7 +914,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -934,7 +931,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -942,7 +939,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -956,7 +953,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -964,7 +961,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -981,7 +978,7 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -989,7 +986,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -998,12 +995,12 @@ #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088) #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088) -#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -1011,9 +1008,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_RXDMA2REO1_RING_BASE_LSB //// @@ -1025,7 +1022,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -1033,7 +1030,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -1047,7 +1044,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -1055,7 +1052,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -1067,12 +1064,12 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x) (x+0x00000094) #define HWIO_REO_R0_RXDMA2REO1_RING_ID_PHYS(x) (x+0x00000094) -#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO1_RING_ID_SHFT 0 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUTM(x, mask, val) \ @@ -1080,10 +1077,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1097,7 +1091,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUTM(x, mask, val) \ @@ -1105,7 +1099,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -1122,7 +1116,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUTM(x, mask, val) \ @@ -1130,7 +1124,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -1159,7 +1153,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -1167,7 +1161,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -1181,7 +1175,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -1189,7 +1183,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -1203,7 +1197,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -1211,7 +1205,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -1231,7 +1225,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -1239,7 +1233,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -1253,7 +1247,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -1261,7 +1255,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -1276,12 +1270,12 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8) -#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -1289,9 +1283,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER //// @@ -1303,7 +1297,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -1311,7 +1305,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -1325,7 +1319,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -1333,7 +1327,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -1350,7 +1344,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -1358,7 +1352,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -1372,7 +1366,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -1380,7 +1374,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -1397,7 +1391,7 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -1405,7 +1399,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -1414,12 +1408,12 @@ #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0) #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0) -#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -1427,9 +1421,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_RXDMA2REO2_RING_BASE_LSB //// @@ -1441,7 +1435,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -1449,7 +1443,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -1463,7 +1457,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -1471,7 +1465,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -1483,12 +1477,12 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x) (x+0x000000ec) #define HWIO_REO_R0_RXDMA2REO2_RING_ID_PHYS(x) (x+0x000000ec) -#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO2_RING_ID_SHFT 0 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUTM(x, mask, val) \ @@ -1496,10 +1490,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1513,7 +1504,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUTM(x, mask, val) \ @@ -1521,7 +1512,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -1538,7 +1529,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUTM(x, mask, val) \ @@ -1546,7 +1537,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -1575,7 +1566,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -1583,7 +1574,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -1597,7 +1588,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -1605,7 +1596,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -1619,7 +1610,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -1627,7 +1618,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -1647,7 +1638,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -1655,7 +1646,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -1669,7 +1660,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -1677,7 +1668,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -1692,12 +1683,12 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) -#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -1705,9 +1696,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER //// @@ -1719,7 +1710,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -1727,7 +1718,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -1741,7 +1732,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -1749,7 +1740,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -1766,7 +1757,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -1774,7 +1765,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -1788,7 +1779,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -1796,7 +1787,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -1813,7 +1804,7 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -1821,7 +1812,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -1830,12 +1821,12 @@ #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) -#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -1843,9 +1834,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB //// @@ -1857,7 +1848,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -1865,7 +1856,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -1879,7 +1870,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -1887,7 +1878,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -1899,12 +1890,12 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000144) #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000144) -#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ @@ -1912,10 +1903,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1929,7 +1917,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ @@ -1937,7 +1925,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -1954,7 +1942,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ @@ -1962,7 +1950,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -1991,7 +1979,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -1999,7 +1987,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -2013,7 +2001,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -2021,7 +2009,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -2035,7 +2023,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -2043,7 +2031,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -2063,7 +2051,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -2071,7 +2059,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -2085,7 +2073,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -2093,7 +2081,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -2108,12 +2096,12 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) -#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -2121,9 +2109,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER //// @@ -2135,7 +2123,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -2143,7 +2131,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -2157,7 +2145,7 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -2165,7 +2153,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -2177,12 +2165,12 @@ #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) -#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -2190,9 +2178,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO_CMD_RING_BASE_LSB //// @@ -2204,7 +2192,7 @@ #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -2212,7 +2200,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -2226,7 +2214,7 @@ #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -2234,7 +2222,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -2246,12 +2234,12 @@ #define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x0000019c) #define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x0000019c) -#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0 #define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK) #define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ @@ -2259,10 +2247,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_REO_R0_REO_CMD_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_REO_CMD_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2276,7 +2261,7 @@ #define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK) #define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ @@ -2284,7 +2269,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -2301,7 +2286,7 @@ #define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK) #define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ @@ -2309,7 +2294,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -2338,7 +2323,7 @@ #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK) #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -2346,7 +2331,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -2360,7 +2345,7 @@ #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK) #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -2368,7 +2353,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -2382,7 +2367,7 @@ #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -2390,7 +2375,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -2410,7 +2395,7 @@ #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -2418,7 +2403,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -2432,7 +2417,7 @@ #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -2440,7 +2425,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -2455,12 +2440,12 @@ #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) -#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -2468,9 +2453,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER //// @@ -2482,7 +2467,7 @@ #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -2490,7 +2475,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -2504,7 +2489,7 @@ #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -2512,7 +2497,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -2529,7 +2514,7 @@ #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -2537,7 +2522,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -2551,7 +2536,7 @@ #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -2559,7 +2544,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -2576,7 +2561,7 @@ #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -2584,7 +2569,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -2593,12 +2578,12 @@ #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) -#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -2606,9 +2591,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_SW2REO_RING_BASE_LSB //// @@ -2620,7 +2605,7 @@ #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -2628,7 +2613,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -2642,7 +2627,7 @@ #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -2650,7 +2635,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -2662,12 +2647,12 @@ #define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x000001f4) #define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x000001f4) -#define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x000000ff #define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0 #define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK) #define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ @@ -2675,10 +2660,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_REO_R0_SW2REO_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_REO_R0_SW2REO_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2692,7 +2674,7 @@ #define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK) #define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ @@ -2700,7 +2682,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -2717,7 +2699,7 @@ #define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK) #define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ @@ -2725,7 +2707,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -2754,7 +2736,7 @@ #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK) #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -2762,7 +2744,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -2776,7 +2758,7 @@ #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK) #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -2784,7 +2766,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -2798,7 +2780,7 @@ #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -2806,7 +2788,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -2826,7 +2808,7 @@ #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -2834,7 +2816,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -2848,7 +2830,7 @@ #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -2856,7 +2838,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -2871,12 +2853,12 @@ #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000228) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000228) -#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -2884,9 +2866,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER //// @@ -2898,7 +2880,7 @@ #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -2906,7 +2888,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -2920,7 +2902,7 @@ #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -2928,7 +2910,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -2945,7 +2927,7 @@ #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -2953,7 +2935,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -2967,7 +2949,7 @@ #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -2975,7 +2957,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -2992,7 +2974,7 @@ #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -3000,7 +2982,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -3009,12 +2991,12 @@ #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) -#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -3022,9 +3004,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2SW1_RING_BASE_LSB //// @@ -3036,7 +3018,7 @@ #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -3044,7 +3026,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -3058,7 +3040,7 @@ #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -3066,7 +3048,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -3083,7 +3065,7 @@ #define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK) #define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ @@ -3091,7 +3073,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8 @@ -3108,7 +3090,7 @@ #define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK) #define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ @@ -3116,7 +3098,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -3133,7 +3115,7 @@ #define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK) #define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ @@ -3141,7 +3123,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -3170,7 +3152,7 @@ #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK) #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -3178,7 +3160,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -3192,7 +3174,7 @@ #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK) #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -3200,7 +3182,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -3214,7 +3196,7 @@ #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -3222,7 +3204,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -3242,7 +3224,7 @@ #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -3250,7 +3232,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -3265,12 +3247,12 @@ #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000270) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000270) -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -3278,9 +3260,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB //// @@ -3292,7 +3274,7 @@ #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -3300,7 +3282,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -3314,7 +3296,7 @@ #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -3322,7 +3304,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -3339,7 +3321,7 @@ #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -3347,7 +3329,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -3356,12 +3338,12 @@ #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) -#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -3369,9 +3351,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2SW2_RING_BASE_LSB //// @@ -3383,7 +3365,7 @@ #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -3391,7 +3373,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -3405,7 +3387,7 @@ #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -3413,7 +3395,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -3430,7 +3412,7 @@ #define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK) #define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ @@ -3438,7 +3420,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 0x8 @@ -3455,7 +3437,7 @@ #define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK) #define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ @@ -3463,7 +3445,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -3480,7 +3462,7 @@ #define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK) #define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ @@ -3488,7 +3470,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -3517,7 +3499,7 @@ #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK) #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -3525,7 +3507,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -3539,7 +3521,7 @@ #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK) #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -3547,7 +3529,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -3561,7 +3543,7 @@ #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -3569,7 +3551,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -3589,7 +3571,7 @@ #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -3597,7 +3579,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -3612,12 +3594,12 @@ #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8) -#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -3625,9 +3607,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB //// @@ -3639,7 +3621,7 @@ #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -3647,7 +3629,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -3661,7 +3643,7 @@ #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -3669,7 +3651,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -3686,7 +3668,7 @@ #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -3694,7 +3676,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -3703,12 +3685,12 @@ #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) -#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -3716,9 +3698,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2SW3_RING_BASE_LSB //// @@ -3730,7 +3712,7 @@ #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -3738,7 +3720,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -3752,7 +3734,7 @@ #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -3760,7 +3742,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -3777,7 +3759,7 @@ #define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK) #define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ @@ -3785,7 +3767,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 0x8 @@ -3802,7 +3784,7 @@ #define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK) #define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ @@ -3810,7 +3792,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -3827,7 +3809,7 @@ #define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK) #define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ @@ -3835,7 +3817,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -3864,7 +3846,7 @@ #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK) #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -3872,7 +3854,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -3886,7 +3868,7 @@ #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK) #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -3894,7 +3876,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -3908,7 +3890,7 @@ #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -3916,7 +3898,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -3936,7 +3918,7 @@ #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -3944,7 +3926,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -3959,12 +3941,12 @@ #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320) -#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -3972,9 +3954,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB //// @@ -3986,7 +3968,7 @@ #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -3994,7 +3976,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -4008,7 +3990,7 @@ #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -4016,7 +3998,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -4033,7 +4015,7 @@ #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -4041,7 +4023,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -4050,12 +4032,12 @@ #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348) #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348) -#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -4063,9 +4045,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2SW4_RING_BASE_LSB //// @@ -4077,7 +4059,7 @@ #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -4085,7 +4067,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -4099,7 +4081,7 @@ #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -4107,7 +4089,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -4124,7 +4106,7 @@ #define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK) #define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ @@ -4132,7 +4114,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 0x8 @@ -4149,7 +4131,7 @@ #define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK) #define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ @@ -4157,7 +4139,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -4174,7 +4156,7 @@ #define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK) #define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ @@ -4182,7 +4164,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -4211,7 +4193,7 @@ #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK) #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -4219,7 +4201,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -4233,7 +4215,7 @@ #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK) #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -4241,7 +4223,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -4255,7 +4237,7 @@ #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -4263,7 +4245,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -4283,7 +4265,7 @@ #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -4291,7 +4273,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -4306,12 +4288,12 @@ #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000378) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000378) -#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -4319,9 +4301,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB //// @@ -4333,7 +4315,7 @@ #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -4341,7 +4323,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -4355,7 +4337,7 @@ #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -4363,7 +4345,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -4380,7 +4362,7 @@ #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -4388,7 +4370,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -4397,12 +4379,12 @@ #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003a0) #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003a0) -#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -4410,9 +4392,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2TCL_RING_BASE_LSB //// @@ -4424,7 +4406,7 @@ #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -4432,7 +4414,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -4446,7 +4428,7 @@ #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -4454,7 +4436,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -4471,7 +4453,7 @@ #define HWIO_REO_R0_REO2TCL_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK) #define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ @@ -4479,7 +4461,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT 0x8 @@ -4496,7 +4478,7 @@ #define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK) #define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ @@ -4504,7 +4486,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -4521,7 +4503,7 @@ #define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK) #define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ @@ -4529,7 +4511,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -4558,7 +4540,7 @@ #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK) #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -4566,7 +4548,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -4580,7 +4562,7 @@ #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK) #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -4588,7 +4570,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -4602,7 +4584,7 @@ #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -4610,7 +4592,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -4630,7 +4612,7 @@ #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -4638,7 +4620,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -4653,12 +4635,12 @@ #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003d0) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003d0) -#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -4666,9 +4648,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB //// @@ -4680,7 +4662,7 @@ #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -4688,7 +4670,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -4702,7 +4684,7 @@ #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -4710,7 +4692,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -4727,7 +4709,7 @@ #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -4735,7 +4717,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -4744,12 +4726,12 @@ #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003f8) #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003f8) -#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -4757,9 +4739,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO2FW_RING_BASE_LSB //// @@ -4771,7 +4753,7 @@ #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -4779,7 +4761,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -4793,7 +4775,7 @@ #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -4801,7 +4783,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -4818,7 +4800,7 @@ #define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK) #define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ @@ -4826,7 +4808,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 0x8 @@ -4843,7 +4825,7 @@ #define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK) #define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ @@ -4851,7 +4833,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -4868,7 +4850,7 @@ #define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK) #define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ @@ -4876,7 +4858,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -4905,7 +4887,7 @@ #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK) #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -4913,7 +4895,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -4927,7 +4909,7 @@ #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK) #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -4935,7 +4917,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -4949,7 +4931,7 @@ #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -4957,7 +4939,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -4977,7 +4959,7 @@ #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -4985,7 +4967,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -5000,12 +4982,12 @@ #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) -#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -5013,9 +4995,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB //// @@ -5027,7 +5009,7 @@ #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -5035,7 +5017,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -5049,7 +5031,7 @@ #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -5057,7 +5039,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -5074,7 +5056,7 @@ #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -5082,7 +5064,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -5091,12 +5073,12 @@ #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) -#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -5104,9 +5086,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO_RELEASE_RING_BASE_LSB //// @@ -5118,7 +5100,7 @@ #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -5126,7 +5108,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -5140,7 +5122,7 @@ #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -5148,7 +5130,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -5165,7 +5147,7 @@ #define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK) #define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val) #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -5173,7 +5155,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 @@ -5190,7 +5172,7 @@ #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK) #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -5198,7 +5180,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -5215,7 +5197,7 @@ #define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK) #define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -5223,7 +5205,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -5252,7 +5234,7 @@ #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK) #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -5260,7 +5242,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -5274,7 +5256,7 @@ #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK) #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -5282,7 +5264,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -5296,7 +5278,7 @@ #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -5304,7 +5286,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -5324,7 +5306,7 @@ #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -5332,7 +5314,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -5347,12 +5329,12 @@ #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) -#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -5360,21 +5342,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) -#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -5382,9 +5364,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_REO_STATUS_RING_BASE_LSB //// @@ -5396,7 +5378,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -5404,7 +5386,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -5418,7 +5400,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -5426,7 +5408,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -5443,7 +5425,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ @@ -5451,7 +5433,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 0x8 @@ -5468,7 +5450,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ @@ -5476,7 +5458,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -5493,7 +5475,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ @@ -5501,7 +5483,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -5530,7 +5512,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -5538,7 +5520,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -5552,7 +5534,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -5560,7 +5542,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -5574,7 +5556,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -5582,7 +5564,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -5602,7 +5584,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -5610,7 +5592,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -5625,12 +5607,12 @@ #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) -#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -5638,9 +5620,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB //// @@ -5652,7 +5634,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -5660,7 +5642,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -5674,7 +5656,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -5682,7 +5664,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -5699,7 +5681,7 @@ #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -5707,7 +5689,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -5716,12 +5698,12 @@ #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) -#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -5729,21 +5711,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register REO_R0_WATCHDOG_TIMEOUT //// #define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x00000504) #define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x00000504) -#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x0fff0fff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x00000fff #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK) #define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val) #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ @@ -5751,10 +5733,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_REO_R0_WATCHDOG_TIMEOUT_GXI_TIMEOUT_BMSK 0x0fff0000 -#define HWIO_REO_R0_WATCHDOG_TIMEOUT_GXI_TIMEOUT_SHFT 0x10 + } while (0) #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0 @@ -5768,7 +5747,7 @@ #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK) #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val) #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ @@ -5776,7 +5755,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0x0 @@ -5790,7 +5769,7 @@ #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK) #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val) #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ @@ -5798,7 +5777,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0x0 @@ -5812,7 +5791,7 @@ #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK) #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val) #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ @@ -5820,7 +5799,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0x0 @@ -5834,7 +5813,7 @@ #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK) #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val) #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ @@ -5842,7 +5821,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0x0 @@ -5856,7 +5835,7 @@ #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK) #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val) #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ @@ -5864,7 +5843,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0x0 @@ -5878,7 +5857,7 @@ #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ @@ -5886,7 +5865,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0x0 @@ -5900,7 +5879,7 @@ #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ @@ -5908,7 +5887,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0x0 @@ -5922,7 +5901,7 @@ #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ @@ -5930,7 +5909,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0x0 @@ -5944,7 +5923,7 @@ #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ @@ -5952,7 +5931,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0x0 @@ -5966,7 +5945,7 @@ #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ @@ -5974,7 +5953,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0x0 @@ -5988,7 +5967,7 @@ #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ @@ -5996,7 +5975,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0x0 @@ -6010,7 +5989,7 @@ #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ @@ -6018,7 +5997,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0x0 @@ -6032,7 +6011,7 @@ #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ @@ -6040,7 +6019,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0x0 @@ -6054,7 +6033,7 @@ #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ @@ -6062,7 +6041,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0x0 @@ -6076,7 +6055,7 @@ #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ @@ -6084,7 +6063,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0x0 @@ -6098,7 +6077,7 @@ #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ @@ -6106,7 +6085,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0x0 @@ -6120,7 +6099,7 @@ #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ @@ -6128,7 +6107,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0x0 @@ -6142,7 +6121,7 @@ #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ @@ -6150,7 +6129,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0x0 @@ -6164,7 +6143,7 @@ #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ @@ -6172,7 +6151,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0x0 @@ -6186,7 +6165,7 @@ #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ @@ -6194,7 +6173,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0x0 @@ -6208,7 +6187,7 @@ #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ @@ -6216,7 +6195,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0x0 @@ -6230,7 +6209,7 @@ #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ @@ -6238,7 +6217,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0x0000ffff #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0x0 @@ -6252,7 +6231,7 @@ #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ @@ -6260,7 +6239,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0x0000ffff #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0x0 @@ -6274,7 +6253,7 @@ #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ @@ -6282,7 +6261,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0x0000ffff #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0x0 @@ -6296,7 +6275,7 @@ #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ @@ -6304,7 +6283,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0x0000ffff #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0x0 @@ -6318,7 +6297,7 @@ #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ @@ -6326,7 +6305,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0x0 @@ -6340,7 +6319,7 @@ #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ @@ -6348,7 +6327,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0x0 @@ -6362,7 +6341,7 @@ #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ @@ -6370,7 +6349,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0x0 @@ -6384,7 +6363,7 @@ #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ @@ -6392,7 +6371,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0x0 @@ -6406,7 +6385,7 @@ #define HWIO_REO_R0_AGING_CONTROL_IN(x) \ in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK) #define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) #define HWIO_REO_R0_AGING_CONTROL_OUT(x, val) \ out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val) #define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ @@ -6414,7 +6393,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x0000001f #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0x0 @@ -6428,7 +6407,7 @@ #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK) #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val) \ out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val) #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ @@ -6436,7 +6415,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0x0 @@ -6450,7 +6429,7 @@ #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ @@ -6458,7 +6437,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0x0 @@ -6472,7 +6451,7 @@ #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ @@ -6480,7 +6459,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0x0 @@ -6494,7 +6473,7 @@ #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ @@ -6502,7 +6481,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0x0 @@ -6516,7 +6495,7 @@ #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ @@ -6524,7 +6503,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0x0 @@ -6538,7 +6517,7 @@ #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ @@ -6546,7 +6525,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0x0 @@ -6560,7 +6539,7 @@ #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ @@ -6568,7 +6547,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0x0 @@ -6582,7 +6561,7 @@ #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ @@ -6590,7 +6569,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0x0 @@ -6604,7 +6583,7 @@ #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val) \ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ @@ -6612,7 +6591,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0x0 @@ -6626,7 +6605,7 @@ #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ @@ -6634,7 +6613,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0x00ffffff #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0x0 @@ -6648,7 +6627,7 @@ #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ @@ -6656,7 +6635,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0x00ffffff #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0x0 @@ -6670,7 +6649,7 @@ #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ @@ -6678,7 +6657,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0x00ffffff #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0x0 @@ -6692,7 +6671,7 @@ #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val) \ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ @@ -6700,7 +6679,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0x0 @@ -6714,7 +6693,7 @@ #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ @@ -6722,7 +6701,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0x0 @@ -6736,7 +6715,7 @@ #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ @@ -6744,7 +6723,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0x0 @@ -6758,7 +6737,7 @@ #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ @@ -6766,7 +6745,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0x0 @@ -6780,7 +6759,7 @@ #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ @@ -6788,7 +6767,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0x0 @@ -6802,7 +6781,7 @@ #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ @@ -6810,7 +6789,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0x0 @@ -6824,7 +6803,7 @@ #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ @@ -6832,7 +6811,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0x0 @@ -6846,7 +6825,7 @@ #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ @@ -6854,7 +6833,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0x0 @@ -6868,7 +6847,7 @@ #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ @@ -6876,7 +6855,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0x0 @@ -6890,7 +6869,7 @@ #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val) \ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ @@ -6898,7 +6877,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x00000010 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 0x4 @@ -6915,7 +6894,7 @@ #define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK) #define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val) #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ @@ -6923,7 +6902,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 @@ -6937,7 +6916,7 @@ #define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK) #define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val) #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ @@ -6945,7 +6924,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 @@ -6959,7 +6938,7 @@ #define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK) #define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val) #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ @@ -6967,7 +6946,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 @@ -6987,7 +6966,7 @@ #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK) #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ @@ -6995,7 +6974,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 @@ -7009,7 +6988,7 @@ #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK) #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ @@ -7017,7 +6996,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f @@ -7034,7 +7013,7 @@ #define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK) #define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val) #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ @@ -7042,7 +7021,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 @@ -7065,7 +7044,7 @@ #define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK) #define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val) #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ @@ -7073,7 +7052,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 @@ -7093,7 +7072,7 @@ #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ @@ -7101,7 +7080,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 @@ -7124,7 +7103,7 @@ #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK) #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ @@ -7132,7 +7111,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 @@ -7155,7 +7134,7 @@ #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK) #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ @@ -7163,7 +7142,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 @@ -7189,7 +7168,7 @@ #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK) #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ @@ -7197,7 +7176,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 @@ -7214,7 +7193,7 @@ #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK) #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ @@ -7222,7 +7201,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 @@ -7236,7 +7215,7 @@ #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK) #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ @@ -7244,7 +7223,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 @@ -7261,7 +7240,7 @@ #define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK) #define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val) \ out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val) #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ @@ -7269,7 +7248,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x00200000 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 0x15 @@ -7304,7 +7283,7 @@ #define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK) #define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val) \ out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val) #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ @@ -7312,7 +7291,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x00000001 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0x0 @@ -7326,7 +7305,7 @@ #define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK) #define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) #define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val) \ out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val) #define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ @@ -7334,7 +7313,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x00040000 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 0x12 @@ -7375,7 +7354,7 @@ #define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK) #define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) #define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val) #define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ @@ -7383,7 +7362,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0x0 @@ -7397,7 +7376,7 @@ #define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK) #define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) #define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val) #define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ @@ -7405,7 +7384,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0x0 @@ -7419,7 +7398,7 @@ #define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK) #define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) #define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val) #define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ @@ -7427,7 +7406,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0x0 @@ -7441,7 +7420,7 @@ #define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK) #define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) #define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val) #define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ @@ -7449,7 +7428,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0x0 @@ -7463,7 +7442,7 @@ #define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK) #define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val) \ out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val) #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ @@ -7471,7 +7450,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 0x14 @@ -7491,7 +7470,7 @@ #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK) #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val) \ out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val) #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ @@ -7499,7 +7478,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 0xc @@ -7516,7 +7495,7 @@ #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK) #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val) \ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val) #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ @@ -7524,7 +7503,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x00000200 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 0x9 @@ -7547,7 +7526,7 @@ #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK) #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val) \ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val) #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ @@ -7555,7 +7534,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0x0 @@ -7569,7 +7548,7 @@ #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK) #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val) \ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val) #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ @@ -7577,7 +7556,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0x0 @@ -7591,7 +7570,7 @@ #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK) #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val) \ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val) #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ @@ -7599,7 +7578,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0x0 @@ -7613,7 +7592,7 @@ #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK) #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val) \ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val) #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ @@ -7621,7 +7600,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0x03ffffff #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0x0 @@ -7635,7 +7614,7 @@ #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK) #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val) \ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val) #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ @@ -7643,7 +7622,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x01ffffff #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0x0 @@ -7657,7 +7636,7 @@ #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK) #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val) \ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val) #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ @@ -7665,7 +7644,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_BMSK 0xff000000 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_SHFT 0x18 @@ -7688,7 +7667,7 @@ #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK) #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val) \ out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val) #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ @@ -7696,7 +7675,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 @@ -7710,7 +7689,7 @@ #define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK) #define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) #define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val) \ out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val) #define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ @@ -7718,7 +7697,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 @@ -7732,7 +7711,7 @@ #define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK) #define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) #define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val) \ out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val) #define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ @@ -7740,7 +7719,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x00000004 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 0x2 @@ -7760,7 +7739,7 @@ #define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK) #define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) #define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val) \ out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val) #define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ @@ -7768,7 +7747,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x0000007f #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0x0 @@ -7782,7 +7761,7 @@ #define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK) #define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) #define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val) \ out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val) #define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ @@ -7790,7 +7769,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 @@ -7804,7 +7783,7 @@ #define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK) #define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) #define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val) \ out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val) #define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ @@ -7812,7 +7791,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 @@ -7826,7 +7805,7 @@ #define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK) #define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) #define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val) #define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ @@ -7834,7 +7813,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0x0 @@ -7848,7 +7827,7 @@ #define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK) #define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) #define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val) \ out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val) #define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ @@ -7856,7 +7835,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0x0 @@ -7870,7 +7849,7 @@ #define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK) #define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) #define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val) \ out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val) #define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ @@ -7878,7 +7857,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0x0 @@ -7892,7 +7871,7 @@ #define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK) #define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) #define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val) \ out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val) #define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ @@ -7900,7 +7879,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0x0 @@ -7914,7 +7893,7 @@ #define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK) #define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) #define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val) \ out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val) #define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ @@ -7922,7 +7901,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0x0 @@ -7936,7 +7915,7 @@ #define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK) #define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) #define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val) \ out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val) #define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ @@ -7944,7 +7923,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0x0 @@ -7958,7 +7937,7 @@ #define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK) #define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) #define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val) \ out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val) #define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ @@ -7966,7 +7945,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0x0 @@ -7980,7 +7959,7 @@ #define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK) #define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) #define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val) \ out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val) #define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ @@ -7988,7 +7967,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0x0 @@ -8002,7 +7981,7 @@ #define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK) #define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) #define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val) \ out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val) #define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ @@ -8010,7 +7989,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x00060000 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 0x11 @@ -8027,7 +8006,7 @@ #define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK) #define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val) #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ @@ -8035,7 +8014,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8049,7 +8028,7 @@ #define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK) #define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val) #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ @@ -8057,7 +8036,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8071,7 +8050,7 @@ #define HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK) #define HWIO_REO_R2_RXDMA2REO1_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), val) #define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUTM(x, mask, val) \ @@ -8079,7 +8058,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8093,7 +8072,7 @@ #define HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK) #define HWIO_REO_R2_RXDMA2REO1_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), val) #define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUTM(x, mask, val) \ @@ -8101,7 +8080,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8115,7 +8094,7 @@ #define HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK) #define HWIO_REO_R2_RXDMA2REO2_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), val) #define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUTM(x, mask, val) \ @@ -8123,7 +8102,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8137,7 +8116,7 @@ #define HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK) #define HWIO_REO_R2_RXDMA2REO2_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), val) #define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUTM(x, mask, val) \ @@ -8145,7 +8124,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8159,7 +8138,7 @@ #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK) #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ @@ -8167,7 +8146,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8181,7 +8160,7 @@ #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK) #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ @@ -8189,7 +8168,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8203,7 +8182,7 @@ #define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK) #define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val) #define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ @@ -8211,7 +8190,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8225,7 +8204,7 @@ #define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK) #define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val) #define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ @@ -8233,7 +8212,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8247,7 +8226,7 @@ #define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK) #define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val) #define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ @@ -8255,7 +8234,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8269,7 +8248,7 @@ #define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK) #define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val) #define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ @@ -8277,7 +8256,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8291,7 +8270,7 @@ #define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK) #define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val) #define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ @@ -8299,7 +8278,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8313,7 +8292,7 @@ #define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK) #define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val) #define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ @@ -8321,7 +8300,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8335,7 +8314,7 @@ #define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK) #define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val) #define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ @@ -8343,7 +8322,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8357,7 +8336,7 @@ #define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK) #define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val) #define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ @@ -8365,7 +8344,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8379,7 +8358,7 @@ #define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK) #define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val) #define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ @@ -8387,7 +8366,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8401,7 +8380,7 @@ #define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK) #define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val) #define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ @@ -8409,7 +8388,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8423,7 +8402,7 @@ #define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK) #define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val) #define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ @@ -8431,7 +8410,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8445,7 +8424,7 @@ #define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK) #define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val) #define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ @@ -8453,7 +8432,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8467,7 +8446,7 @@ #define HWIO_REO_R2_REO2TCL_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK) #define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val) #define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ @@ -8475,7 +8454,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8489,7 +8468,7 @@ #define HWIO_REO_R2_REO2TCL_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK) #define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val) #define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ @@ -8497,7 +8476,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8511,7 +8490,7 @@ #define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK) #define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val) #define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ @@ -8519,7 +8498,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8533,7 +8512,7 @@ #define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK) #define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val) #define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ @@ -8541,7 +8520,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8555,7 +8534,7 @@ #define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK) #define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val) #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -8563,7 +8542,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8577,7 +8556,7 @@ #define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK) #define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val) #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -8585,7 +8564,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -8599,7 +8578,7 @@ #define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK) #define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) #define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val) #define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ @@ -8607,7 +8586,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 @@ -8621,7 +8600,7 @@ #define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK) #define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) #define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val) \ out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val) #define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ @@ -8629,7 +8608,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 diff --git a/hw/qca8074/v1/rx_msdu_end.h b/hw/qca8074/v1/rx_msdu_end.h index 6a148102f5d3..3210112ebd62 100644 --- a/hw/qca8074/v1/rx_msdu_end.h +++ b/hw/qca8074/v1/rx_msdu_end.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -16,8 +16,6 @@ * PERFORMANCE OF THIS SOFTWARE. */ -// $ATH_LICENSE_HW_HDR_C$ -// // DO NOT EDIT! This file is automatically generated // These definitions are tied to a particular hardware layout @@ -36,11 +34,11 @@ // 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], ext_wapi_pn_63_48[31:16] // 3 ext_wapi_pn_95_64[31:0] // 4 ext_wapi_pn_127_96[31:0] -// 5 reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], reserved_5a[31:26] +// 5 reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], reserved_5a[31:28] // 6 ipv6_options_crc[31:0] // 7 tcp_seq_number[31:0] // 8 tcp_ack_number[31:0] -// 9 tcp_flag[8:0], lro_eligible[9], l3_header_padding[12:10], reserved_9a[15:13], window_size[31:16] +// 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16] // 10 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], type_offset[20:14], reserved_10a[31:21] // 11 rule_indication_31_0[31:0] // 12 rule_indication_63_32[31:0] @@ -80,14 +78,14 @@ struct rx_msdu_end { sa_is_valid : 1, //[23] da_is_valid : 1, //[24] da_is_mcbc : 1, //[25] - reserved_5a : 6; //[31:26] + l3_header_padding : 2, //[27:26] + reserved_5a : 4; //[31:28] uint32_t ipv6_options_crc : 32; //[31:0] uint32_t tcp_seq_number : 32; //[31:0] uint32_t tcp_ack_number : 32; //[31:0] uint32_t tcp_flag : 9, //[8:0] lro_eligible : 1, //[9] - l3_header_padding : 3, //[12:10] - reserved_9a : 3, //[15:13] + reserved_9a : 6, //[15:10] window_size : 16; //[31:16] uint32_t da_offset : 6, //[5:0] sa_offset : 6, //[11:6] @@ -111,193 +109,193 @@ struct rx_msdu_end { /* rxpcu_mpdu_filter_in_category - + Field indicates what the reason was that this MPDU frame was allowed to come into the receive path by RXPCU - + This MPDU passed the normal frame filter programming of rxpcu - + This MPDU did NOT pass the regular frame filter and would have been dropped, were it not for the frame fitting into the 'monitor_client' category. - + This MPDU did NOT pass the regular frame filter and also did not pass the rxpcu_monitor_client filter. It would have been dropped accept that it did pass the 'monitor_other' category. - + sw_frame_group_id - + SW processes frames based on certain classifications. This field indicates to what sw classification this MPDU is mapped. - + The classification is given in priority order - - - - - - - - - - - + + + + + + + + + + + This includes mpdus of type Data Null as well as QoS Data Null - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + This covers type 3 and protocol version != 0 - - - - - - + + + + + + reserved_0 - + phy_ppdu_id - + A ppdu counter value that PHY increments for every PPDU - received. The counter value wraps around - + received. The counter value wraps around + ip_hdr_chksum - + This can include the IP header checksum or the pseudo header checksum used by TCP/UDP checksum. tcp_udp_chksum - + The value of the computed TCP/UDP checksum. A mode bit selects whether this checksum is the full checksum or the - partial checksum which does not include the pseudo header. + partial checksum which does not include the pseudo header. key_id_octet - + The key ID octet from the IV. Only valid when first_msdu is set. cce_super_rule - - Indicates the super filter rule + + Indicates the super filter rule cce_classify_not_done_truncate - + Classification failed due to truncated frame cce_classify_not_done_cce_dis - + Classification failed due to CCE global disable ext_wapi_pn_63_48 - + Extension PN (packet number) which is only used by WAPI. - This corresponds to WAPI PN bits [63:48] (pn6 and pn7). + This corresponds to WAPI PN bits [63:48] (pn6 and pn7). The WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start descriptor. ext_wapi_pn_95_64 - + Extension PN (packet number) which is only used by WAPI. This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 and pn11). ext_wapi_pn_127_96 - + Extension PN (packet number) which is only used by WAPI. This corresponds to WAPI PN bits [127:96] (pn12, pn13, pn14, pn15). reported_mpdu_length - + MPDU length before decapsulation. Only valid when first_msdu is set. This field is taken directly from the length field of the A-MPDU delimiter or the preamble length field for non-A-MPDU frames. first_msdu - + Indicates the first MSDU of A-MSDU. If both first_msdu and last_msdu are set in the MSDU then this is a non-aggregated MSDU frame: normal MPDU. Interior MSDU in an @@ -305,288 +303,291 @@ first_msdu 0. last_msdu - + Indicates the last MSDU of the A-MSDU. MPDU end status is only valid when last_msdu is set. sa_idx_timeout - + Indicates an unsuccessful MAC source address search due to the expiring of the search timer. da_idx_timeout - + Indicates an unsuccessful MAC destination address search due to the expiring of the search timer. msdu_limit_error - + Indicates that the MSDU threshold was exceeded and thus all the rest of the MSDUs will not be scattered and will not be decapsulated but will be DMA'ed in RAW format as a single MSDU buffer flow_idx_timeout - + Indicates an unsuccessful flow search due to the expiring of the search timer. - + flow_idx_invalid - + flow id is not valid - + wifi_parser_error - + TODO: add details to the description - + amsdu_parser_error - + A-MSDU could not be properly de-agregated. - + sa_is_valid - + Indicates that OLE found a valid SA entry da_is_valid - + Indicates that OLE found a valid DA entry da_is_mcbc - + Field Only valid if da_is_valid is set - - - + + + Indicates the DA address was a Multicast of Broadcast address. -reserved_5a - - - -ipv6_options_crc - - 32 bit CRC computed out of IP v6 extension headers - -tcp_seq_number - - TCP sequence number - -tcp_ack_number - - TCP acknowledge number - -tcp_flag - - TCP flags - - {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} - -lro_eligible - - Computed out of TCP and IP fields to indicate that this - MSDU is eligible for LRO - l3_header_padding - + Number of bytes padded to make sure that the L3 header will always start of a Dword boundary +reserved_5a + + + +ipv6_options_crc + + 32 bit CRC computed out of IP v6 extension headers + +tcp_seq_number + + TCP sequence number + +tcp_ack_number + + TCP acknowledge number + +tcp_flag + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} + +lro_eligible + + Computed out of TCP and IP fields to indicate that this + MSDU is eligible for LRO + reserved_9a - + + NOTE: DO not assign a field... Internally used in + RXOLE.. + window_size - + TCP receive window size da_offset - + Offset into MSDU buffer for DA sa_offset - + Offset into MSDU buffer for SA da_offset_valid - + da_offset field is valid. This will be set to 0 in case of a dynamic A-MSDU when DA is compressed sa_offset_valid - + sa_offset field is valid. This will be set to 0 in case of a dynamic A-MSDU when SA is compressed type_offset - + Offset into MSDU buffer for Type reserved_10a - + rule_indication_31_0 - + Bitmap indicating which of rules 31-0 have matched rule_indication_63_32 - + Bitmap indicating which of rules 63-32 have matched sa_idx - + The offset in the address table which matches the MAC source address. da_idx - + The offset in the address table which matches the MAC source address msdu_drop - + When set, REO shall drop this MSDU and not forward it to any other ring... - + reo_destination_indication - + The ID of the REO exit ring where the MSDU frame shall push after (MPDU level) reordering has finished. - - - + + + Reo will push the frame into the REO2TCL ring - + Reo will push the frame into the REO2SW1 ring - + Reo will push the frame into the REO2SW1 ring - + Reo will push the frame into the REO2SW1 ring - + Reo will push the frame into the REO2SW1 ring - + Reo will push the frame into the REO_release ring - + Reo will push the frame into the REO2FW ring - + REO remaps this - + REO remaps this REO remaps this REO remaps this - - REO remaps this - + reo_destination_10> REO remaps this + + REO remaps this + REO remaps this REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - - + reo_destination_13> REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + flow_idx - + Flow table index - + reserved_14 - + fse_metadata - + FSE related meta data: - + cce_metadata - + CCE related meta data: - + sa_sw_peer_id - + sw_peer_id from the address search entry corresponding to the source address of the MSDU - + */ /* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY - + Field indicates what the reason was that this MPDU frame was allowed to come into the receive path by RXPCU - + This MPDU passed the normal frame filter programming of rxpcu - + This MPDU did NOT pass the regular frame filter and would have been dropped, were it not for the frame fitting into the 'monitor_client' category. - + This MPDU did NOT pass the regular frame filter and also did not pass the rxpcu_monitor_client filter. It would have been dropped accept that it did pass the 'monitor_other' category. - + */ #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 @@ -594,104 +595,104 @@ sa_sw_peer_id #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 /* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID - + SW processes frames based on certain classifications. This field indicates to what sw classification this MPDU is mapped. - + The classification is given in priority order - - - - - - - - - - - + + + + + + + + + + + This includes mpdus of type Data Null as well as QoS Data Null - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + This covers type 3 and protocol version != 0 - - - - - - + + + + + + */ #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 @@ -699,7 +700,7 @@ sa_sw_peer_id #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc /* Description RX_MSDU_END_0_RESERVED_0 - + */ #define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 @@ -707,10 +708,10 @@ sa_sw_peer_id #define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 /* Description RX_MSDU_END_0_PHY_PPDU_ID - + A ppdu counter value that PHY increments for every PPDU - received. The counter value wraps around - + received. The counter value wraps around + */ #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 @@ -718,7 +719,7 @@ sa_sw_peer_id #define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 /* Description RX_MSDU_END_1_IP_HDR_CHKSUM - + This can include the IP header checksum or the pseudo header checksum used by TCP/UDP checksum. */ @@ -727,17 +728,17 @@ sa_sw_peer_id #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff /* Description RX_MSDU_END_1_TCP_UDP_CHKSUM - + The value of the computed TCP/UDP checksum. A mode bit selects whether this checksum is the full checksum or the - partial checksum which does not include the pseudo header. + partial checksum which does not include the pseudo header. */ #define RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET 0x00000004 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB 16 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK 0xffff0000 /* Description RX_MSDU_END_2_KEY_ID_OCTET - + The key ID octet from the IV. Only valid when first_msdu is set. */ @@ -746,15 +747,15 @@ sa_sw_peer_id #define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff /* Description RX_MSDU_END_2_CCE_SUPER_RULE - - Indicates the super filter rule + + Indicates the super filter rule */ #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE - + Classification failed due to truncated frame */ #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 @@ -762,7 +763,7 @@ sa_sw_peer_id #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS - + Classification failed due to CCE global disable */ #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 @@ -770,9 +771,9 @@ sa_sw_peer_id #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 /* Description RX_MSDU_END_2_EXT_WAPI_PN_63_48 - + Extension PN (packet number) which is only used by WAPI. - This corresponds to WAPI PN bits [63:48] (pn6 and pn7). + This corresponds to WAPI PN bits [63:48] (pn6 and pn7). The WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start descriptor. */ @@ -781,7 +782,7 @@ sa_sw_peer_id #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_MASK 0xffff0000 /* Description RX_MSDU_END_3_EXT_WAPI_PN_95_64 - + Extension PN (packet number) which is only used by WAPI. This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 and pn11). @@ -791,7 +792,7 @@ sa_sw_peer_id #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_MASK 0xffffffff /* Description RX_MSDU_END_4_EXT_WAPI_PN_127_96 - + Extension PN (packet number) which is only used by WAPI. This corresponds to WAPI PN bits [127:96] (pn12, pn13, pn14, pn15). @@ -801,7 +802,7 @@ sa_sw_peer_id #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_MASK 0xffffffff /* Description RX_MSDU_END_5_REPORTED_MPDU_LENGTH - + MPDU length before decapsulation. Only valid when first_msdu is set. This field is taken directly from the length field of the A-MPDU delimiter or the preamble length @@ -812,7 +813,7 @@ sa_sw_peer_id #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_MASK 0x00003fff /* Description RX_MSDU_END_5_FIRST_MSDU - + Indicates the first MSDU of A-MSDU. If both first_msdu and last_msdu are set in the MSDU then this is a non-aggregated MSDU frame: normal MPDU. Interior MSDU in an @@ -824,7 +825,7 @@ sa_sw_peer_id #define RX_MSDU_END_5_FIRST_MSDU_MASK 0x00004000 /* Description RX_MSDU_END_5_LAST_MSDU - + Indicates the last MSDU of the A-MSDU. MPDU end status is only valid when last_msdu is set. */ @@ -833,7 +834,7 @@ sa_sw_peer_id #define RX_MSDU_END_5_LAST_MSDU_MASK 0x00008000 /* Description RX_MSDU_END_5_SA_IDX_TIMEOUT - + Indicates an unsuccessful MAC source address search due to the expiring of the search timer. */ @@ -842,7 +843,7 @@ sa_sw_peer_id #define RX_MSDU_END_5_SA_IDX_TIMEOUT_MASK 0x00010000 /* Description RX_MSDU_END_5_DA_IDX_TIMEOUT - + Indicates an unsuccessful MAC destination address search due to the expiring of the search timer. */ @@ -851,7 +852,7 @@ sa_sw_peer_id #define RX_MSDU_END_5_DA_IDX_TIMEOUT_MASK 0x00020000 /* Description RX_MSDU_END_5_MSDU_LIMIT_ERROR - + Indicates that the MSDU threshold was exceeded and thus all the rest of the MSDUs will not be scattered and will not be decapsulated but will be DMA'ed in RAW format as a single @@ -862,10 +863,10 @@ sa_sw_peer_id #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_MASK 0x00040000 /* Description RX_MSDU_END_5_FLOW_IDX_TIMEOUT - + Indicates an unsuccessful flow search due to the expiring of the search timer. - + */ #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET 0x00000014 @@ -873,9 +874,9 @@ sa_sw_peer_id #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK 0x00080000 /* Description RX_MSDU_END_5_FLOW_IDX_INVALID - + flow id is not valid - + */ #define RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET 0x00000014 @@ -883,9 +884,9 @@ sa_sw_peer_id #define RX_MSDU_END_5_FLOW_IDX_INVALID_MASK 0x00100000 /* Description RX_MSDU_END_5_WIFI_PARSER_ERROR - + TODO: add details to the description - + */ #define RX_MSDU_END_5_WIFI_PARSER_ERROR_OFFSET 0x00000014 @@ -893,9 +894,9 @@ sa_sw_peer_id #define RX_MSDU_END_5_WIFI_PARSER_ERROR_MASK 0x00200000 /* Description RX_MSDU_END_5_AMSDU_PARSER_ERROR - + A-MSDU could not be properly de-agregated. - + */ #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_OFFSET 0x00000014 @@ -903,7 +904,7 @@ sa_sw_peer_id #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_MASK 0x00400000 /* Description RX_MSDU_END_5_SA_IS_VALID - + Indicates that OLE found a valid SA entry */ #define RX_MSDU_END_5_SA_IS_VALID_OFFSET 0x00000014 @@ -911,7 +912,7 @@ sa_sw_peer_id #define RX_MSDU_END_5_SA_IS_VALID_MASK 0x00800000 /* Description RX_MSDU_END_5_DA_IS_VALID - + Indicates that OLE found a valid DA entry */ #define RX_MSDU_END_5_DA_IS_VALID_OFFSET 0x00000014 @@ -919,11 +920,11 @@ sa_sw_peer_id #define RX_MSDU_END_5_DA_IS_VALID_MASK 0x01000000 /* Description RX_MSDU_END_5_DA_IS_MCBC - + Field Only valid if da_is_valid is set - - - + + + Indicates the DA address was a Multicast of Broadcast address. */ @@ -931,16 +932,25 @@ sa_sw_peer_id #define RX_MSDU_END_5_DA_IS_MCBC_LSB 25 #define RX_MSDU_END_5_DA_IS_MCBC_MASK 0x02000000 +/* Description RX_MSDU_END_5_L3_HEADER_PADDING + + Number of bytes padded to make sure that the L3 header + will always start of a Dword boundary +*/ +#define RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET 0x00000014 +#define RX_MSDU_END_5_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_5_L3_HEADER_PADDING_MASK 0x0c000000 + /* Description RX_MSDU_END_5_RESERVED_5A - + */ #define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 -#define RX_MSDU_END_5_RESERVED_5A_LSB 26 -#define RX_MSDU_END_5_RESERVED_5A_MASK 0xfc000000 +#define RX_MSDU_END_5_RESERVED_5A_LSB 28 +#define RX_MSDU_END_5_RESERVED_5A_MASK 0xf0000000 /* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC - + 32 bit CRC computed out of IP v6 extension headers */ #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 @@ -948,7 +958,7 @@ sa_sw_peer_id #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff /* Description RX_MSDU_END_7_TCP_SEQ_NUMBER - + TCP sequence number */ #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c @@ -956,7 +966,7 @@ sa_sw_peer_id #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff /* Description RX_MSDU_END_8_TCP_ACK_NUMBER - + TCP acknowledge number */ #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 @@ -964,9 +974,9 @@ sa_sw_peer_id #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff /* Description RX_MSDU_END_9_TCP_FLAG - + TCP flags - + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} */ #define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 @@ -974,7 +984,7 @@ sa_sw_peer_id #define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff /* Description RX_MSDU_END_9_LRO_ELIGIBLE - + Computed out of TCP and IP fields to indicate that this MSDU is eligible for LRO */ @@ -982,25 +992,19 @@ sa_sw_peer_id #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 -/* Description RX_MSDU_END_9_L3_HEADER_PADDING - - Number of bytes padded to make sure that the L3 header - will always start of a Dword boundary -*/ -#define RX_MSDU_END_9_L3_HEADER_PADDING_OFFSET 0x00000024 -#define RX_MSDU_END_9_L3_HEADER_PADDING_LSB 10 -#define RX_MSDU_END_9_L3_HEADER_PADDING_MASK 0x00001c00 - /* Description RX_MSDU_END_9_RESERVED_9A - + + NOTE: DO not assign a field... Internally used in + RXOLE.. + */ #define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 -#define RX_MSDU_END_9_RESERVED_9A_LSB 13 -#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000e000 +#define RX_MSDU_END_9_RESERVED_9A_LSB 10 +#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 /* Description RX_MSDU_END_9_WINDOW_SIZE - + TCP receive window size */ #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 @@ -1008,7 +1012,7 @@ sa_sw_peer_id #define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 /* Description RX_MSDU_END_10_DA_OFFSET - + Offset into MSDU buffer for DA */ #define RX_MSDU_END_10_DA_OFFSET_OFFSET 0x00000028 @@ -1016,7 +1020,7 @@ sa_sw_peer_id #define RX_MSDU_END_10_DA_OFFSET_MASK 0x0000003f /* Description RX_MSDU_END_10_SA_OFFSET - + Offset into MSDU buffer for SA */ #define RX_MSDU_END_10_SA_OFFSET_OFFSET 0x00000028 @@ -1024,7 +1028,7 @@ sa_sw_peer_id #define RX_MSDU_END_10_SA_OFFSET_MASK 0x00000fc0 /* Description RX_MSDU_END_10_DA_OFFSET_VALID - + da_offset field is valid. This will be set to 0 in case of a dynamic A-MSDU when DA is compressed */ @@ -1033,7 +1037,7 @@ sa_sw_peer_id #define RX_MSDU_END_10_DA_OFFSET_VALID_MASK 0x00001000 /* Description RX_MSDU_END_10_SA_OFFSET_VALID - + sa_offset field is valid. This will be set to 0 in case of a dynamic A-MSDU when SA is compressed */ @@ -1042,7 +1046,7 @@ sa_sw_peer_id #define RX_MSDU_END_10_SA_OFFSET_VALID_MASK 0x00002000 /* Description RX_MSDU_END_10_TYPE_OFFSET - + Offset into MSDU buffer for Type */ #define RX_MSDU_END_10_TYPE_OFFSET_OFFSET 0x00000028 @@ -1050,7 +1054,7 @@ sa_sw_peer_id #define RX_MSDU_END_10_TYPE_OFFSET_MASK 0x001fc000 /* Description RX_MSDU_END_10_RESERVED_10A - + */ #define RX_MSDU_END_10_RESERVED_10A_OFFSET 0x00000028 @@ -1058,7 +1062,7 @@ sa_sw_peer_id #define RX_MSDU_END_10_RESERVED_10A_MASK 0xffe00000 /* Description RX_MSDU_END_11_RULE_INDICATION_31_0 - + Bitmap indicating which of rules 31-0 have matched */ #define RX_MSDU_END_11_RULE_INDICATION_31_0_OFFSET 0x0000002c @@ -1066,7 +1070,7 @@ sa_sw_peer_id #define RX_MSDU_END_11_RULE_INDICATION_31_0_MASK 0xffffffff /* Description RX_MSDU_END_12_RULE_INDICATION_63_32 - + Bitmap indicating which of rules 63-32 have matched */ #define RX_MSDU_END_12_RULE_INDICATION_63_32_OFFSET 0x00000030 @@ -1074,7 +1078,7 @@ sa_sw_peer_id #define RX_MSDU_END_12_RULE_INDICATION_63_32_MASK 0xffffffff /* Description RX_MSDU_END_13_SA_IDX - + The offset in the address table which matches the MAC source address. */ @@ -1083,7 +1087,7 @@ sa_sw_peer_id #define RX_MSDU_END_13_SA_IDX_MASK 0x0000ffff /* Description RX_MSDU_END_13_DA_IDX - + The offset in the address table which matches the MAC source address */ @@ -1092,10 +1096,10 @@ sa_sw_peer_id #define RX_MSDU_END_13_DA_IDX_MASK 0xffff0000 /* Description RX_MSDU_END_14_MSDU_DROP - + When set, REO shall drop this MSDU and not forward it to any other ring... - + */ #define RX_MSDU_END_14_MSDU_DROP_OFFSET 0x00000038 @@ -1103,82 +1107,82 @@ sa_sw_peer_id #define RX_MSDU_END_14_MSDU_DROP_MASK 0x00000001 /* Description RX_MSDU_END_14_REO_DESTINATION_INDICATION - + The ID of the REO exit ring where the MSDU frame shall push after (MPDU level) reordering has finished. - - - + + + Reo will push the frame into the REO2TCL ring - + Reo will push the frame into the REO2SW1 ring - + Reo will push the frame into the REO2SW1 ring - + Reo will push the frame into the REO2SW1 ring - + Reo will push the frame into the REO2SW1 ring - + Reo will push the frame into the REO_release ring - + Reo will push the frame into the REO2FW ring - + REO remaps this - + REO remaps this REO remaps this REO remaps this - - REO remaps this - + reo_destination_10> REO remaps this + + REO remaps this + REO remaps this REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - REO remaps this - - - + reo_destination_13> REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + */ #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_OFFSET 0x00000038 @@ -1186,9 +1190,9 @@ sa_sw_peer_id #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_MASK 0x0000003e /* Description RX_MSDU_END_14_FLOW_IDX - + Flow table index - + */ #define RX_MSDU_END_14_FLOW_IDX_OFFSET 0x00000038 @@ -1196,7 +1200,7 @@ sa_sw_peer_id #define RX_MSDU_END_14_FLOW_IDX_MASK 0x03ffffc0 /* Description RX_MSDU_END_14_RESERVED_14 - + */ #define RX_MSDU_END_14_RESERVED_14_OFFSET 0x00000038 @@ -1204,9 +1208,9 @@ sa_sw_peer_id #define RX_MSDU_END_14_RESERVED_14_MASK 0xfc000000 /* Description RX_MSDU_END_15_FSE_METADATA - + FSE related meta data: - + */ #define RX_MSDU_END_15_FSE_METADATA_OFFSET 0x0000003c @@ -1214,9 +1218,9 @@ sa_sw_peer_id #define RX_MSDU_END_15_FSE_METADATA_MASK 0xffffffff /* Description RX_MSDU_END_16_CCE_METADATA - + CCE related meta data: - + */ #define RX_MSDU_END_16_CCE_METADATA_OFFSET 0x00000040 @@ -1224,10 +1228,10 @@ sa_sw_peer_id #define RX_MSDU_END_16_CCE_METADATA_MASK 0x0000ffff /* Description RX_MSDU_END_16_SA_SW_PEER_ID - + sw_peer_id from the address search entry corresponding to the source address of the MSDU - + */ #define RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET 0x00000040 diff --git a/hw/qca8074/v1/rx_msdu_start.h b/hw/qca8074/v1/rx_msdu_start.h index 0be1a43d5b6b..bd208f67cb99 100644 --- a/hw/qca8074/v1/rx_msdu_start.h +++ b/hw/qca8074/v1/rx_msdu_start.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -16,8 +16,6 @@ * PERFORMANCE OF THIS SOFTWARE. */ -// $ATH_LICENSE_HW_HDR_C$ -// // DO NOT EDIT! This file is automatically generated // These definitions are tied to a particular hardware layout @@ -33,17 +31,16 @@ // Dword Fields // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] // 1 msdu_length[13:0], reserved_1a[14], ipsec_esp[15], l3_offset[22:16], ipsec_ah[23], l4_offset[31:24] -// 2 msdu_number[7:0], decap_format[9:8], ipv4_proto[10], ipv6_proto[11], tcp_proto[12], udp_proto[13], ip_frag[14], tcp_only_ack[15], reserved_2a[31:16] -// 3 reserved_3a[10:0], da_is_bcast_mcast[11], reserved_3b[15:12], ip4_protocol_ip6_next_header[23:16], reserved_3c[30:24], toeplitz_hash[31] -// 4 toeplitz_hash_2_or_4[31:0] -// 5 flow_id_toeplitz[31:0] -// 6 user_rssi[7:0], pkt_type[11:8], stbc[12], sgi[14:13], rate_mcs[18:15], receive_bandwidth[20:19], reception_type[22:21], nss[25:23], reserved_6[31:26] -// 7 ppdu_start_timestamp[31:0] -// 8 sw_phy_meta_data[31:0] +// 2 msdu_number[7:0], decap_format[9:8], ipv4_proto[10], ipv6_proto[11], tcp_proto[12], udp_proto[13], ip_frag[14], tcp_only_ack[15], da_is_bcast_mcast[16], toeplitz_hash[17], reserved_2a[23:18], ip4_protocol_ip6_next_header[31:24] +// 3 toeplitz_hash_2_or_4[31:0] +// 4 flow_id_toeplitz[31:0] +// 5 user_rssi[7:0], pkt_type[11:8], stbc[12], sgi[14:13], rate_mcs[18:15], receive_bandwidth[20:19], reception_type[22:21], nss[25:23], reserved_5[31:26] +// 6 ppdu_start_timestamp[31:0] +// 7 sw_phy_meta_data[31:0] // // ################ END SUMMARY ################# -#define NUM_OF_DWORDS_RX_MSDU_START 9 +#define NUM_OF_DWORDS_RX_MSDU_START 8 struct rx_msdu_start { uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] @@ -64,13 +61,10 @@ struct rx_msdu_start { udp_proto : 1, //[13] ip_frag : 1, //[14] tcp_only_ack : 1, //[15] - reserved_2a : 16; //[31:16] - uint32_t reserved_3a : 11, //[10:0] - da_is_bcast_mcast : 1, //[11] - reserved_3b : 4, //[15:12] - ip4_protocol_ip6_next_header : 8, //[23:16] - reserved_3c : 7, //[30:24] - toeplitz_hash : 1; //[31] + da_is_bcast_mcast : 1, //[16] + toeplitz_hash : 1, //[17] + reserved_2a : 6, //[23:18] + ip4_protocol_ip6_next_header : 8; //[31:24] uint32_t toeplitz_hash_2_or_4 : 32; //[31:0] uint32_t flow_id_toeplitz : 32; //[31:0] uint32_t user_rssi : 8, //[7:0] @@ -81,7 +75,7 @@ struct rx_msdu_start { receive_bandwidth : 2, //[20:19] reception_type : 2, //[22:21] nss : 3, //[25:23] - reserved_6 : 6; //[31:26] + reserved_5 : 6; //[31:26] uint32_t ppdu_start_timestamp : 32; //[31:0] uint32_t sw_phy_meta_data : 32; //[31:0] }; @@ -89,155 +83,155 @@ struct rx_msdu_start { /* rxpcu_mpdu_filter_in_category - + Field indicates what the reason was that this MPDU frame was allowed to come into the receive path by RXPCU - + This MPDU passed the normal frame filter programming of rxpcu - + This MPDU did NOT pass the regular frame filter and would have been dropped, were it not for the frame fitting into the 'monitor_client' category. - + This MPDU did NOT pass the regular frame filter and also did not pass the rxpcu_monitor_client filter. It would have been dropped accept that it did pass the 'monitor_other' category. - + sw_frame_group_id - + SW processes frames based on certain classifications. This field indicates to what sw classification this MPDU is mapped. - + The classification is given in priority order - - - - - - - - - - - + + + + + + + + + + + This includes mpdus of type Data Null as well as QoS Data Null - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 and protocol version != 0 - - - - - - + + + + + + reserved_0 - + phy_ppdu_id - + A ppdu counter value that PHY increments for every PPDU - received. The counter value wraps around - + received. The counter value wraps around + msdu_length - - MSDU length in bytes after decapsulation. - - - + + MSDU length in bytes after decapsulation. + + + This field is still valid for MPDU frames without reserved_1a - + ipsec_esp - + Set if IPv4/v6 packet is using IPsec ESP l3_offset - + Depending upon mode bit, this field either indicates the L3 offset in bytes from the start of the RX_HEADER or the IP offset in bytes from the start of the packet after @@ -245,11 +239,11 @@ l3_offset ipv6_proto is set. ipsec_ah - + Set if IPv4/v6 packet is using IPsec AH l4_offset - + Depending upon mode bit, this field either indicates the L4 offset nin bytes from the start of RX_HEADER(only valid if either ipv4_proto or ipv6_proto is set to 1) or indicates @@ -259,270 +253,261 @@ l4_offset the offset is longer than 127 bytes. msdu_number - + Indicates the MSDU number within a MPDU. This value is reset to zero at the start of each MPDU. If the number of MSDU exceeds 255 this number will wrap using modulo 256. decap_format - + Indicates the format after decapsulation: - - - + + + No encapsulation - + - - Ethernet 2 (DIX) - - 802.3 (uses SNAP/LLC) - + + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) + + DO NOT USE. Indicate Ethernet + ipv4_proto - + Set if L2 layer indicates IPv4 protocol. ipv6_proto - + Set if L2 layer indicates IPv6 protocol. tcp_proto - + Set if the ipv4_proto or ipv6_proto are set and the IP protocol indicates TCP. udp_proto - + Set if the ipv4_proto or ipv6_proto are set and the IP protocol indicates UDP. ip_frag - + Indicates that either the IP More frag bit is set or IP frag number is non-zero. If set indicates that this is a fragmented IP packet. tcp_only_ack - + Set if only the TCP Ack bit is set in the TCP flags and if the TCP payload is 0. -reserved_2a - - - -reserved_3a - - - da_is_bcast_mcast - + The destination address is broadcast or multicast. -reserved_3b - - - -ip4_protocol_ip6_next_header - - For IPv4 this is the 8 bit protocol field (when - ipv4_proto is set). For IPv6 this is the 8 bit next_header - field (when ipv6_proto is set). - -reserved_3c - - - toeplitz_hash - + Actual choosen Hash. - - - + + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP destination address)1 -> Toeplitz hash of 4-tuple (IP source address, IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP) destination port) +reserved_2a + + + +ip4_protocol_ip6_next_header + + For IPv4 this is the 8 bit protocol field (when + ipv4_proto is set). For IPv6 this is the 8 bit next_header + field (when ipv6_proto is set). + toeplitz_hash_2_or_4 - + Controlled by RxOLE register - If register bit set to 0, Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest addresses; otherwise, toeplitz hash is computed over 4-tuple IPv4 or IPv6 src/dest addresses and src/dest ports flow_id_toeplitz - - Toeplitz hash of 5-tuple - + + Toeplitz hash of 5-tuple + {IP source address, IP destination address, IP source port, IP destination port, L4 protocol} in case of non-IPSec. - - In case of IPSec - Toeplitz hash of 4-tuple - + + In case of IPSec - Toeplitz hash of 4-tuple + {IP source address, IP destination address, SPI, L4 - protocol} - - - + protocol} + + + The relevant Toeplitz key registers are provided in RxOLE's instance of common parser module. These registers are separate from the Toeplitz keys used by ASE/FSE modules inside RxOLE.The actual value will be passed on from common parser module to RxOLE in one of the WHO_* TLVs. - + user_rssi - + RSSI for this user - + pkt_type - + Packet type: - + 802.11a PPDU type - + 802.11b PPDU type - + 802.11n Mixed Mode PPDU type - + 802.11ac PPDU type - + 802.11ax PPDU type stbc - + When set, use STBC transmission rates sgi - + Field only valid when pkt type is HT, VHT or HE. - - - - Legacy normal GI - - Legacy short GI - + + + + Legacy normal GI. Can also be + used for HE + + Legacy short GI. Can also be + used for HE + HE related GI - + HE related GI - + rate_mcs - + For details, refer to MCS_TYPE description - + receive_bandwidth - + Full receive Bandwidth - - - + + + - + - + - - - - - + + + + + reception_type - + Indicates what type of reception this is. - - - - - - - - - + + + + + + + + + nss - + Field only valid when Reception_type = reception_type_MU_MIMO or reception_type_MU_OFDMA_MIMO - - - + + + Number of Spatial Streams occupied by the User - - - + + + Single spatial stream - + 2 spatial streams - + 3 spatial streams - + 4 spatial streams - + 5 spatial streams - + 6 spatial streams - + 7 spatial streams - + 8 spatial streams -reserved_6 - +reserved_5 + ppdu_start_timestamp - + Timestamp that indicates when the PPDU that contained this MPDU started on the medium. - + sw_phy_meta_data - + SW programmed Meta data provided by the PHY. - - - + + + Can be used for SW to indicate the channel the device is on. - + */ /* Description RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY - + Field indicates what the reason was that this MPDU frame was allowed to come into the receive path by RXPCU - + This MPDU passed the normal frame filter programming of rxpcu - + This MPDU did NOT pass the regular frame filter and would have been dropped, were it not for the frame fitting into the 'monitor_client' category. - + This MPDU did NOT pass the regular frame filter and also did not pass the rxpcu_monitor_client filter. It would have been dropped accept that it did pass the 'monitor_other' category. - + */ #define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 @@ -530,104 +515,104 @@ sw_phy_meta_data #define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 /* Description RX_MSDU_START_0_SW_FRAME_GROUP_ID - + SW processes frames based on certain classifications. This field indicates to what sw classification this MPDU is mapped. - + The classification is given in priority order - - - - - - - - - - - + + + + + + + + + + + This includes mpdus of type Data Null as well as QoS Data Null - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 and protocol version != 0 - - - - - - + + + + + + */ #define RX_MSDU_START_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 @@ -635,7 +620,7 @@ sw_phy_meta_data #define RX_MSDU_START_0_SW_FRAME_GROUP_ID_MASK 0x000001fc /* Description RX_MSDU_START_0_RESERVED_0 - + */ #define RX_MSDU_START_0_RESERVED_0_OFFSET 0x00000000 @@ -643,10 +628,10 @@ sw_phy_meta_data #define RX_MSDU_START_0_RESERVED_0_MASK 0x0000fe00 /* Description RX_MSDU_START_0_PHY_PPDU_ID - + A ppdu counter value that PHY increments for every PPDU - received. The counter value wraps around - + received. The counter value wraps around + */ #define RX_MSDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000 @@ -654,11 +639,11 @@ sw_phy_meta_data #define RX_MSDU_START_0_PHY_PPDU_ID_MASK 0xffff0000 /* Description RX_MSDU_START_1_MSDU_LENGTH - - MSDU length in bytes after decapsulation. - - - + + MSDU length in bytes after decapsulation. + + + This field is still valid for MPDU frames without */ #define RX_MSDU_START_1_MSDU_LENGTH_OFFSET 0x00000004 @@ -666,7 +651,7 @@ sw_phy_meta_data #define RX_MSDU_START_1_MSDU_LENGTH_MASK 0x00003fff /* Description RX_MSDU_START_1_RESERVED_1A - + */ #define RX_MSDU_START_1_RESERVED_1A_OFFSET 0x00000004 @@ -674,7 +659,7 @@ sw_phy_meta_data #define RX_MSDU_START_1_RESERVED_1A_MASK 0x00004000 /* Description RX_MSDU_START_1_IPSEC_ESP - + Set if IPv4/v6 packet is using IPsec ESP */ #define RX_MSDU_START_1_IPSEC_ESP_OFFSET 0x00000004 @@ -682,7 +667,7 @@ sw_phy_meta_data #define RX_MSDU_START_1_IPSEC_ESP_MASK 0x00008000 /* Description RX_MSDU_START_1_L3_OFFSET - + Depending upon mode bit, this field either indicates the L3 offset in bytes from the start of the RX_HEADER or the IP offset in bytes from the start of the packet after @@ -694,7 +679,7 @@ sw_phy_meta_data #define RX_MSDU_START_1_L3_OFFSET_MASK 0x007f0000 /* Description RX_MSDU_START_1_IPSEC_AH - + Set if IPv4/v6 packet is using IPsec AH */ #define RX_MSDU_START_1_IPSEC_AH_OFFSET 0x00000004 @@ -702,7 +687,7 @@ sw_phy_meta_data #define RX_MSDU_START_1_IPSEC_AH_MASK 0x00800000 /* Description RX_MSDU_START_1_L4_OFFSET - + Depending upon mode bit, this field either indicates the L4 offset nin bytes from the start of RX_HEADER(only valid if either ipv4_proto or ipv6_proto is set to 1) or indicates @@ -716,7 +701,7 @@ sw_phy_meta_data #define RX_MSDU_START_1_L4_OFFSET_MASK 0xff000000 /* Description RX_MSDU_START_2_MSDU_NUMBER - + Indicates the MSDU number within a MPDU. This value is reset to zero at the start of each MPDU. If the number of MSDU exceeds 255 this number will wrap using modulo 256. @@ -726,32 +711,28 @@ sw_phy_meta_data #define RX_MSDU_START_2_MSDU_NUMBER_MASK 0x000000ff /* Description RX_MSDU_START_2_DECAP_FORMAT - + Indicates the format after decapsulation: - - - + + + No encapsulation - + - - Ethernet 2 (DIX) - - 802.3 (uses SNAP/LLC) - + + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) + + DO NOT USE. Indicate Ethernet + */ -#ifndef RX_MSDU_START_2_DECAP_FORMAT_OFFSET #define RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 -#endif -#ifndef RX_MSDU_START_2_DECAP_FORMAT_LSB #define RX_MSDU_START_2_DECAP_FORMAT_LSB 8 -#endif -#ifndef RX_MSDU_START_2_DECAP_FORMAT_MASK #define RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 -#endif + /* Description RX_MSDU_START_2_IPV4_PROTO - + Set if L2 layer indicates IPv4 protocol. */ #define RX_MSDU_START_2_IPV4_PROTO_OFFSET 0x00000008 @@ -759,7 +740,7 @@ sw_phy_meta_data #define RX_MSDU_START_2_IPV4_PROTO_MASK 0x00000400 /* Description RX_MSDU_START_2_IPV6_PROTO - + Set if L2 layer indicates IPv6 protocol. */ #define RX_MSDU_START_2_IPV6_PROTO_OFFSET 0x00000008 @@ -767,7 +748,7 @@ sw_phy_meta_data #define RX_MSDU_START_2_IPV6_PROTO_MASK 0x00000800 /* Description RX_MSDU_START_2_TCP_PROTO - + Set if the ipv4_proto or ipv6_proto are set and the IP protocol indicates TCP. */ @@ -776,7 +757,7 @@ sw_phy_meta_data #define RX_MSDU_START_2_TCP_PROTO_MASK 0x00001000 /* Description RX_MSDU_START_2_UDP_PROTO - + Set if the ipv4_proto or ipv6_proto are set and the IP protocol indicates UDP. */ @@ -785,7 +766,7 @@ sw_phy_meta_data #define RX_MSDU_START_2_UDP_PROTO_MASK 0x00002000 /* Description RX_MSDU_START_2_IP_FRAG - + Indicates that either the IP More frag bit is set or IP frag number is non-zero. If set indicates that this is a fragmented IP packet. @@ -795,7 +776,7 @@ sw_phy_meta_data #define RX_MSDU_START_2_IP_FRAG_MASK 0x00004000 /* Description RX_MSDU_START_2_TCP_ONLY_ACK - + Set if only the TCP Ack bit is set in the TCP flags and if the TCP payload is 0. */ @@ -803,279 +784,257 @@ sw_phy_meta_data #define RX_MSDU_START_2_TCP_ONLY_ACK_LSB 15 #define RX_MSDU_START_2_TCP_ONLY_ACK_MASK 0x00008000 -/* Description RX_MSDU_START_2_RESERVED_2A - - -*/ -#define RX_MSDU_START_2_RESERVED_2A_OFFSET 0x00000008 -#define RX_MSDU_START_2_RESERVED_2A_LSB 16 -#define RX_MSDU_START_2_RESERVED_2A_MASK 0xffff0000 +/* Description RX_MSDU_START_2_DA_IS_BCAST_MCAST -/* Description RX_MSDU_START_3_RESERVED_3A - - -*/ -#define RX_MSDU_START_3_RESERVED_3A_OFFSET 0x0000000c -#define RX_MSDU_START_3_RESERVED_3A_LSB 0 -#define RX_MSDU_START_3_RESERVED_3A_MASK 0x000007ff - -/* Description RX_MSDU_START_3_DA_IS_BCAST_MCAST - The destination address is broadcast or multicast. */ -#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_OFFSET 0x0000000c -#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_LSB 11 -#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_MASK 0x00000800 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_OFFSET 0x00000008 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_MASK 0x00010000 -/* Description RX_MSDU_START_3_RESERVED_3B - - -*/ -#define RX_MSDU_START_3_RESERVED_3B_OFFSET 0x0000000c -#define RX_MSDU_START_3_RESERVED_3B_LSB 12 -#define RX_MSDU_START_3_RESERVED_3B_MASK 0x0000f000 +/* Description RX_MSDU_START_2_TOEPLITZ_HASH -/* Description RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER - - For IPv4 this is the 8 bit protocol field (when - ipv4_proto is set). For IPv6 this is the 8 bit next_header - field (when ipv6_proto is set). -*/ -#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000c -#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 16 -#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00ff0000 - -/* Description RX_MSDU_START_3_RESERVED_3C - - -*/ -#define RX_MSDU_START_3_RESERVED_3C_OFFSET 0x0000000c -#define RX_MSDU_START_3_RESERVED_3C_LSB 24 -#define RX_MSDU_START_3_RESERVED_3C_MASK 0x7f000000 - -/* Description RX_MSDU_START_3_TOEPLITZ_HASH - Actual choosen Hash. - - - + + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP destination address)1 -> Toeplitz hash of 4-tuple (IP source address, IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP) destination port) */ -#define RX_MSDU_START_3_TOEPLITZ_HASH_OFFSET 0x0000000c -#define RX_MSDU_START_3_TOEPLITZ_HASH_LSB 31 -#define RX_MSDU_START_3_TOEPLITZ_HASH_MASK 0x80000000 +#define RX_MSDU_START_2_TOEPLITZ_HASH_OFFSET 0x00000008 +#define RX_MSDU_START_2_TOEPLITZ_HASH_LSB 17 +#define RX_MSDU_START_2_TOEPLITZ_HASH_MASK 0x00020000 + +/* Description RX_MSDU_START_2_RESERVED_2A + + +*/ +#define RX_MSDU_START_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_MSDU_START_2_RESERVED_2A_LSB 18 +#define RX_MSDU_START_2_RESERVED_2A_MASK 0x00fc0000 + +/* Description RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER + + For IPv4 this is the 8 bit protocol field (when + ipv4_proto is set). For IPv6 this is the 8 bit next_header + field (when ipv6_proto is set). +*/ +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +/* Description RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4 -/* Description RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4 - Controlled by RxOLE register - If register bit set to 0, Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest addresses; otherwise, toeplitz hash is computed over 4-tuple IPv4 or IPv6 src/dest addresses and src/dest ports */ -#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_OFFSET 0x00000010 -#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_LSB 0 -#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +/* Description RX_MSDU_START_4_FLOW_ID_TOEPLITZ + + Toeplitz hash of 5-tuple -/* Description RX_MSDU_START_5_FLOW_ID_TOEPLITZ - - Toeplitz hash of 5-tuple - {IP source address, IP destination address, IP source port, IP destination port, L4 protocol} in case of non-IPSec. - - In case of IPSec - Toeplitz hash of 4-tuple - + + In case of IPSec - Toeplitz hash of 4-tuple + {IP source address, IP destination address, SPI, L4 - protocol} - - - + protocol} + + + The relevant Toeplitz key registers are provided in RxOLE's instance of common parser module. These registers are separate from the Toeplitz keys used by ASE/FSE modules inside RxOLE.The actual value will be passed on from common parser module to RxOLE in one of the WHO_* TLVs. - + */ -#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_OFFSET 0x00000014 -#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_LSB 0 -#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_MASK 0xffffffff +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET 0x00000010 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +/* Description RX_MSDU_START_5_USER_RSSI -/* Description RX_MSDU_START_6_USER_RSSI - RSSI for this user - + */ -#define RX_MSDU_START_6_USER_RSSI_OFFSET 0x00000018 -#define RX_MSDU_START_6_USER_RSSI_LSB 0 -#define RX_MSDU_START_6_USER_RSSI_MASK 0x000000ff +#define RX_MSDU_START_5_USER_RSSI_OFFSET 0x00000014 +#define RX_MSDU_START_5_USER_RSSI_LSB 0 +#define RX_MSDU_START_5_USER_RSSI_MASK 0x000000ff + +/* Description RX_MSDU_START_5_PKT_TYPE -/* Description RX_MSDU_START_6_PKT_TYPE - Packet type: - + 802.11a PPDU type - + 802.11b PPDU type - + 802.11n Mixed Mode PPDU type - + 802.11ac PPDU type - + 802.11ax PPDU type */ -#define RX_MSDU_START_6_PKT_TYPE_OFFSET 0x00000018 -#define RX_MSDU_START_6_PKT_TYPE_LSB 8 -#define RX_MSDU_START_6_PKT_TYPE_MASK 0x00000f00 +#define RX_MSDU_START_5_PKT_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_PKT_TYPE_LSB 8 +#define RX_MSDU_START_5_PKT_TYPE_MASK 0x00000f00 + +/* Description RX_MSDU_START_5_STBC -/* Description RX_MSDU_START_6_STBC - When set, use STBC transmission rates */ -#define RX_MSDU_START_6_STBC_OFFSET 0x00000018 -#define RX_MSDU_START_6_STBC_LSB 12 -#define RX_MSDU_START_6_STBC_MASK 0x00001000 +#define RX_MSDU_START_5_STBC_OFFSET 0x00000014 +#define RX_MSDU_START_5_STBC_LSB 12 +#define RX_MSDU_START_5_STBC_MASK 0x00001000 + +/* Description RX_MSDU_START_5_SGI -/* Description RX_MSDU_START_6_SGI - Field only valid when pkt type is HT, VHT or HE. - - - - Legacy normal GI - - Legacy short GI - + + + + Legacy normal GI. Can also be + used for HE + + Legacy short GI. Can also be + used for HE + HE related GI - + HE related GI - + */ -#define RX_MSDU_START_6_SGI_OFFSET 0x00000018 -#define RX_MSDU_START_6_SGI_LSB 13 -#define RX_MSDU_START_6_SGI_MASK 0x00006000 +#define RX_MSDU_START_5_SGI_OFFSET 0x00000014 +#define RX_MSDU_START_5_SGI_LSB 13 +#define RX_MSDU_START_5_SGI_MASK 0x00006000 + +/* Description RX_MSDU_START_5_RATE_MCS -/* Description RX_MSDU_START_6_RATE_MCS - For details, refer to MCS_TYPE description - + */ -#define RX_MSDU_START_6_RATE_MCS_OFFSET 0x00000018 -#define RX_MSDU_START_6_RATE_MCS_LSB 15 -#define RX_MSDU_START_6_RATE_MCS_MASK 0x00078000 +#define RX_MSDU_START_5_RATE_MCS_OFFSET 0x00000014 +#define RX_MSDU_START_5_RATE_MCS_LSB 15 +#define RX_MSDU_START_5_RATE_MCS_MASK 0x00078000 + +/* Description RX_MSDU_START_5_RECEIVE_BANDWIDTH -/* Description RX_MSDU_START_6_RECEIVE_BANDWIDTH - Full receive Bandwidth - - - + + + - + - + - - - - - + + + + + */ -#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_OFFSET 0x00000018 -#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_LSB 19 -#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_MASK 0x00180000 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB 19 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK 0x00180000 + +/* Description RX_MSDU_START_5_RECEPTION_TYPE -/* Description RX_MSDU_START_6_RECEPTION_TYPE - Indicates what type of reception this is. - - - - - - - - - + + + + + + + + + */ -#define RX_MSDU_START_6_RECEPTION_TYPE_OFFSET 0x00000018 -#define RX_MSDU_START_6_RECEPTION_TYPE_LSB 21 -#define RX_MSDU_START_6_RECEPTION_TYPE_MASK 0x00600000 +#define RX_MSDU_START_5_RECEPTION_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_START_5_RECEPTION_TYPE_MASK 0x00600000 + +/* Description RX_MSDU_START_5_NSS -/* Description RX_MSDU_START_6_NSS - Field only valid when Reception_type = reception_type_MU_MIMO or reception_type_MU_OFDMA_MIMO - - - + + + Number of Spatial Streams occupied by the User - - - + + + Single spatial stream - + 2 spatial streams - + 3 spatial streams - + 4 spatial streams - + 5 spatial streams - + 6 spatial streams - + 7 spatial streams - + 8 spatial streams */ -#define RX_MSDU_START_6_NSS_OFFSET 0x00000018 -#define RX_MSDU_START_6_NSS_LSB 23 -#define RX_MSDU_START_6_NSS_MASK 0x03800000 +#define RX_MSDU_START_5_NSS_OFFSET 0x00000014 +#define RX_MSDU_START_5_NSS_LSB 23 +#define RX_MSDU_START_5_NSS_MASK 0x03800000 + +/* Description RX_MSDU_START_5_RESERVED_5 -/* Description RX_MSDU_START_6_RESERVED_6 - */ -#define RX_MSDU_START_6_RESERVED_6_OFFSET 0x00000018 -#define RX_MSDU_START_6_RESERVED_6_LSB 26 -#define RX_MSDU_START_6_RESERVED_6_MASK 0xfc000000 +#define RX_MSDU_START_5_RESERVED_5_OFFSET 0x00000014 +#define RX_MSDU_START_5_RESERVED_5_LSB 26 +#define RX_MSDU_START_5_RESERVED_5_MASK 0xfc000000 + +/* Description RX_MSDU_START_6_PPDU_START_TIMESTAMP -/* Description RX_MSDU_START_7_PPDU_START_TIMESTAMP - Timestamp that indicates when the PPDU that contained this MPDU started on the medium. - + */ -#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_OFFSET 0x0000001c -#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_LSB 0 -#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_MASK 0xffffffff +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_OFFSET 0x00000018 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_LSB 0 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_MASK 0xffffffff + +/* Description RX_MSDU_START_7_SW_PHY_META_DATA -/* Description RX_MSDU_START_8_SW_PHY_META_DATA - SW programmed Meta data provided by the PHY. - - - + + + Can be used for SW to indicate the channel the device is on. - + */ -#define RX_MSDU_START_8_SW_PHY_META_DATA_OFFSET 0x00000020 -#define RX_MSDU_START_8_SW_PHY_META_DATA_LSB 0 -#define RX_MSDU_START_8_SW_PHY_META_DATA_MASK 0xffffffff +#define RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET 0x0000001c +#define RX_MSDU_START_7_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_7_SW_PHY_META_DATA_MASK 0xffffffff #endif // _RX_MSDU_START_H_ diff --git a/hw/qca8074/v1/seq_hwio.h b/hw/qca8074/v1/seq_hwio.h index fd489f20d8a1..0ecce75ec6fc 100644 --- a/hw/qca8074/v1/seq_hwio.h +++ b/hw/qca8074/v1/seq_hwio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -22,7 +22,7 @@ * - This is an extension of standard msmhwio.h to support relative addressing * scheme used in SCALe auto-generated sequences. * - The objective of this new addressing scheme is enable the same C function - * definition to be applicable to multiple baseances of the same block. + * definition to be applicable to multiple baseances of the same block. * - Such code reuse is not feasible with the standard HWIO macros that use a * absolute addressing scheme. * - Compared to the standard HWIO macros, the new macros defined here take an @@ -93,11 +93,11 @@ typedef enum { NS } SEQ_TimeUnit; -extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); +void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); /************ seq_poll() ************/ -extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); +uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); #endif /* __SEQ_H__ */ diff --git a/hw/qca8074/v1/sw_xml_headers.h b/hw/qca8074/v1/sw_xml_headers.h index f263386f85be..14dd0c9929ea 100644 --- a/hw/qca8074/v1/sw_xml_headers.h +++ b/hw/qca8074/v1/sw_xml_headers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -16,7 +16,6 @@ * PERFORMANCE OF THIS SOFTWARE. */ -// // DO NOT EDIT! This file is automatically generated // These definitions are tied to a particular hardware layout @@ -28,7 +27,9 @@ #include "addr_search_entry.h" #include "buffer_addr_info.h" #include "cce_rule.h" +#include "ce_dst_desc.h" #include "ce_src_desc.h" +#include "ce_stat_desc.h" #include "he_sig_a_mu_dl_info.h" #include "he_sig_a_mu_ul_info.h" #include "he_sig_a_su_info.h" @@ -125,7 +126,6 @@ #include "who_classify_info.h" #include "macrx_abort_request_info.h" #include "phytx_abort_request_info.h" -#include "ce_stat_desc.h" #include "coex_mac_nap.h" #include "coex_rx_status.h" #include "coex_status_broadcast.h" @@ -139,6 +139,7 @@ #include "mactx_bf_params_common.h" #include "mactx_coex_phy_ctrl.h" #include "mactx_delete_cv.h" +#include "mactx_expect_cbf_common.h" #include "mactx_he_sig_a_mu_dl.h" #include "mactx_he_sig_a_mu_ul.h" #include "mactx_he_sig_a_su.h" @@ -275,7 +276,6 @@ #include "who_terminate.h" #include "data_to_time_config.h" #include "mactx_bf_params_per_user.h" -#include "mactx_expect_cbf_common.h" #include "mactx_expect_cbf_per_user.h" #include "mactx_mu_uplink_user_setup.h" #include "mactx_service.h" @@ -312,7 +312,6 @@ #include "tqm_acked_mpdu.h" #include "tqm_update_tx_mpdu_count.h" #include "tx_11ah_setup.h" -#include "tx_cv_start.h" #include "tx_fes_status_ack_or_ba.h" #include "tx_fes_status_user_ppdu.h" #include "tx_fes_status_user_response.h" diff --git a/hw/qca8074/v1/tlv_tag_def.h b/hw/qca8074/v1/tlv_tag_def.h index ca0c5aff3037..cff31fde8698 100644 --- a/hw/qca8074/v1/tlv_tag_def.h +++ b/hw/qca8074/v1/tlv_tag_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -178,7 +178,7 @@ typedef enum { WIFIMPDU_INFO_E = 150 /* 0x96 */, WIFIPDG_USER_SETUP_E = 151 /* 0x97 */, WIFITX_11AH_SETUP_E = 152 /* 0x98 */, - WIFITX_CV_START_E = 153 /* 0x99 */, + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 153 /* 0x99 */, WIFITX_PEER_ENTRY_E = 154 /* 0x9a */, WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 /* 0x9b */, WIFIEXAMPLE_STRUCT_NAME_E = 156 /* 0x9c */, @@ -445,7 +445,7 @@ typedef enum { WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 /* 0x1a1 */, WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 /* 0x1a2 */, WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 /* 0x1a3 */, - WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 420 /* 0x1a4 */, + WIFICE_DST_DESC_E = 420 /* 0x1a4 */, WIFITLV_BASE_E = 511 /* 0x1ff */ } tlv_tag_def__e; ///< tlv_tag_def Enum Type diff --git a/hw/qca8074/v1/wbm_reg_seq_hwioreg.h b/hw/qca8074/v1/wbm_reg_seq_hwioreg.h index 600376c48c60..54222aa11b21 100644 --- a/hw/qca8074/v1/wbm_reg_seq_hwioreg.h +++ b/hw/qca8074/v1/wbm_reg_seq_hwioreg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,7 +18,7 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// wbm_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// wbm_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 2/3/2017 // User Name:pgohil // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. @@ -50,7 +50,7 @@ #define HWIO_WBM_R0_GENERAL_ENABLE_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), HWIO_WBM_R0_GENERAL_ENABLE_RMSK) #define HWIO_WBM_R0_GENERAL_ENABLE_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask) #define HWIO_WBM_R0_GENERAL_ENABLE_OUT(x, val) \ out_dword( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), val) #define HWIO_WBM_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ @@ -58,7 +58,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_GENERAL_ENABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x00000080 #define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 0x7 @@ -93,7 +93,7 @@ #define HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK) #define HWIO_WBM_R0_RELEASE_RING_ENABLE_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask) #define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUT(x, val) \ out_dword( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), val) #define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUTM(x, mask, val) \ @@ -101,7 +101,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RELEASE_RING_ENABLE_VALUE_BMSK 0x000000ff #define HWIO_WBM_R0_RELEASE_RING_ENABLE_VALUE_SHFT 0x0 @@ -115,7 +115,7 @@ #define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x) \ in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK) #define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask) #define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUT(x, val) \ out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), val) #define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUTM(x, mask, val) \ @@ -123,7 +123,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_VALUE_BMSK 0x0000003f #define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_VALUE_SHFT 0x0 @@ -137,7 +137,7 @@ #define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x) \ in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK) #define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask) #define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUT(x, val) \ out_dword( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), val) #define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUTM(x, mask, val) \ @@ -145,7 +145,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_VALUE_BMSK 0x0000007f #define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_VALUE_SHFT 0x0 @@ -159,7 +159,7 @@ #define HWIO_WBM_R0_MISC_RING_ENABLE_IN(x) \ in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MISC_RING_ENABLE_RMSK) #define HWIO_WBM_R0_MISC_RING_ENABLE_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask) #define HWIO_WBM_R0_MISC_RING_ENABLE_OUT(x, val) \ out_dword( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), val) #define HWIO_WBM_R0_MISC_RING_ENABLE_OUTM(x, mask, val) \ @@ -167,7 +167,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_ENABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW3_BUFFER_RING_BMSK 0x00000010 #define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW3_BUFFER_RING_SHFT 0x4 @@ -193,7 +193,7 @@ #define HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -201,7 +201,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RELEASE_RING_STATUS_RELEASE_RING_NOT_IDLE_BMSK 0x000000ff #define HWIO_WBM_R0_RELEASE_RING_STATUS_RELEASE_RING_NOT_IDLE_SHFT 0x0 @@ -215,7 +215,7 @@ #define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK) #define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUTM(x, mask, val) \ @@ -223,7 +223,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_MSDU_BUFFER_RING_NOT_IDLE_BMSK 0x0000003f #define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_MSDU_BUFFER_RING_NOT_IDLE_SHFT 0x0 @@ -237,7 +237,7 @@ #define HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK) #define HWIO_WBM_R0_LINK_DESC_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUTM(x, mask, val) \ @@ -245,7 +245,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_LINK_DESC_RING_STATUS_LINK_DESC_RING_NOT_IDLE_BMSK 0x0000007f #define HWIO_WBM_R0_LINK_DESC_RING_STATUS_LINK_DESC_RING_NOT_IDLE_SHFT 0x0 @@ -259,7 +259,7 @@ #define HWIO_WBM_R0_MISC_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), HWIO_WBM_R0_MISC_RING_STATUS_RMSK) #define HWIO_WBM_R0_MISC_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_MISC_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_MISC_RING_STATUS_OUTM(x, mask, val) \ @@ -267,7 +267,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_BMSK 0x00000100 #define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_SHFT 0x8 @@ -305,7 +305,7 @@ #define HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK) #define HWIO_WBM_R0_RELEASE_RING_FLUSH_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask) #define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUT(x, val) \ out_dword( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), val) #define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUTM(x, mask, val) \ @@ -313,7 +313,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_BMSK 0x00010000 #define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_SHFT 0x10 @@ -336,7 +336,7 @@ #define HWIO_WBM_R0_IDLE_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), HWIO_WBM_R0_IDLE_STATUS_RMSK) #define HWIO_WBM_R0_IDLE_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_IDLE_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), val) #define HWIO_WBM_R0_IDLE_STATUS_OUTM(x, mask, val) \ @@ -344,7 +344,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_BMSK 0x00004000 #define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_SHFT 0xe @@ -400,7 +400,7 @@ #define HWIO_WBM_R0_IDLE_SEQUENCE_IN(x) \ in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), HWIO_WBM_R0_IDLE_SEQUENCE_RMSK) #define HWIO_WBM_R0_IDLE_SEQUENCE_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask) #define HWIO_WBM_R0_IDLE_SEQUENCE_OUT(x, val) \ out_dword( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), val) #define HWIO_WBM_R0_IDLE_SEQUENCE_OUTM(x, mask, val) \ @@ -408,7 +408,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_SEQUENCE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_BMSK 0x00000020 #define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_SHFT 0x5 @@ -428,7 +428,7 @@ #define HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x) \ in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK) #define HWIO_WBM_R0_MSDU_PARSER_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask) #define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUT(x, val) \ out_dword( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), val) #define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUTM(x, mask, val) \ @@ -436,7 +436,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_BMSK 0x00000004 #define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_SHFT 0x2 @@ -451,12 +451,12 @@ #define HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x) (x+0x00000034) #define HWIO_WBM_R0_MSDU_PARSER_STATUS_PHYS(x) (x+0x00000034) -#define HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK 0x0007ffff +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK 0x000fffff #define HWIO_WBM_R0_MSDU_PARSER_STATUS_SHFT 0 #define HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK) #define HWIO_WBM_R0_MSDU_PARSER_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), val) #define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUTM(x, mask, val) \ @@ -464,7 +464,10 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_BMSK 0x00080000 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_SHFT 0x13 #define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK 0x00078000 #define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT 0xf @@ -490,7 +493,7 @@ #define HWIO_WBM_R0_MISC_CONTROL_IN(x) \ in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_MISC_CONTROL_RMSK) #define HWIO_WBM_R0_MISC_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask) #define HWIO_WBM_R0_MISC_CONTROL_OUT(x, val) \ out_dword( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), val) #define HWIO_WBM_R0_MISC_CONTROL_OUTM(x, mask, val) \ @@ -498,7 +501,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MISC_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0x0000fffc #define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2 @@ -518,7 +521,7 @@ #define HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK) #define HWIO_WBM_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) #define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ out_dword( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), val) #define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ @@ -526,7 +529,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_BMSK 0x00000fff #define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_SHFT 0x0 @@ -540,7 +543,7 @@ #define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x) \ in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK) #define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask) #define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUT(x, val) \ out_dword( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), val) #define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUTM(x, mask, val) \ @@ -548,7 +551,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask, val, HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_MSDU_PARSER_ERROR_1_DATA_BMSK 0x000001ff #define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_MSDU_PARSER_ERROR_1_DATA_SHFT 0x0 @@ -562,7 +565,7 @@ #define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x) \ in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK) #define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) #define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ out_dword( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) #define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ @@ -570,7 +573,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_BMSK 0x0001ffff #define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_SHFT 0x0 @@ -584,7 +587,7 @@ #define HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x) \ in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK) #define HWIO_WBM_R0_IDLE_LIST_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask) #define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUT(x, val) \ out_dword( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), val) #define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUTM(x, mask, val) \ @@ -592,7 +595,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x000007fc #define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 0x2 @@ -612,7 +615,7 @@ #define HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x) \ in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK) #define HWIO_WBM_R0_IDLE_LIST_SIZE_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask) #define HWIO_WBM_R0_IDLE_LIST_SIZE_OUT(x, val) \ out_dword( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), val) #define HWIO_WBM_R0_IDLE_LIST_SIZE_OUTM(x, mask, val) \ @@ -620,7 +623,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 #define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 0x10 @@ -637,7 +640,7 @@ #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_RMSK) #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUTM(x, mask, val) \ @@ -645,7 +648,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0x0 @@ -659,7 +662,7 @@ #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_RMSK) #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUTM(x, mask, val) \ @@ -667,7 +670,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 #define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 0x8 @@ -684,7 +687,7 @@ #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUTM(x, mask, val) \ @@ -692,7 +695,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0x0 @@ -706,7 +709,7 @@ #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUTM(x, mask, val) \ @@ -714,7 +717,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 0x8 @@ -731,7 +734,7 @@ #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_RMSK) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \ @@ -739,7 +742,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 @@ -753,7 +756,7 @@ #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_RMSK) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \ @@ -761,7 +764,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00 #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 0x8 @@ -778,7 +781,7 @@ #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \ @@ -786,7 +789,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 @@ -800,7 +803,7 @@ #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \ @@ -808,7 +811,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 0x8 @@ -825,7 +828,7 @@ #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_RMSK) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \ @@ -833,7 +836,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 @@ -847,7 +850,7 @@ #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_RMSK) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \ @@ -855,7 +858,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00 #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 0x8 @@ -872,7 +875,7 @@ #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \ @@ -880,7 +883,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 @@ -894,7 +897,7 @@ #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \ @@ -902,7 +905,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 0x8 @@ -919,7 +922,7 @@ #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_RMSK) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUTM(x, mask, val) \ @@ -927,7 +930,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_BMSK 0x000fffff #define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_SHFT 0x0 @@ -941,7 +944,7 @@ #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUTM(x, mask, val) \ @@ -949,7 +952,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_BMSK 0x000fffff #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_SHFT 0x0 @@ -963,7 +966,7 @@ #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_RMSK) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUTM(x, mask, val) \ @@ -971,7 +974,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_BMSK 0x000fffff #define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_SHFT 0x0 @@ -985,7 +988,7 @@ #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUT(x, val) \ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), val) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUTM(x, mask, val) \ @@ -993,7 +996,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_BMSK 0x000fffff #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_SHFT 0x0 @@ -1007,7 +1010,7 @@ #define HWIO_WBM_R0_CLK_GATE_CTRL_IN(x) \ in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), HWIO_WBM_R0_CLK_GATE_CTRL_RMSK) #define HWIO_WBM_R0_CLK_GATE_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask) #define HWIO_WBM_R0_CLK_GATE_CTRL_OUT(x, val) \ out_dword( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), val) #define HWIO_WBM_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ @@ -1015,7 +1018,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_WBM_R0_CLK_GATE_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_BMSK 0x00020000 #define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_SHFT 0x11 @@ -1035,7 +1038,7 @@ #define HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_LOWER_RMSK) #define HWIO_WBM_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) #define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), val) #define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ @@ -1043,7 +1046,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 @@ -1057,7 +1060,7 @@ #define HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_UPPER_RMSK) #define HWIO_WBM_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) #define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), val) #define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ @@ -1065,7 +1068,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff #define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 @@ -1079,7 +1082,7 @@ #define HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R0_GXI_SM_STATES_IX_0_RMSK) #define HWIO_WBM_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) #define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), val) #define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ @@ -1087,7 +1090,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 #define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 @@ -1107,7 +1110,7 @@ #define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_RMSK) #define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) #define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) #define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ @@ -1115,7 +1118,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 @@ -1129,7 +1132,7 @@ #define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RMSK) #define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) #define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) #define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ @@ -1137,7 +1140,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 #define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f @@ -1154,7 +1157,7 @@ #define HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_INTS_RMSK) #define HWIO_WBM_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) #define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), val) #define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ @@ -1162,7 +1165,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 #define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 @@ -1185,7 +1188,7 @@ #define HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_STATS_RMSK) #define HWIO_WBM_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) #define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), val) #define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ @@ -1193,7 +1196,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 #define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 @@ -1213,7 +1216,7 @@ #define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) #define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) #define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) #define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ @@ -1221,7 +1224,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 #define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 @@ -1244,7 +1247,7 @@ #define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_RMSK) #define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) #define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) #define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ @@ -1252,7 +1255,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 #define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 @@ -1275,7 +1278,7 @@ #define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_RMSK) #define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) #define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) #define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ @@ -1283,7 +1286,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 #define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 @@ -1309,7 +1312,7 @@ #define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_RMSK) #define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) #define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) #define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ @@ -1317,7 +1320,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 #define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 @@ -1334,7 +1337,7 @@ #define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_RMSK) #define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) #define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ @@ -1342,7 +1345,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff #define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 @@ -1356,7 +1359,7 @@ #define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_RMSK) #define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) #define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ out_dword( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) #define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ @@ -1364,7 +1367,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 #define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 @@ -1381,7 +1384,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -1389,7 +1392,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -1403,7 +1406,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -1411,7 +1414,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -1423,12 +1426,12 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x) (x+0x000000d0) #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_PHYS(x) (x+0x000000d0) -#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -1436,10 +1439,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1453,7 +1453,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -1461,7 +1461,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -1478,7 +1478,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -1486,7 +1486,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -1515,7 +1515,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -1523,7 +1523,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -1537,7 +1537,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -1545,7 +1545,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -1559,7 +1559,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -1567,7 +1567,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -1587,7 +1587,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -1595,7 +1595,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -1609,7 +1609,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -1617,7 +1617,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -1632,12 +1632,12 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000104) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000104) -#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -1645,9 +1645,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -1659,7 +1659,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -1667,7 +1667,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -1681,7 +1681,7 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -1689,7 +1689,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -1701,12 +1701,12 @@ #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000011c) #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000011c) -#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -1714,9 +1714,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_TQM_RELEASE_RING_BASE_LSB //// @@ -1728,7 +1728,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -1736,7 +1736,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -1750,7 +1750,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -1758,7 +1758,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -1770,12 +1770,12 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x) (x+0x00000128) #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_PHYS(x) (x+0x00000128) -#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -1783,10 +1783,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1800,7 +1797,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -1808,7 +1805,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -1825,7 +1822,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -1833,7 +1830,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -1862,7 +1859,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -1870,7 +1867,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -1884,7 +1881,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -1892,7 +1889,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -1906,7 +1903,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -1914,7 +1911,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -1934,7 +1931,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -1942,7 +1939,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -1956,7 +1953,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -1964,7 +1961,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -1979,12 +1976,12 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000015c) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000015c) -#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -1992,9 +1989,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -2006,7 +2003,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -2014,7 +2011,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -2028,7 +2025,7 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -2036,7 +2033,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -2048,12 +2045,12 @@ #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000174) #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000174) -#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -2061,9 +2058,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_REO_RELEASE_RING_BASE_LSB //// @@ -2075,7 +2072,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -2083,7 +2080,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -2097,7 +2094,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -2105,7 +2102,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -2117,12 +2114,12 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x00000180) #define HWIO_WBM_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x00000180) -#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_REO_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -2130,10 +2127,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2147,7 +2141,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -2155,7 +2149,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -2172,7 +2166,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -2180,7 +2174,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -2209,7 +2203,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -2217,7 +2211,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -2231,7 +2225,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -2239,7 +2233,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -2253,7 +2247,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -2261,7 +2255,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -2281,7 +2275,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -2289,7 +2283,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -2303,7 +2297,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -2311,7 +2305,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -2326,12 +2320,12 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001b4) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001b4) -#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -2339,9 +2333,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -2353,7 +2347,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -2361,7 +2355,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -2375,7 +2369,7 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -2383,7 +2377,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -2395,12 +2389,12 @@ #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001cc) #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001cc) -#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -2408,9 +2402,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_SW_RELEASE_RING_BASE_LSB //// @@ -2422,7 +2416,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -2430,7 +2424,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -2444,7 +2438,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -2452,7 +2446,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -2464,12 +2458,12 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x) (x+0x000001d8) #define HWIO_WBM_R0_SW_RELEASE_RING_ID_PHYS(x) (x+0x000001d8) -#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_SW_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -2477,10 +2471,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2494,7 +2485,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -2502,7 +2493,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -2519,7 +2510,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -2527,7 +2518,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -2556,7 +2547,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -2564,7 +2555,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -2578,7 +2569,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -2586,7 +2577,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -2600,7 +2591,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -2608,7 +2599,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -2628,7 +2619,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -2636,7 +2627,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -2650,7 +2641,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -2658,7 +2649,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -2673,12 +2664,12 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000020c) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000020c) -#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -2686,9 +2677,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -2700,7 +2691,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -2708,7 +2699,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -2722,7 +2713,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -2730,7 +2721,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -2747,7 +2738,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -2755,7 +2746,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -2769,7 +2760,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -2777,7 +2768,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -2794,7 +2785,7 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -2802,7 +2793,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -2811,12 +2802,12 @@ #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000224) #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000224) -#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -2824,9 +2815,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_FW_RELEASE_RING_BASE_LSB //// @@ -2838,7 +2829,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -2846,7 +2837,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -2860,7 +2851,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -2868,7 +2859,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -2880,12 +2871,12 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x) (x+0x00000230) #define HWIO_WBM_R0_FW_RELEASE_RING_ID_PHYS(x) (x+0x00000230) -#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_FW_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -2893,10 +2884,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -2910,7 +2898,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -2918,7 +2906,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -2935,7 +2923,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -2943,7 +2931,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -2972,7 +2960,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -2980,7 +2968,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -2994,7 +2982,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -3002,7 +2990,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -3016,7 +3004,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -3024,7 +3012,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -3044,7 +3032,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -3052,7 +3040,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -3066,7 +3054,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -3074,7 +3062,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -3089,12 +3077,12 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000264) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000264) -#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -3102,9 +3090,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -3116,7 +3104,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -3124,7 +3112,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -3138,7 +3126,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -3146,7 +3134,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -3163,7 +3151,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -3171,7 +3159,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -3185,7 +3173,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -3193,7 +3181,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -3210,7 +3198,7 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -3218,7 +3206,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -3227,12 +3215,12 @@ #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000027c) #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000027c) -#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -3240,9 +3228,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB //// @@ -3254,7 +3242,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -3262,7 +3250,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -3276,7 +3264,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -3284,7 +3272,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -3296,12 +3284,12 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x) (x+0x00000288) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_PHYS(x) (x+0x00000288) -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -3309,10 +3297,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -3326,7 +3311,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -3334,7 +3319,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -3351,7 +3336,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -3359,7 +3344,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -3388,7 +3373,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -3396,7 +3381,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -3410,7 +3395,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -3418,7 +3403,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -3432,7 +3417,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -3440,7 +3425,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -3460,7 +3445,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -3468,7 +3453,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -3482,7 +3467,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -3490,7 +3475,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -3505,12 +3490,12 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000002bc) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000002bc) -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -3518,9 +3503,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -3532,7 +3517,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -3540,7 +3525,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -3554,7 +3539,7 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -3562,7 +3547,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -3574,12 +3559,12 @@ #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002d4) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002d4) -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -3587,9 +3572,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB //// @@ -3601,7 +3586,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -3609,7 +3594,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -3623,7 +3608,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -3631,7 +3616,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -3643,12 +3628,12 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x) (x+0x000002e0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_PHYS(x) (x+0x000002e0) -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -3656,10 +3641,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -3673,7 +3655,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -3681,7 +3663,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -3698,7 +3680,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -3706,7 +3688,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -3735,7 +3717,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -3743,7 +3725,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -3757,7 +3739,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -3765,7 +3747,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -3779,7 +3761,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -3787,7 +3769,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -3807,7 +3789,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -3815,7 +3797,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -3829,7 +3811,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -3837,7 +3819,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -3852,12 +3834,12 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000314) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000314) -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -3865,9 +3847,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -3879,7 +3861,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -3887,7 +3869,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -3901,7 +3883,7 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -3909,7 +3891,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -3921,12 +3903,12 @@ #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000032c) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000032c) -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -3934,9 +3916,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB //// @@ -3948,7 +3930,7 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -3956,7 +3938,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -3970,7 +3952,7 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -3978,7 +3960,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -3990,12 +3972,12 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x) (x+0x00000338) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_PHYS(x) (x+0x00000338) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RMSK 0x000000ff #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_SHFT 0 #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -4003,10 +3985,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -4020,7 +3999,7 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -4028,7 +4007,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -4045,7 +4024,7 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -4053,7 +4032,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -4082,7 +4061,7 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -4090,7 +4069,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -4104,7 +4083,7 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -4112,7 +4091,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -4126,7 +4105,7 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -4134,7 +4113,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -4154,7 +4133,7 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -4162,7 +4141,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -4176,7 +4155,7 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -4184,7 +4163,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -4199,12 +4178,12 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000036c) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000036c) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -4212,9 +4191,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// @@ -4226,7 +4205,7 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -4234,7 +4213,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -4248,7 +4227,7 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -4256,7 +4235,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -4268,12 +4247,12 @@ #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000384) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000384) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -4281,9 +4260,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2PPE_BUF_RING_BASE_LSB //// @@ -4295,7 +4274,7 @@ #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -4303,7 +4282,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -4317,7 +4296,7 @@ #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -4325,7 +4304,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -4342,7 +4321,7 @@ #define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUTM(x, mask, val) \ @@ -4350,7 +4329,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_SHFT 0x8 @@ -4367,7 +4346,7 @@ #define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUTM(x, mask, val) \ @@ -4375,7 +4354,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -4392,7 +4371,7 @@ #define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUTM(x, mask, val) \ @@ -4400,7 +4379,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -4429,7 +4408,7 @@ #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -4437,7 +4416,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -4451,7 +4430,7 @@ #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -4459,7 +4438,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -4473,7 +4452,7 @@ #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -4481,7 +4460,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -4501,7 +4480,7 @@ #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -4509,7 +4488,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -4524,12 +4503,12 @@ #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003b4) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003b4) -#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -4537,21 +4516,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003dc) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003dc) -#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -4559,9 +4538,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW_BUF_RING_BASE_LSB //// @@ -4573,7 +4552,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -4581,7 +4560,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -4595,7 +4574,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -4603,7 +4582,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -4620,7 +4599,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUTM(x, mask, val) \ @@ -4628,7 +4607,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_SHFT 0x8 @@ -4645,7 +4624,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUTM(x, mask, val) \ @@ -4653,7 +4632,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -4670,7 +4649,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUTM(x, mask, val) \ @@ -4678,7 +4657,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -4707,7 +4686,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -4715,7 +4694,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -4729,7 +4708,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -4737,7 +4716,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -4751,7 +4730,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -4759,7 +4738,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -4779,7 +4758,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -4787,7 +4766,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -4802,12 +4781,12 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000040c) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000040c) -#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -4815,9 +4794,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB //// @@ -4829,7 +4808,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -4837,7 +4816,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -4851,7 +4830,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -4859,7 +4838,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -4876,7 +4855,7 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -4884,7 +4863,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -4893,12 +4872,12 @@ #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000434) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000434) -#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -4906,9 +4885,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2FW_BUF_RING_BASE_LSB //// @@ -4920,7 +4899,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -4928,7 +4907,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -4942,7 +4921,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -4950,7 +4929,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -4967,7 +4946,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUTM(x, mask, val) \ @@ -4975,7 +4954,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_SHFT 0x8 @@ -4992,7 +4971,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUTM(x, mask, val) \ @@ -5000,7 +4979,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -5017,7 +4996,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUTM(x, mask, val) \ @@ -5025,7 +5004,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -5054,7 +5033,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -5062,7 +5041,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -5076,7 +5055,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -5084,7 +5063,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -5098,7 +5077,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -5106,7 +5085,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -5126,7 +5105,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -5134,7 +5113,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -5149,12 +5128,12 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000464) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000464) -#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -5162,9 +5141,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB //// @@ -5176,7 +5155,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -5184,7 +5163,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -5198,7 +5177,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -5206,7 +5185,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -5223,7 +5202,7 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -5231,7 +5210,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -5240,12 +5219,12 @@ #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000048c) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000048c) -#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -5253,9 +5232,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB //// @@ -5267,7 +5246,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -5275,7 +5254,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -5289,7 +5268,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -5297,7 +5276,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -5314,7 +5293,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUTM(x, mask, val) \ @@ -5322,7 +5301,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_SHFT 0x8 @@ -5339,7 +5318,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUTM(x, mask, val) \ @@ -5347,7 +5326,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -5364,7 +5343,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUTM(x, mask, val) \ @@ -5372,7 +5351,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -5401,7 +5380,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -5409,7 +5388,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -5423,7 +5402,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -5431,7 +5410,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -5445,7 +5424,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -5453,7 +5432,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -5473,7 +5452,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -5481,7 +5460,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -5496,12 +5475,12 @@ #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004bc) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004bc) -#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -5509,21 +5488,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004e4) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004e4) -#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -5531,9 +5510,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB //// @@ -5545,7 +5524,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -5553,7 +5532,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -5567,7 +5546,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -5575,7 +5554,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -5592,7 +5571,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_OUTM(x, mask, val) \ @@ -5600,7 +5579,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RING_ID_SHFT 0x8 @@ -5617,7 +5596,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_OUTM(x, mask, val) \ @@ -5625,7 +5604,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -5642,7 +5621,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_OUTM(x, mask, val) \ @@ -5650,7 +5629,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -5679,7 +5658,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -5687,7 +5666,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -5701,7 +5680,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -5709,7 +5688,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -5723,7 +5702,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -5731,7 +5710,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -5751,7 +5730,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -5759,7 +5738,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -5774,12 +5753,12 @@ #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000514) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000514) -#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -5787,21 +5766,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000053c) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000053c) -#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -5809,9 +5788,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB //// @@ -5823,7 +5802,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -5831,7 +5810,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -5845,7 +5824,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -5853,7 +5832,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -5870,7 +5849,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_OUTM(x, mask, val) \ @@ -5878,7 +5857,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RING_ID_SHFT 0x8 @@ -5895,7 +5874,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_OUTM(x, mask, val) \ @@ -5903,7 +5882,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -5920,7 +5899,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_OUTM(x, mask, val) \ @@ -5928,7 +5907,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -5957,7 +5936,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -5965,7 +5944,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -5979,7 +5958,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -5987,7 +5966,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -6001,7 +5980,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -6009,7 +5988,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -6029,7 +6008,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -6037,7 +6016,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -6052,12 +6031,12 @@ #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000056c) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000056c) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -6065,21 +6044,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000594) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000594) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -6087,9 +6066,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2TQM_LINK_RING_BASE_LSB //// @@ -6101,7 +6080,7 @@ #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -6109,7 +6088,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -6123,7 +6102,7 @@ #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -6131,7 +6110,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -6148,7 +6127,7 @@ #define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUTM(x, mask, val) \ @@ -6156,7 +6135,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_SHFT 0x8 @@ -6173,7 +6152,7 @@ #define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUTM(x, mask, val) \ @@ -6181,7 +6160,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -6198,7 +6177,7 @@ #define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUTM(x, mask, val) \ @@ -6206,7 +6185,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -6235,7 +6214,7 @@ #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -6243,7 +6222,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -6257,7 +6236,7 @@ #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -6265,7 +6244,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -6279,7 +6258,7 @@ #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -6287,7 +6266,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -6307,7 +6286,7 @@ #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -6315,7 +6294,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -6330,12 +6309,12 @@ #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000005c4) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000005c4) -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -6343,21 +6322,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000005ec) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000005ec) -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -6365,9 +6344,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2REO_LINK_RING_BASE_LSB //// @@ -6379,7 +6358,7 @@ #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -6387,7 +6366,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -6401,7 +6380,7 @@ #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -6409,7 +6388,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -6426,7 +6405,7 @@ #define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ @@ -6434,7 +6413,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT 0x8 @@ -6451,7 +6430,7 @@ #define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ @@ -6459,7 +6438,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -6476,7 +6455,7 @@ #define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ @@ -6484,7 +6463,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -6513,7 +6492,7 @@ #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -6521,7 +6500,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -6535,7 +6514,7 @@ #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -6543,7 +6522,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -6557,7 +6536,7 @@ #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -6565,7 +6544,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -6585,7 +6564,7 @@ #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -6593,7 +6572,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -6608,12 +6587,12 @@ #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000061c) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000061c) -#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -6621,21 +6600,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000644) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000644) -#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -6643,9 +6622,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW_LINK_RING_BASE_LSB //// @@ -6657,7 +6636,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -6665,7 +6644,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -6679,7 +6658,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -6687,7 +6666,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -6704,7 +6683,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUTM(x, mask, val) \ @@ -6712,7 +6691,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_SHFT 0x8 @@ -6729,7 +6708,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUTM(x, mask, val) \ @@ -6737,7 +6716,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -6754,7 +6733,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUTM(x, mask, val) \ @@ -6762,7 +6741,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -6791,7 +6770,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -6799,7 +6778,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -6813,7 +6792,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -6821,7 +6800,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -6835,7 +6814,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -6843,7 +6822,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -6863,7 +6842,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -6871,7 +6850,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -6886,12 +6865,12 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000674) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000674) -#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -6899,9 +6878,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB //// @@ -6913,7 +6892,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -6921,7 +6900,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -6935,7 +6914,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -6943,7 +6922,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -6960,7 +6939,7 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -6968,7 +6947,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -6977,12 +6956,12 @@ #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000069c) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000069c) -#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -6990,9 +6969,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2FW_LINK_RING_BASE_LSB //// @@ -7004,7 +6983,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -7012,7 +6991,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -7026,7 +7005,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -7034,7 +7013,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -7051,7 +7030,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUTM(x, mask, val) \ @@ -7059,7 +7038,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_SHFT 0x8 @@ -7076,7 +7055,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUTM(x, mask, val) \ @@ -7084,7 +7063,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -7101,7 +7080,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUTM(x, mask, val) \ @@ -7109,7 +7088,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -7138,7 +7117,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -7146,7 +7125,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -7160,7 +7139,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -7168,7 +7147,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -7182,7 +7161,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -7190,7 +7169,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -7210,7 +7189,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -7218,7 +7197,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -7233,12 +7212,12 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000006cc) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000006cc) -#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -7246,9 +7225,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB //// @@ -7260,7 +7239,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -7268,7 +7247,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -7282,7 +7261,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -7290,7 +7269,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -7307,7 +7286,7 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -7315,7 +7294,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -7324,12 +7303,12 @@ #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006f4) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006f4) -#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -7337,9 +7316,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB //// @@ -7351,7 +7330,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -7359,7 +7338,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -7373,7 +7352,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -7381,7 +7360,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -7398,7 +7377,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUTM(x, mask, val) \ @@ -7406,7 +7385,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_SHFT 0x8 @@ -7423,7 +7402,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUTM(x, mask, val) \ @@ -7431,7 +7410,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -7448,7 +7427,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUTM(x, mask, val) \ @@ -7456,7 +7435,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -7485,7 +7464,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -7493,7 +7472,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -7507,7 +7486,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -7515,7 +7494,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -7529,7 +7508,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -7537,7 +7516,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -7557,7 +7536,7 @@ #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -7565,7 +7544,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -7580,12 +7559,12 @@ #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000724) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000724) -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -7593,21 +7572,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000074c) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000074c) -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -7615,9 +7594,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB //// @@ -7629,7 +7608,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -7637,7 +7616,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -7651,7 +7630,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -7659,7 +7638,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -7676,7 +7655,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_OUTM(x, mask, val) \ @@ -7684,7 +7663,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RING_ID_SHFT 0x8 @@ -7701,7 +7680,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_OUTM(x, mask, val) \ @@ -7709,7 +7688,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -7726,7 +7705,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_OUTM(x, mask, val) \ @@ -7734,7 +7713,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -7763,7 +7742,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -7771,7 +7750,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -7785,7 +7764,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -7793,7 +7772,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -7807,7 +7786,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -7815,7 +7794,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -7835,7 +7814,7 @@ #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -7843,7 +7822,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -7858,12 +7837,12 @@ #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000077c) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000077c) -#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -7871,21 +7850,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007a4) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007a4) -#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -7893,9 +7872,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB //// @@ -7907,7 +7886,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -7915,7 +7894,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -7929,7 +7908,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -7937,7 +7916,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -7954,7 +7933,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_OUTM(x, mask, val) \ @@ -7962,7 +7941,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RING_ID_SHFT 0x8 @@ -7979,7 +7958,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_OUTM(x, mask, val) \ @@ -7987,7 +7966,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -8004,7 +7983,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_OUTM(x, mask, val) \ @@ -8012,7 +7991,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -8041,7 +8020,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -8049,7 +8028,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -8063,7 +8042,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -8071,7 +8050,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -8085,7 +8064,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -8093,7 +8072,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -8113,7 +8092,7 @@ #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -8121,7 +8100,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -8136,12 +8115,12 @@ #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000007d4) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000007d4) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -8149,21 +8128,21 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET //// #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007fc) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007fc) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -8171,9 +8150,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB //// @@ -8185,7 +8164,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -8193,7 +8172,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -8207,7 +8186,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -8215,7 +8194,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -8232,7 +8211,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUTM(x, mask, val) \ @@ -8240,7 +8219,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_SHFT 0x8 @@ -8257,7 +8236,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUTM(x, mask, val) \ @@ -8265,7 +8244,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -8282,7 +8261,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUTM(x, mask, val) \ @@ -8290,7 +8269,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -8319,7 +8298,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -8327,7 +8306,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -8341,7 +8320,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -8349,7 +8328,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -8363,7 +8342,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -8371,7 +8350,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -8385,7 +8364,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -8393,7 +8372,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -8407,7 +8386,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -8415,7 +8394,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -8435,7 +8414,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -8443,7 +8422,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -8458,12 +8437,12 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000082c) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000082c) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -8471,9 +8450,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0 //// @@ -8485,7 +8464,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -8493,7 +8472,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -8513,7 +8492,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -8521,7 +8500,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -8535,7 +8514,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -8543,7 +8522,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -8558,12 +8537,12 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000083c) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000083c) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -8571,9 +8550,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER //// @@ -8585,7 +8564,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -8593,7 +8572,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -8607,7 +8586,7 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -8615,7 +8594,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -8627,12 +8606,12 @@ #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000854) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000854) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -8640,9 +8619,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB //// @@ -8654,7 +8633,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -8662,7 +8641,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -8676,7 +8655,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -8684,7 +8663,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -8701,7 +8680,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUTM(x, mask, val) \ @@ -8709,7 +8688,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_SHFT 0x8 @@ -8726,7 +8705,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUTM(x, mask, val) \ @@ -8734,7 +8713,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -8751,7 +8730,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUTM(x, mask, val) \ @@ -8759,7 +8738,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -8788,7 +8767,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -8796,7 +8775,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -8810,7 +8789,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -8818,7 +8797,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -8832,7 +8811,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -8840,7 +8819,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -8854,7 +8833,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -8862,7 +8841,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -8876,7 +8855,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -8884,7 +8863,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -8904,7 +8883,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -8912,7 +8891,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -8927,12 +8906,12 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000884) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000884) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -8940,9 +8919,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0 //// @@ -8954,7 +8933,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -8962,7 +8941,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -8982,7 +8961,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -8990,7 +8969,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -9004,7 +8983,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -9012,7 +8991,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -9027,12 +9006,12 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000894) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000894) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -9040,9 +9019,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER //// @@ -9054,7 +9033,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -9062,7 +9041,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -9076,7 +9055,7 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -9084,7 +9063,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -9096,12 +9075,12 @@ #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008ac) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008ac) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -9109,9 +9088,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB //// @@ -9123,7 +9102,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -9131,7 +9110,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -9145,7 +9124,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -9153,7 +9132,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -9170,7 +9149,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -9178,7 +9157,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_SHFT 0x8 @@ -9195,7 +9174,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -9203,7 +9182,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -9220,7 +9199,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -9228,7 +9207,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -9257,7 +9236,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -9265,7 +9244,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -9279,7 +9258,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -9287,7 +9266,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -9301,7 +9280,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -9309,7 +9288,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -9329,7 +9308,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -9337,7 +9316,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -9352,12 +9331,12 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008dc) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008dc) -#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -9365,9 +9344,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB //// @@ -9379,7 +9358,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -9387,7 +9366,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -9401,7 +9380,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -9409,7 +9388,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -9426,7 +9405,7 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -9434,7 +9413,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -9443,12 +9422,12 @@ #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000904) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000904) -#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -9456,9 +9435,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB //// @@ -9470,7 +9449,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -9478,7 +9457,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -9492,7 +9471,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -9500,7 +9479,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -9517,7 +9496,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -9525,7 +9504,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_SHFT 0x8 @@ -9542,7 +9521,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -9550,7 +9529,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -9567,7 +9546,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -9575,7 +9554,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -9604,7 +9583,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -9612,7 +9591,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -9626,7 +9605,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -9634,7 +9613,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -9648,7 +9627,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -9656,7 +9635,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -9676,7 +9655,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -9684,7 +9663,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -9699,12 +9678,12 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000934) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000934) -#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -9712,9 +9691,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB //// @@ -9726,7 +9705,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -9734,7 +9713,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -9748,7 +9727,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -9756,7 +9735,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -9773,7 +9752,7 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -9781,7 +9760,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -9790,12 +9769,12 @@ #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000095c) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000095c) -#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -9803,9 +9782,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB //// @@ -9817,7 +9796,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -9825,7 +9804,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -9839,7 +9818,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -9847,7 +9826,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -9864,7 +9843,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -9872,7 +9851,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_SHFT 0x8 @@ -9889,7 +9868,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -9897,7 +9876,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -9914,7 +9893,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -9922,7 +9901,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -9951,7 +9930,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -9959,7 +9938,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -9973,7 +9952,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -9981,7 +9960,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -9995,7 +9974,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -10003,7 +9982,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -10023,7 +10002,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -10031,7 +10010,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -10046,12 +10025,12 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000098c) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000098c) -#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -10059,9 +10038,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB //// @@ -10073,7 +10052,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -10081,7 +10060,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -10095,7 +10074,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -10103,7 +10082,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -10120,7 +10099,7 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -10128,7 +10107,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -10137,12 +10116,12 @@ #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000009b4) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000009b4) -#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -10150,9 +10129,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB //// @@ -10164,7 +10143,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -10172,7 +10151,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -10186,7 +10165,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -10194,7 +10173,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -10211,7 +10190,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -10219,7 +10198,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_SHFT 0x8 @@ -10236,7 +10215,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -10244,7 +10223,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -10261,7 +10240,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -10269,7 +10248,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -10298,7 +10277,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -10306,7 +10285,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -10320,7 +10299,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -10328,7 +10307,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -10342,7 +10321,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -10350,7 +10329,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -10370,7 +10349,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -10378,7 +10357,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -10393,12 +10372,12 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000009e4) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000009e4) -#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -10406,9 +10385,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB //// @@ -10420,7 +10399,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -10428,7 +10407,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -10442,7 +10421,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -10450,7 +10429,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -10467,7 +10446,7 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -10475,7 +10454,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -10484,12 +10463,12 @@ #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a0c) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a0c) -#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -10497,9 +10476,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB //// @@ -10511,7 +10490,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -10519,7 +10498,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -10533,7 +10512,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -10541,7 +10520,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -10558,7 +10537,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUTM(x, mask, val) \ @@ -10566,7 +10545,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_SHFT 0x8 @@ -10583,7 +10562,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUTM(x, mask, val) \ @@ -10591,7 +10570,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -10608,7 +10587,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUTM(x, mask, val) \ @@ -10616,7 +10595,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -10645,7 +10624,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -10653,7 +10632,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -10667,7 +10646,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -10675,7 +10654,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -10689,7 +10668,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -10697,7 +10676,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -10717,7 +10696,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -10725,7 +10704,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -10740,12 +10719,12 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000a3c) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000a3c) -#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -10753,9 +10732,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB //// @@ -10767,7 +10746,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -10775,7 +10754,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -10789,7 +10768,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -10797,7 +10776,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -10814,7 +10793,7 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -10822,7 +10801,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -10831,12 +10810,12 @@ #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a64) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a64) -#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -10844,9 +10823,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WBM_R1_END_OF_TEST_CHECK //// @@ -10858,7 +10837,7 @@ #define HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x) \ in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK) #define HWIO_WBM_R1_END_OF_TEST_CHECK_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask) #define HWIO_WBM_R1_END_OF_TEST_CHECK_OUT(x, val) \ out_dword( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), val) #define HWIO_WBM_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ @@ -10866,7 +10845,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 @@ -10880,7 +10859,7 @@ #define HWIO_WBM_R1_TESTBUS_CTRL_IN(x) \ in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), HWIO_WBM_R1_TESTBUS_CTRL_RMSK) #define HWIO_WBM_R1_TESTBUS_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask) #define HWIO_WBM_R1_TESTBUS_CTRL_OUT(x, val) \ out_dword( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), val) #define HWIO_WBM_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ @@ -10888,7 +10867,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_BMSK 0x00001f00 #define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_SHFT 0x8 @@ -10905,7 +10884,7 @@ #define HWIO_WBM_R1_TESTBUS_LOWER_IN(x) \ in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R1_TESTBUS_LOWER_RMSK) #define HWIO_WBM_R1_TESTBUS_LOWER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask) #define HWIO_WBM_R1_TESTBUS_LOWER_OUT(x, val) \ out_dword( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), val) #define HWIO_WBM_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ @@ -10913,7 +10892,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_LOWER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff #define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 @@ -10927,7 +10906,7 @@ #define HWIO_WBM_R1_TESTBUS_HIGHER_IN(x) \ in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), HWIO_WBM_R1_TESTBUS_HIGHER_RMSK) #define HWIO_WBM_R1_TESTBUS_HIGHER_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask) #define HWIO_WBM_R1_TESTBUS_HIGHER_OUT(x, val) \ out_dword( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), val) #define HWIO_WBM_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ @@ -10935,7 +10914,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_HIGHER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff #define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 @@ -10949,7 +10928,7 @@ #define HWIO_WBM_R1_SM_STATES_IX_0_IN(x) \ in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_0_RMSK) #define HWIO_WBM_R1_SM_STATES_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask) #define HWIO_WBM_R1_SM_STATES_IX_0_OUT(x, val) \ out_dword( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), val) #define HWIO_WBM_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ @@ -10957,7 +10936,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_BMSK 0x60000000 #define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_SHFT 0x1d @@ -11010,7 +10989,7 @@ #define HWIO_WBM_R1_SM_STATES_IX_1_IN(x) \ in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_1_RMSK) #define HWIO_WBM_R1_SM_STATES_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask) #define HWIO_WBM_R1_SM_STATES_IX_1_OUT(x, val) \ out_dword( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), val) #define HWIO_WBM_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ @@ -11018,7 +10997,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_BMSK 0x0000e000 #define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_SHFT 0xd @@ -11047,7 +11026,7 @@ #define HWIO_WBM_R1_EVENTMASK_IX_0_IN(x) \ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_0_RMSK) #define HWIO_WBM_R1_EVENTMASK_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask) #define HWIO_WBM_R1_EVENTMASK_IX_0_OUT(x, val) \ out_dword( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), val) #define HWIO_WBM_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ @@ -11055,7 +11034,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff #define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 @@ -11069,7 +11048,7 @@ #define HWIO_WBM_R1_EVENTMASK_IX_1_IN(x) \ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_1_RMSK) #define HWIO_WBM_R1_EVENTMASK_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask) #define HWIO_WBM_R1_EVENTMASK_IX_1_OUT(x, val) \ out_dword( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), val) #define HWIO_WBM_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ @@ -11077,7 +11056,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff #define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 @@ -11091,7 +11070,7 @@ #define HWIO_WBM_R1_EVENTMASK_IX_2_IN(x) \ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_2_RMSK) #define HWIO_WBM_R1_EVENTMASK_IX_2_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask) #define HWIO_WBM_R1_EVENTMASK_IX_2_OUT(x, val) \ out_dword( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), val) #define HWIO_WBM_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ @@ -11099,7 +11078,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_BMSK 0xffffffff #define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_SHFT 0x0 @@ -11113,7 +11092,7 @@ #define HWIO_WBM_R1_EVENTMASK_IX_3_IN(x) \ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_3_RMSK) #define HWIO_WBM_R1_EVENTMASK_IX_3_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask) #define HWIO_WBM_R1_EVENTMASK_IX_3_OUT(x, val) \ out_dword( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), val) #define HWIO_WBM_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ @@ -11121,7 +11100,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_BMSK 0xffffffff #define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_SHFT 0x0 @@ -11135,7 +11114,7 @@ #define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) #define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) #define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ out_dword( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) #define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ @@ -11143,7 +11122,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 #define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 @@ -11166,7 +11145,7 @@ #define HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_PPE_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -11174,7 +11153,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11188,7 +11167,7 @@ #define HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_PPE_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -11196,7 +11175,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11210,7 +11189,7 @@ #define HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_TQM_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -11218,7 +11197,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11232,7 +11211,7 @@ #define HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_TQM_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -11240,7 +11219,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11254,7 +11233,7 @@ #define HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_REO_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -11262,7 +11241,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11276,7 +11255,7 @@ #define HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_REO_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -11284,7 +11263,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11298,7 +11277,7 @@ #define HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_SW_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -11306,7 +11285,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11320,7 +11299,7 @@ #define HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_SW_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -11328,7 +11307,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11342,7 +11321,7 @@ #define HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_FW_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -11350,7 +11329,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11364,7 +11343,7 @@ #define HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_FW_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -11372,7 +11351,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11386,7 +11365,7 @@ #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -11394,7 +11373,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11408,7 +11387,7 @@ #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -11416,7 +11395,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11430,7 +11409,7 @@ #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -11438,7 +11417,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11452,7 +11431,7 @@ #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -11460,7 +11439,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11474,7 +11453,7 @@ #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -11482,7 +11461,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11496,7 +11475,7 @@ #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -11504,7 +11483,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11518,7 +11497,7 @@ #define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUTM(x, mask, val) \ @@ -11526,7 +11505,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11540,7 +11519,7 @@ #define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUTM(x, mask, val) \ @@ -11548,7 +11527,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11562,7 +11541,7 @@ #define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUTM(x, mask, val) \ @@ -11570,7 +11549,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11584,7 +11563,7 @@ #define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUTM(x, mask, val) \ @@ -11592,7 +11571,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11606,7 +11585,7 @@ #define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUTM(x, mask, val) \ @@ -11614,7 +11593,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11628,7 +11607,7 @@ #define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUTM(x, mask, val) \ @@ -11636,7 +11615,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11650,7 +11629,7 @@ #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUTM(x, mask, val) \ @@ -11658,7 +11637,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11672,7 +11651,7 @@ #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUTM(x, mask, val) \ @@ -11680,7 +11659,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11694,7 +11673,7 @@ #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_OUTM(x, mask, val) \ @@ -11702,7 +11681,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11716,7 +11695,7 @@ #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_OUTM(x, mask, val) \ @@ -11724,7 +11703,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11738,7 +11717,7 @@ #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_OUTM(x, mask, val) \ @@ -11746,7 +11725,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11760,7 +11739,7 @@ #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_OUTM(x, mask, val) \ @@ -11768,7 +11747,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11782,7 +11761,7 @@ #define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUTM(x, mask, val) \ @@ -11790,7 +11769,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11804,7 +11783,7 @@ #define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUTM(x, mask, val) \ @@ -11812,7 +11791,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11826,7 +11805,7 @@ #define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ @@ -11834,7 +11813,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11848,7 +11827,7 @@ #define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ @@ -11856,7 +11835,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11870,7 +11849,7 @@ #define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUTM(x, mask, val) \ @@ -11878,7 +11857,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11892,7 +11871,7 @@ #define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUTM(x, mask, val) \ @@ -11900,7 +11879,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11914,7 +11893,7 @@ #define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUTM(x, mask, val) \ @@ -11922,7 +11901,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11936,7 +11915,7 @@ #define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUTM(x, mask, val) \ @@ -11944,7 +11923,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_SHFT 0x0 @@ -11958,7 +11937,7 @@ #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUTM(x, mask, val) \ @@ -11966,7 +11945,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_SHFT 0x0 @@ -11980,7 +11959,7 @@ #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUTM(x, mask, val) \ @@ -11988,7 +11967,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_SHFT 0x0 @@ -12002,7 +11981,7 @@ #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_OUTM(x, mask, val) \ @@ -12010,7 +11989,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_HEAD_PTR_SHFT 0x0 @@ -12024,7 +12003,7 @@ #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_OUTM(x, mask, val) \ @@ -12032,7 +12011,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_TAIL_PTR_SHFT 0x0 @@ -12046,7 +12025,7 @@ #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_OUTM(x, mask, val) \ @@ -12054,7 +12033,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_HEAD_PTR_SHFT 0x0 @@ -12068,7 +12047,7 @@ #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_OUTM(x, mask, val) \ @@ -12076,7 +12055,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_TAIL_PTR_SHFT 0x0 @@ -12090,7 +12069,7 @@ #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_RMSK) #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUTM(x, mask, val) \ @@ -12098,7 +12077,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_SHFT 0x0 @@ -12112,7 +12091,7 @@ #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_RMSK) #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUTM(x, mask, val) \ @@ -12120,7 +12099,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_SHFT 0x0 @@ -12134,7 +12113,7 @@ #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK) #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUTM(x, mask, val) \ @@ -12142,7 +12121,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_SHFT 0x0 @@ -12156,7 +12135,7 @@ #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK) #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUTM(x, mask, val) \ @@ -12164,7 +12143,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_SHFT 0x0 @@ -12178,7 +12157,7 @@ #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -12186,7 +12165,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -12200,7 +12179,7 @@ #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -12208,7 +12187,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -12222,7 +12201,7 @@ #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -12230,7 +12209,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -12244,7 +12223,7 @@ #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -12252,7 +12231,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -12266,7 +12245,7 @@ #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -12274,7 +12253,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -12288,7 +12267,7 @@ #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -12296,7 +12275,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -12310,7 +12289,7 @@ #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -12318,7 +12297,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -12332,7 +12311,7 @@ #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -12340,7 +12319,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 @@ -12354,7 +12333,7 @@ #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK) #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUTM(x, mask, val) \ @@ -12362,7 +12341,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 @@ -12376,7 +12355,7 @@ #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x) \ in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK) #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask) #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUT(x, val) \ out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), val) #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUTM(x, mask, val) \ @@ -12384,7 +12363,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 diff --git a/hw/qca8074/v1/wcss_seq_hwiobase.h b/hw/qca8074/v1/wcss_seq_hwiobase.h index 8efcab08ecce..f5e8917d4ae5 100644 --- a/hw/qca8074/v1/wcss_seq_hwiobase.h +++ b/hw/qca8074/v1/wcss_seq_hwiobase.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,7 +18,7 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016 +// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.1 2/3/2017 // User Name:pgohil // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. @@ -42,8 +42,11 @@ #define SEQ_WCSS_ECAHB_OFFSET 0x00008000 #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 -#define SEQ_WCSS_MPSS_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00240000 -#define SEQ_WCSS_MPSS_PCSS_B_REG_MAP_OFFSET 0x00250000 +#define SEQ_WCSS_MPSS_OFFSET 0x00200000 +#define SEQ_WCSS_MPSS_SEG0PDMEM_WFAX_PCSS_PDMEM_OFFSET 0x00200000 +#define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_OFFSET 0x00280000 +#define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00281800 +#define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_WATCHDOG_OFFSET 0x00281c00 #define SEQ_WCSS_PHYA0_OFFSET 0x00400000 #define SEQ_WCSS_PHYA0_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000 #define SEQ_WCSS_PHYA0_WFAX_PCSS_REG_MAP_OFFSET 0x00480000 @@ -52,6 +55,8 @@ #define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00480c00 #define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00481000 #define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00481400 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00481800 +#define SEQ_WCSS_PHYA0_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00481c00 #define SEQ_WCSS_PHYA0_WFAX_NOC_REG_MAP_OFFSET 0x00484000 #define SEQ_WCSS_PHYA0_WFAX_TXTD_REG_MAP_OFFSET 0x00488000 #define SEQ_WCSS_PHYA0_WFAX_TXFD_REG_MAP_OFFSET 0x00500000 @@ -59,6 +64,126 @@ #define SEQ_WCSS_PHYA0_WFAX_RXTD_REG_MAP_OFFSET 0x00528000 #define SEQ_WCSS_PHYA0_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00530000 #define SEQ_WCSS_PHYA0_WFAX_PHYRF_REG_MAP_OFFSET 0x005a0000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_DIG_OTP_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_DIG_TLMM_OFFSET 0x005c4000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x005c8000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4400 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6080 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d60c0 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6100 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d6140 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6200 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6880 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d68c0 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6900 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6940 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a00 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e0400 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e0800 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x005e1000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x005e1180 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x005e1300 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x005e1480 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x005e2000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x005e4000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x005e8000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x005e8400 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x005e8800 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x005e9000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x005e9180 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x005e9300 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x005e9480 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x005ea000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x005ec000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x005f0000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x005f0400 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x005f0800 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x005f1000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x005f1180 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x005f1300 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x005f1480 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x005f2000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x005f4000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x005f8000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x005f8400 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x005f8800 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x005f9000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x005f9180 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x005f9300 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x005f9480 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x005fa000 +#define SEQ_WCSS_PHYA0_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x005fc000 +#define SEQ_WCSS_IRONA0_OFFSET 0x005c0000 +#define SEQ_WCSS_IRONA0_RFA_DIG_OFFSET 0x005c0000 +#define SEQ_WCSS_IRONA0_RFA_DIG_OTP_OFFSET 0x005c0000 +#define SEQ_WCSS_IRONA0_RFA_DIG_TLMM_OFFSET 0x005c4000 +#define SEQ_WCSS_IRONA0_RFA_DIG_SYSCTRL_OFFSET 0x005c8000 +#define SEQ_WCSS_IRONA0_RFA_CMN_OFFSET 0x005d4000 +#define SEQ_WCSS_IRONA0_RFA_CMN_AON_OFFSET 0x005d4000 +#define SEQ_WCSS_IRONA0_RFA_CMN_RFFE_M_OFFSET 0x005d4300 +#define SEQ_WCSS_IRONA0_RFA_CMN_CLKGEN_OFFSET 0x005d4400 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6080 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d60c0 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6100 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d6140 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6200 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6880 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d68c0 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6900 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6940 +#define SEQ_WCSS_IRONA0_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a00 +#define SEQ_WCSS_IRONA0_RFA_WL_OFFSET 0x005e0000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_MC_CH0_OFFSET 0x005e0000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e0400 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e0800 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE2_CH0_OFFSET 0x005e1000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE5_CH0_OFFSET 0x005e1180 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE2_CH0_OFFSET 0x005e1300 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE5_CH0_OFFSET 0x005e1480 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TPC_CH0_OFFSET 0x005e2000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_MEM_CH0_OFFSET 0x005e4000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_MC_CH1_OFFSET 0x005e8000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXBB_CH1_OFFSET 0x005e8400 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXBB_CH1_OFFSET 0x005e8800 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE2_CH1_OFFSET 0x005e9000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE5_CH1_OFFSET 0x005e9180 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE2_CH1_OFFSET 0x005e9300 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE5_CH1_OFFSET 0x005e9480 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TPC_CH1_OFFSET 0x005ea000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_MEM_CH1_OFFSET 0x005ec000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_MC_CH2_OFFSET 0x005f0000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXBB_CH2_OFFSET 0x005f0400 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXBB_CH2_OFFSET 0x005f0800 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE2_CH2_OFFSET 0x005f1000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE5_CH2_OFFSET 0x005f1180 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE2_CH2_OFFSET 0x005f1300 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE5_CH2_OFFSET 0x005f1480 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TPC_CH2_OFFSET 0x005f2000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_MEM_CH2_OFFSET 0x005f4000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_MC_CH3_OFFSET 0x005f8000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXBB_CH3_OFFSET 0x005f8400 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXBB_CH3_OFFSET 0x005f8800 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE2_CH3_OFFSET 0x005f9000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_RXFE5_CH3_OFFSET 0x005f9180 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE2_CH3_OFFSET 0x005f9300 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TXFE5_CH3_OFFSET 0x005f9480 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_TPC_CH3_OFFSET 0x005fa000 +#define SEQ_WCSS_IRONA0_RFA_WL_WL_MEM_CH3_OFFSET 0x005fc000 #define SEQ_WCSS_PHYA1_OFFSET 0x00600000 #define SEQ_WCSS_PHYA1_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00600000 #define SEQ_WCSS_PHYA1_WFAX_PCSS_REG_MAP_OFFSET 0x00680000 @@ -67,6 +192,8 @@ #define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00680c00 #define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00681000 #define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00681400 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00681800 +#define SEQ_WCSS_PHYA1_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00681c00 #define SEQ_WCSS_PHYA1_WFAX_NOC_REG_MAP_OFFSET 0x00684000 #define SEQ_WCSS_PHYA1_WFAX_TXTD_REG_MAP_OFFSET 0x00688000 #define SEQ_WCSS_PHYA1_WFAX_TXFD_REG_MAP_OFFSET 0x00700000 @@ -74,6 +201,126 @@ #define SEQ_WCSS_PHYA1_WFAX_RXTD_REG_MAP_OFFSET 0x00728000 #define SEQ_WCSS_PHYA1_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00730000 #define SEQ_WCSS_PHYA1_WFAX_PHYRF_REG_MAP_OFFSET 0x007a0000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_OFFSET 0x007c0000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x007c0000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_DIG_OTP_OFFSET 0x007c0000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_DIG_TLMM_OFFSET 0x007c4000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x007c8000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x007d4000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x007d4000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x007d4300 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x007d4400 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d6080 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x007d60c0 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x007d6100 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x007d6140 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x007d6200 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x007d6800 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x007d6840 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x007d6880 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x007d68c0 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6900 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d6940 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x007d6a00 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x007e0000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x007e0000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x007e0400 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x007e0800 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x007e1000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x007e1180 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x007e1300 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x007e1480 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x007e2000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x007e4000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x007e8000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x007e8400 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x007e8800 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x007e9000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x007e9180 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x007e9300 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x007e9480 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x007ea000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x007ec000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x007f0000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x007f0400 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x007f0800 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x007f1000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x007f1180 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x007f1300 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x007f1480 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x007f2000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x007f4000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x007f8000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x007f8400 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x007f8800 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x007f9000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x007f9180 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x007f9300 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x007f9480 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x007fa000 +#define SEQ_WCSS_PHYA1_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x007fc000 +#define SEQ_WCSS_IRONA1_OFFSET 0x007c0000 +#define SEQ_WCSS_IRONA1_RFA_DIG_OFFSET 0x007c0000 +#define SEQ_WCSS_IRONA1_RFA_DIG_OTP_OFFSET 0x007c0000 +#define SEQ_WCSS_IRONA1_RFA_DIG_TLMM_OFFSET 0x007c4000 +#define SEQ_WCSS_IRONA1_RFA_DIG_SYSCTRL_OFFSET 0x007c8000 +#define SEQ_WCSS_IRONA1_RFA_CMN_OFFSET 0x007d4000 +#define SEQ_WCSS_IRONA1_RFA_CMN_AON_OFFSET 0x007d4000 +#define SEQ_WCSS_IRONA1_RFA_CMN_RFFE_M_OFFSET 0x007d4300 +#define SEQ_WCSS_IRONA1_RFA_CMN_CLKGEN_OFFSET 0x007d4400 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d6080 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x007d60c0 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x007d6100 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x007d6140 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x007d6200 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x007d6800 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x007d6840 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x007d6880 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x007d68c0 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6900 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d6940 +#define SEQ_WCSS_IRONA1_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x007d6a00 +#define SEQ_WCSS_IRONA1_RFA_WL_OFFSET 0x007e0000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_MC_CH0_OFFSET 0x007e0000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXBB_CH0_OFFSET 0x007e0400 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXBB_CH0_OFFSET 0x007e0800 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE2_CH0_OFFSET 0x007e1000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE5_CH0_OFFSET 0x007e1180 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE2_CH0_OFFSET 0x007e1300 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE5_CH0_OFFSET 0x007e1480 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TPC_CH0_OFFSET 0x007e2000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_MEM_CH0_OFFSET 0x007e4000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_MC_CH1_OFFSET 0x007e8000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXBB_CH1_OFFSET 0x007e8400 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXBB_CH1_OFFSET 0x007e8800 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE2_CH1_OFFSET 0x007e9000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE5_CH1_OFFSET 0x007e9180 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE2_CH1_OFFSET 0x007e9300 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE5_CH1_OFFSET 0x007e9480 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TPC_CH1_OFFSET 0x007ea000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_MEM_CH1_OFFSET 0x007ec000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_MC_CH2_OFFSET 0x007f0000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXBB_CH2_OFFSET 0x007f0400 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXBB_CH2_OFFSET 0x007f0800 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE2_CH2_OFFSET 0x007f1000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE5_CH2_OFFSET 0x007f1180 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE2_CH2_OFFSET 0x007f1300 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE5_CH2_OFFSET 0x007f1480 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TPC_CH2_OFFSET 0x007f2000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_MEM_CH2_OFFSET 0x007f4000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_MC_CH3_OFFSET 0x007f8000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXBB_CH3_OFFSET 0x007f8400 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXBB_CH3_OFFSET 0x007f8800 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE2_CH3_OFFSET 0x007f9000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_RXFE5_CH3_OFFSET 0x007f9180 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE2_CH3_OFFSET 0x007f9300 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TXFE5_CH3_OFFSET 0x007f9480 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_TPC_CH3_OFFSET 0x007fa000 +#define SEQ_WCSS_IRONA1_RFA_WL_WL_MEM_CH3_OFFSET 0x007fc000 #define SEQ_WCSS_PHYB_OFFSET 0x00800000 #define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00800000 #define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00880000 @@ -82,6 +329,8 @@ #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00880c00 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00881000 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00881400 +#define SEQ_WCSS_PHYB_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00881800 +#define SEQ_WCSS_PHYB_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00881c00 #define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00884000 #define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00888000 #define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00900000 @@ -89,6 +338,126 @@ #define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00928000 #define SEQ_WCSS_PHYB_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00930000 #define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x009a0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET 0x009c0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x009c0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OTP_OFFSET 0x009c0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_TLMM_OFFSET 0x009c4000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x009c8000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x009d4000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x009d4000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x009d4300 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x009d4400 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x009d6000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x009d6040 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x009d6080 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x009d60c0 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x009d6100 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x009d6140 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x009d6200 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x009d6800 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x009d6840 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x009d6880 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x009d68c0 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x009d6900 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x009d6940 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x009d6a00 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x009e0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x009e0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x009e0400 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x009e0800 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x009e1000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x009e1180 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x009e1300 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x009e1480 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x009e2000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x009e4000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x009e8000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x009e8400 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x009e8800 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x009e9000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x009e9180 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x009e9300 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x009e9480 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x009ea000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x009ec000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x009f0000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x009f0400 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x009f0800 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x009f1000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x009f1180 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x009f1300 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x009f1480 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x009f2000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x009f4000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x009f8000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x009f8400 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x009f8800 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x009f9000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x009f9180 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x009f9300 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x009f9480 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x009fa000 +#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x009fc000 +#define SEQ_WCSS_IRONB_OFFSET 0x009c0000 +#define SEQ_WCSS_IRONB_RFA_DIG_OFFSET 0x009c0000 +#define SEQ_WCSS_IRONB_RFA_DIG_OTP_OFFSET 0x009c0000 +#define SEQ_WCSS_IRONB_RFA_DIG_TLMM_OFFSET 0x009c4000 +#define SEQ_WCSS_IRONB_RFA_DIG_SYSCTRL_OFFSET 0x009c8000 +#define SEQ_WCSS_IRONB_RFA_CMN_OFFSET 0x009d4000 +#define SEQ_WCSS_IRONB_RFA_CMN_AON_OFFSET 0x009d4000 +#define SEQ_WCSS_IRONB_RFA_CMN_RFFE_M_OFFSET 0x009d4300 +#define SEQ_WCSS_IRONB_RFA_CMN_CLKGEN_OFFSET 0x009d4400 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x009d6000 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x009d6040 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x009d6080 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x009d60c0 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x009d6100 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x009d6140 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x009d6200 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x009d6800 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x009d6840 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x009d6880 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x009d68c0 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x009d6900 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x009d6940 +#define SEQ_WCSS_IRONB_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x009d6a00 +#define SEQ_WCSS_IRONB_RFA_WL_OFFSET 0x009e0000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_MC_CH0_OFFSET 0x009e0000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXBB_CH0_OFFSET 0x009e0400 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXBB_CH0_OFFSET 0x009e0800 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE2_CH0_OFFSET 0x009e1000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE5_CH0_OFFSET 0x009e1180 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE2_CH0_OFFSET 0x009e1300 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE5_CH0_OFFSET 0x009e1480 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TPC_CH0_OFFSET 0x009e2000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_MEM_CH0_OFFSET 0x009e4000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_MC_CH1_OFFSET 0x009e8000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXBB_CH1_OFFSET 0x009e8400 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXBB_CH1_OFFSET 0x009e8800 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE2_CH1_OFFSET 0x009e9000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE5_CH1_OFFSET 0x009e9180 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE2_CH1_OFFSET 0x009e9300 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE5_CH1_OFFSET 0x009e9480 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TPC_CH1_OFFSET 0x009ea000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_MEM_CH1_OFFSET 0x009ec000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_MC_CH2_OFFSET 0x009f0000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXBB_CH2_OFFSET 0x009f0400 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXBB_CH2_OFFSET 0x009f0800 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE2_CH2_OFFSET 0x009f1000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE5_CH2_OFFSET 0x009f1180 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE2_CH2_OFFSET 0x009f1300 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE5_CH2_OFFSET 0x009f1480 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TPC_CH2_OFFSET 0x009f2000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_MEM_CH2_OFFSET 0x009f4000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_MC_CH3_OFFSET 0x009f8000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXBB_CH3_OFFSET 0x009f8400 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXBB_CH3_OFFSET 0x009f8800 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE2_CH3_OFFSET 0x009f9000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_RXFE5_CH3_OFFSET 0x009f9180 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE2_CH3_OFFSET 0x009f9300 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TXFE5_CH3_OFFSET 0x009f9480 +#define SEQ_WCSS_IRONB_RFA_WL_WL_TPC_CH3_OFFSET 0x009fa000 +#define SEQ_WCSS_IRONB_RFA_WL_WL_MEM_CH3_OFFSET 0x009fc000 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000 @@ -203,8 +572,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00b84000 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00b88000 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00b88100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00b88200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00b88300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00b88180 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH0_OFFSET 0x00b881c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH0_OFFSET 0x00b882c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00b88340 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00b88400 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00b88440 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00b88480 @@ -213,8 +584,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00b88600 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00b88800 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00b88900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00b88a00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00b88b00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00b88980 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH1_OFFSET 0x00b889c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH1_OFFSET 0x00b88ac0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00b88b40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00b88c00 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00b88c40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00b88c80 @@ -223,8 +596,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00b88e00 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00b89000 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00b89100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00b89200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00b89300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00b89180 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH2_OFFSET 0x00b891c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH2_OFFSET 0x00b892c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00b89340 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00b89400 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00b89440 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00b89480 @@ -233,8 +608,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00b89600 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00b89800 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00b89900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00b89a00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00b89b00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00b89980 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH3_OFFSET 0x00b899c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH3_OFFSET 0x00b89ac0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00b89b40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00b89c00 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00b89c40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00b89c80 @@ -243,8 +620,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00b89e00 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x00b8a000 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x00b8a100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x00b8a200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x00b8a300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x00b8a180 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH0_OFFSET 0x00b8a1c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH0_OFFSET 0x00b8a2c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x00b8a340 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x00b8a400 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x00b8a440 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x00b8a480 @@ -253,8 +632,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x00b8a600 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x00b8a800 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x00b8a900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x00b8aa00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x00b8ab00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x00b8a980 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH1_OFFSET 0x00b8a9c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH1_OFFSET 0x00b8aac0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x00b8ab40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x00b8ac00 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x00b8ac40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x00b8ac80 @@ -263,8 +644,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x00b8ae00 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x00b8b000 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x00b8b100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x00b8b200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x00b8b300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x00b8b180 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH2_OFFSET 0x00b8b1c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH2_OFFSET 0x00b8b2c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x00b8b340 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x00b8b400 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x00b8b440 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x00b8b480 @@ -273,8 +656,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x00b8b600 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x00b8b800 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x00b8b900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x00b8ba00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x00b8bb00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x00b8b980 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH3_OFFSET 0x00b8b9c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH3_OFFSET 0x00b8bac0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x00b8bb40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x00b8bc00 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x00b8bc40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x00b8bc80 @@ -283,8 +668,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x00b8be00 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x00b8c000 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x00b8c100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x00b8c200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x00b8c300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x00b8c180 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH0_OFFSET 0x00b8c1c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH0_OFFSET 0x00b8c2c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x00b8c340 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x00b8c400 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x00b8c440 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x00b8c480 @@ -293,8 +680,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x00b8c600 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x00b8c800 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x00b8c900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x00b8ca00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x00b8cb00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x00b8c980 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH1_OFFSET 0x00b8c9c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH1_OFFSET 0x00b8cac0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x00b8cb40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x00b8cc00 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x00b8cc40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x00b8cc80 @@ -303,8 +692,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x00b8ce00 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x00b8d000 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x00b8d100 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x00b8d200 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x00b8d300 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x00b8d180 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH2_OFFSET 0x00b8d1c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH2_OFFSET 0x00b8d2c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x00b8d340 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x00b8d400 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x00b8d440 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x00b8d480 @@ -313,8 +704,10 @@ #define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x00b8d600 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x00b8d800 #define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x00b8d900 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x00b8da00 -#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x00b8db00 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x00b8d980 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH3_OFFSET 0x00b8d9c0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH3_OFFSET 0x00b8dac0 +#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x00b8db40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x00b8dc00 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x00b8dc40 #define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x00b8dc80 @@ -341,19 +734,19 @@ #define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb0000 #define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00bb1000 #define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00bb6000 -#define SEQ_WCSS_DBG_PHYA_CPU0_AHB_AP_OFFSET 0x00bbe000 -#define SEQ_WCSS_DBG_PHYA_CPU1_AHB_AP_OFFSET 0x00bbf000 +#define SEQ_WCSS_DBG_PHYA_CPU0_M3_AHB_AP_OFFSET 0x00bbe000 +#define SEQ_WCSS_DBG_PHYA_CPU1_M3_AHB_AP_OFFSET 0x00bbf000 #define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc0000 #define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00bc1000 #define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc6000 -#define SEQ_WCSS_DBG_PHYB_CPU0_AHB_AP_OFFSET 0x00bce000 -#define SEQ_WCSS_DBG_UMAC_CPU_AHB_AP_OFFSET 0x00bf0000 +#define SEQ_WCSS_DBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x00bce000 +#define SEQ_WCSS_DBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00bf0000 +#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00bf1000 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000 #define SEQ_WCSS_CC_OFFSET 0x00c30000 #define SEQ_WCSS_ACMT_OFFSET 0x00c40000 #define SEQ_WCSS_WRAPPER_ACMT_OFFSET 0x00c60000 -#define SEQ_WCSS_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET 0x00c60000 #define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x00d00000 #define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x00d00000 #define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x00d80000 @@ -366,6 +759,16 @@ #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x00db0000 +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block mpss_top +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_MPSS_TOP_SEG0PDMEM_WFAX_PCSS_PDMEM_OFFSET 0x00000000 +#define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_OFFSET 0x00080000 +#define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00081800 +#define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_WATCHDOG_OFFSET 0x00081c00 + + /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block wfax_top /////////////////////////////////////////////////////////////////////////////////////////////// @@ -377,6 +780,8 @@ #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 +#define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00081800 +#define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00084000 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x00088000 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00100000 @@ -384,6 +789,205 @@ #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x00128000 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00130000 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x001a0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_OTP_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_TLMM_OFFSET 0x001c4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x001d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d60c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6100 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6140 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6200 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6880 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d68c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x001e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x001e1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x001e1180 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x001e1300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x001e1480 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x001e4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x001e9000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x001e9180 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x001e9300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x001e9480 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x001ec000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x001f1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x001f1180 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x001f1300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x001f1480 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x001f4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x001f9000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x001f9180 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x001f9300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x001f9480 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x001fc000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block iron2g +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_IRON2G_RFA_DIG_OFFSET 0x00000000 +#define SEQ_IRON2G_RFA_DIG_OTP_OFFSET 0x00000000 +#define SEQ_IRON2G_RFA_DIG_TLMM_OFFSET 0x00004000 +#define SEQ_IRON2G_RFA_DIG_SYSCTRL_OFFSET 0x00008000 +#define SEQ_IRON2G_RFA_CMN_OFFSET 0x00014000 +#define SEQ_IRON2G_RFA_CMN_AON_OFFSET 0x00014000 +#define SEQ_IRON2G_RFA_CMN_RFFE_M_OFFSET 0x00014300 +#define SEQ_IRON2G_RFA_CMN_CLKGEN_OFFSET 0x00014400 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016080 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x000160c0 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016100 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00016140 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016200 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00016880 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x000168c0 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016900 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00016940 +#define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a00 +#define SEQ_IRON2G_RFA_WL_OFFSET 0x00020000 +#define SEQ_IRON2G_RFA_WL_WL_MC_CH0_OFFSET 0x00020000 +#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400 +#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800 +#define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00021000 +#define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH0_OFFSET 0x00021180 +#define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00021300 +#define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH0_OFFSET 0x00021480 +#define SEQ_IRON2G_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000 +#define SEQ_IRON2G_RFA_WL_WL_MEM_CH0_OFFSET 0x00024000 +#define SEQ_IRON2G_RFA_WL_WL_MC_CH1_OFFSET 0x00028000 +#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400 +#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800 +#define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00029000 +#define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH1_OFFSET 0x00029180 +#define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00029300 +#define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH1_OFFSET 0x00029480 +#define SEQ_IRON2G_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000 +#define SEQ_IRON2G_RFA_WL_WL_MEM_CH1_OFFSET 0x0002c000 +#define SEQ_IRON2G_RFA_WL_WL_MC_CH2_OFFSET 0x00030000 +#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH2_OFFSET 0x00030400 +#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH2_OFFSET 0x00030800 +#define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH2_OFFSET 0x00031000 +#define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH2_OFFSET 0x00031180 +#define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH2_OFFSET 0x00031300 +#define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH2_OFFSET 0x00031480 +#define SEQ_IRON2G_RFA_WL_WL_TPC_CH2_OFFSET 0x00032000 +#define SEQ_IRON2G_RFA_WL_WL_MEM_CH2_OFFSET 0x00034000 +#define SEQ_IRON2G_RFA_WL_WL_MC_CH3_OFFSET 0x00038000 +#define SEQ_IRON2G_RFA_WL_WL_RXBB_CH3_OFFSET 0x00038400 +#define SEQ_IRON2G_RFA_WL_WL_TXBB_CH3_OFFSET 0x00038800 +#define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH3_OFFSET 0x00039000 +#define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH3_OFFSET 0x00039180 +#define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH3_OFFSET 0x00039300 +#define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH3_OFFSET 0x00039480 +#define SEQ_IRON2G_RFA_WL_WL_TPC_CH3_OFFSET 0x0003a000 +#define SEQ_IRON2G_RFA_WL_WL_MEM_CH3_OFFSET 0x0003c000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_dig +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_DIG_OTP_OFFSET 0x00000000 +#define SEQ_RFA_DIG_TLMM_OFFSET 0x00004000 +#define SEQ_RFA_DIG_SYSCTRL_OFFSET 0x00008000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_cmn +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_CMN_AON_OFFSET 0x00000000 +#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 +#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000400 +#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 +#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 +#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002080 +#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x000020c0 +#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002100 +#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00002140 +#define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002200 +#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 +#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 +#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00002880 +#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x000028c0 +#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002900 +#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00002940 +#define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a00 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_wl +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000 +#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400 +#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800 +#define SEQ_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00001000 +#define SEQ_RFA_WL_WL_RXFE5_CH0_OFFSET 0x00001180 +#define SEQ_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00001300 +#define SEQ_RFA_WL_WL_TXFE5_CH0_OFFSET 0x00001480 +#define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000 +#define SEQ_RFA_WL_WL_MEM_CH0_OFFSET 0x00004000 +#define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000 +#define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400 +#define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800 +#define SEQ_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00009000 +#define SEQ_RFA_WL_WL_RXFE5_CH1_OFFSET 0x00009180 +#define SEQ_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00009300 +#define SEQ_RFA_WL_WL_TXFE5_CH1_OFFSET 0x00009480 +#define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000 +#define SEQ_RFA_WL_WL_MEM_CH1_OFFSET 0x0000c000 +#define SEQ_RFA_WL_WL_MC_CH2_OFFSET 0x00010000 +#define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET 0x00010400 +#define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET 0x00010800 +#define SEQ_RFA_WL_WL_RXFE2_CH2_OFFSET 0x00011000 +#define SEQ_RFA_WL_WL_RXFE5_CH2_OFFSET 0x00011180 +#define SEQ_RFA_WL_WL_TXFE2_CH2_OFFSET 0x00011300 +#define SEQ_RFA_WL_WL_TXFE5_CH2_OFFSET 0x00011480 +#define SEQ_RFA_WL_WL_TPC_CH2_OFFSET 0x00012000 +#define SEQ_RFA_WL_WL_MEM_CH2_OFFSET 0x00014000 +#define SEQ_RFA_WL_WL_MC_CH3_OFFSET 0x00018000 +#define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET 0x00018400 +#define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET 0x00018800 +#define SEQ_RFA_WL_WL_RXFE2_CH3_OFFSET 0x00019000 +#define SEQ_RFA_WL_WL_RXFE5_CH3_OFFSET 0x00019180 +#define SEQ_RFA_WL_WL_TXFE2_CH3_OFFSET 0x00019300 +#define SEQ_RFA_WL_WL_TXFE5_CH3_OFFSET 0x00019480 +#define SEQ_RFA_WL_WL_TPC_CH3_OFFSET 0x0001a000 +#define SEQ_RFA_WL_WL_MEM_CH3_OFFSET 0x0001c000 /////////////////////////////////////////////////////////////////////////////////////////////// @@ -397,6 +1001,8 @@ #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00081800 +#define SEQ_WFAX_TOP_B_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00081c00 #define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00084000 #define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x00088000 #define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00100000 @@ -404,6 +1010,66 @@ #define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000 #define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00130000 #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OTP_OFFSET 0x001c0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_TLMM_OFFSET 0x001c4000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x001d4000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4400 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d60c0 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6100 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6140 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6200 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6880 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d68c0 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x001e0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x001e1000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x001e1180 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x001e1300 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x001e1480 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x001e4000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x001e9000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x001e9180 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x001e9300 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x001e9480 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x001ec000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x001f1000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x001f1180 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x001f1300 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x001f1480 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x001f4000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x001f9000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x001f9180 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x001f9300 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x001f9480 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 +#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x001fc000 /////////////////////////////////////////////////////////////////////////////////////////////// @@ -485,15 +1151,15 @@ /////////////////////////////////////////////////////////////////////////////////////////////// -// Instance Relative Offsets from Block cxc_top_reg_14lpp +// Instance Relative Offsets from Block cxc_top_reg /////////////////////////////////////////////////////////////////////////////////////////////// -#define SEQ_CXC_TOP_REG_14LPP_CXC_BMH_REG_OFFSET 0x00000000 -#define SEQ_CXC_TOP_REG_14LPP_CXC_LCMH_REG_OFFSET 0x00002000 -#define SEQ_CXC_TOP_REG_14LPP_CXC_MCIBASIC_REG_OFFSET 0x00004000 -#define SEQ_CXC_TOP_REG_14LPP_CXC_LMH_REG_OFFSET 0x00006000 -#define SEQ_CXC_TOP_REG_14LPP_CXC_SMH_REG_OFFSET 0x00008000 -#define SEQ_CXC_TOP_REG_14LPP_CXC_PMH_REG_OFFSET 0x0000a000 +#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 +#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 +#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 +#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 +#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 +#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 /////////////////////////////////////////////////////////////////////////////////////////////// @@ -522,134 +1188,158 @@ /////////////////////////////////////////////////////////////////////////////////////////////// -// Instance Relative Offsets from Block rfa_cmn +// Instance Relative Offsets from Block zinc_rfa_cmn /////////////////////////////////////////////////////////////////////////////////////////////// -#define SEQ_RFA_CMN_PLL_A_OFFSET 0x00000000 -#define SEQ_RFA_CMN_BIASCLKS_A_OFFSET 0x00000100 -#define SEQ_RFA_CMN_PLL_B_OFFSET 0x00002000 -#define SEQ_RFA_CMN_BIASCLKS_B_OFFSET 0x00002100 -#define SEQ_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00004000 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00008000 -#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00008100 -#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00008200 -#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00008300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00008400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00008440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00008480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x000084c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00008500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00008600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00008800 -#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00008900 -#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00008a00 -#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00008b00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00008c00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00008c40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00008c80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00008cc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00008d00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00008e00 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00009000 -#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00009100 -#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00009200 -#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00009300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00009400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00009440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00009480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x000094c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00009500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00009600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00009800 -#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00009900 -#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00009a00 -#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00009b00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00009c00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00009c40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00009c80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00009cc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00009d00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00009e00 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x0000a000 -#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x0000a100 -#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x0000a200 -#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x0000a300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x0000a400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x0000a440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x0000a480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x0000a4c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x0000a500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x0000a600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x0000a800 -#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x0000a900 -#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x0000aa00 -#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x0000ab00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x0000ac00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x0000ac40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x0000ac80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x0000acc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x0000ad00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x0000ae00 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x0000b000 -#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x0000b100 -#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x0000b200 -#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x0000b300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x0000b400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x0000b440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x0000b480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x0000b4c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x0000b500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x0000b600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x0000b800 -#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x0000b900 -#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x0000ba00 -#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x0000bb00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x0000bc00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x0000bc40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x0000bc80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x0000bcc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x0000bd00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x0000be00 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x0000c000 -#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x0000c100 -#define SEQ_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x0000c200 -#define SEQ_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x0000c300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x0000c400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x0000c440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x0000c480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x0000c4c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x0000c500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x0000c600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x0000c800 -#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x0000c900 -#define SEQ_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x0000ca00 -#define SEQ_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x0000cb00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x0000cc00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x0000cc40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x0000cc80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x0000ccc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x0000cd00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x0000ce00 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x0000d000 -#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x0000d100 -#define SEQ_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x0000d200 -#define SEQ_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x0000d300 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x0000d400 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x0000d440 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x0000d480 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x0000d4c0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x0000d500 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x0000d600 -#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x0000d800 -#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x0000d900 -#define SEQ_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x0000da00 -#define SEQ_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x0000db00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x0000dc00 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x0000dc40 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x0000dc80 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x0000dcc0 -#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x0000dd00 -#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x0000de00 +#define SEQ_ZINC_RFA_CMN_PLL_A_OFFSET 0x00000000 +#define SEQ_ZINC_RFA_CMN_BIASCLKS_A_OFFSET 0x00000100 +#define SEQ_ZINC_RFA_CMN_PLL_B_OFFSET 0x00002000 +#define SEQ_ZINC_RFA_CMN_BIASCLKS_B_OFFSET 0x00002100 +#define SEQ_ZINC_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00004000 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00008000 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00008100 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00008180 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH0_OFFSET 0x000081c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH0_OFFSET 0x000082c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00008340 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00008400 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00008440 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00008480 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x000084c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00008500 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00008600 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00008800 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00008900 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00008980 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH1_OFFSET 0x000089c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH1_OFFSET 0x00008ac0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00008b40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00008c00 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00008c40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00008c80 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00008cc0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00008d00 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00008e00 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00009000 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00009100 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00009180 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH2_OFFSET 0x000091c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH2_OFFSET 0x000092c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00009340 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00009400 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00009440 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00009480 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x000094c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00009500 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00009600 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00009800 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00009900 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00009980 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA0_CH3_OFFSET 0x000099c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA0_CH3_OFFSET 0x00009ac0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00009b40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00009c00 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00009c40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00009c80 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00009cc0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00009d00 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00009e00 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x0000a000 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x0000a100 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x0000a180 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH0_OFFSET 0x0000a1c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH0_OFFSET 0x0000a2c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x0000a340 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x0000a400 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x0000a440 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x0000a480 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x0000a4c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x0000a500 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x0000a600 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x0000a800 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x0000a900 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x0000a980 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH1_OFFSET 0x0000a9c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH1_OFFSET 0x0000aac0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x0000ab40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x0000ac00 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x0000ac40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x0000ac80 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x0000acc0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x0000ad00 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x0000ae00 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x0000b000 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x0000b100 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x0000b180 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH2_OFFSET 0x0000b1c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH2_OFFSET 0x0000b2c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x0000b340 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x0000b400 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x0000b440 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x0000b480 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x0000b4c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x0000b500 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x0000b600 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x0000b800 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x0000b900 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x0000b980 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYA1_CH3_OFFSET 0x0000b9c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYA1_CH3_OFFSET 0x0000bac0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x0000bb40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x0000bc00 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x0000bc40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x0000bc80 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x0000bcc0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x0000bd00 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x0000be00 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x0000c000 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x0000c100 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x0000c180 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH0_OFFSET 0x0000c1c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH0_OFFSET 0x0000c2c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x0000c340 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x0000c400 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x0000c440 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x0000c480 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x0000c4c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x0000c500 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x0000c600 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x0000c800 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x0000c900 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x0000c980 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH1_OFFSET 0x0000c9c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH1_OFFSET 0x0000cac0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x0000cb40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x0000cc00 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x0000cc40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x0000cc80 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x0000ccc0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x0000cd00 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x0000ce00 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x0000d000 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x0000d100 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x0000d180 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH2_OFFSET 0x0000d1c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH2_OFFSET 0x0000d2c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x0000d340 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x0000d400 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x0000d440 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x0000d480 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x0000d4c0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x0000d500 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x0000d600 +#define SEQ_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x0000d800 +#define SEQ_ZINC_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x0000d900 +#define SEQ_ZINC_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x0000d980 +#define SEQ_ZINC_RFA_CMN_WL_DAC_DIG_CORRECTION_PHYB_CH3_OFFSET 0x0000d9c0 +#define SEQ_ZINC_RFA_CMN_WL_DAC_MISC_PHYB_CH3_OFFSET 0x0000dac0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x0000db40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x0000dc00 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x0000dc40 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x0000dc80 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x0000dcc0 +#define SEQ_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x0000dd00 +#define SEQ_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x0000de00 /////////////////////////////////////////////////////////////////////////////////////////////// @@ -675,13 +1365,14 @@ #define SEQ_WCSSDBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00020000 #define SEQ_WCSSDBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00021000 #define SEQ_WCSSDBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00026000 -#define SEQ_WCSSDBG_PHYA_CPU0_AHB_AP_OFFSET 0x0002e000 -#define SEQ_WCSSDBG_PHYA_CPU1_AHB_AP_OFFSET 0x0002f000 +#define SEQ_WCSSDBG_PHYA_CPU0_M3_AHB_AP_OFFSET 0x0002e000 +#define SEQ_WCSSDBG_PHYA_CPU1_M3_AHB_AP_OFFSET 0x0002f000 #define SEQ_WCSSDBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00030000 #define SEQ_WCSSDBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00031000 #define SEQ_WCSSDBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00036000 -#define SEQ_WCSSDBG_PHYB_CPU0_AHB_AP_OFFSET 0x0003e000 -#define SEQ_WCSSDBG_UMAC_CPU_AHB_AP_OFFSET 0x00060000 +#define SEQ_WCSSDBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x0003e000 +#define SEQ_WCSSDBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00060000 +#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x00061000 /////////////////////////////////////////////////////////////////////////////////////////////// @@ -700,13 +1391,6 @@ #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000 -/////////////////////////////////////////////////////////////////////////////////////////////// -// Instance Relative Offsets from Block wrapper_acmt -/////////////////////////////////////////////////////////////////////////////////////////////// - -#define SEQ_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET 0x00000000 - - /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block qdsp6ss_public /////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/hw/qca8074/v1/wfss_ce_reg_seq_hwioreg.h b/hw/qca8074/v1/wfss_ce_reg_seq_hwioreg.h index b66ae4fffda2..93a31c383553 100644 --- a/hw/qca8074/v1/wfss_ce_reg_seq_hwioreg.h +++ b/hw/qca8074/v1/wfss_ce_reg_seq_hwioreg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -18,7 +18,7 @@ /////////////////////////////////////////////////////////////////////////////////////////////// // -// wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq 3.3 7/29/2016 +// wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 2/3/2017 // User Name:pgohil // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. @@ -50,7 +50,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -58,7 +58,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -72,7 +72,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -80,7 +80,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -92,12 +92,12 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) (x+0x00000008) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) (x+0x00000008) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0x000000ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x, mask, val) \ @@ -105,10 +105,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -122,7 +119,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUTM(x, mask, val) \ @@ -130,7 +127,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -147,7 +144,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x, mask, val) \ @@ -155,7 +152,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -184,7 +181,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -192,7 +189,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -206,7 +203,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -214,7 +211,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -228,7 +225,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -236,7 +233,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -256,7 +253,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -264,7 +261,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -278,7 +275,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -286,7 +283,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -301,12 +298,12 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -314,9 +311,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER //// @@ -328,7 +325,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -336,7 +333,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -350,7 +347,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -358,7 +355,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -375,7 +372,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -383,7 +380,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -397,7 +394,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -405,7 +402,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -422,7 +419,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -430,7 +427,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -439,12 +436,12 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -452,9 +449,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB //// @@ -466,7 +463,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -474,7 +471,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -488,7 +485,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -496,7 +493,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -513,7 +510,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x, mask, val) \ @@ -521,7 +518,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 @@ -538,7 +535,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUTM(x, mask, val) \ @@ -546,7 +543,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -563,7 +560,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x, mask, val) \ @@ -571,7 +568,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -600,7 +597,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ @@ -608,7 +605,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 @@ -622,7 +619,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ @@ -630,7 +627,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 @@ -644,7 +641,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ @@ -652,7 +649,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -672,7 +669,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ @@ -680,7 +677,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -695,12 +692,12 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000084) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000084) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ @@ -708,9 +705,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB //// @@ -722,7 +719,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -730,7 +727,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -744,7 +741,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -752,7 +749,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -769,7 +766,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -777,7 +774,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -786,12 +783,12 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000ac) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000ac) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -799,9 +796,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_CTRL //// @@ -813,7 +810,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x, mask, val) \ @@ -821,7 +818,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x00010000 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 @@ -838,7 +835,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x, mask, val) \ @@ -846,7 +843,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x00000020 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 @@ -875,7 +872,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x, mask, val) \ @@ -883,7 +880,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x00000008 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 @@ -906,7 +903,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x, mask, val) \ @@ -914,7 +911,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 @@ -928,7 +925,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x, mask, val) \ @@ -936,7 +933,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 @@ -950,7 +947,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x, mask, val) \ @@ -958,7 +955,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 @@ -972,7 +969,7 @@ #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x, mask, val) \ @@ -980,7 +977,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 @@ -999,7 +996,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x, mask, val) \ @@ -1007,7 +1004,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 @@ -1021,7 +1018,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x, mask, val) \ @@ -1029,7 +1026,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 @@ -1041,12 +1038,12 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) (x+0x00000008) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) (x+0x00000008) -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0x000000ff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x, mask, val) \ @@ -1054,10 +1051,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)); \ HWIO_INTFREE();\ - } while (0) - -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RING_ID_BMSK 0x0000ff00 -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RING_ID_SHFT 0x8 + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0x000000ff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 @@ -1071,7 +1065,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUTM(x, mask, val) \ @@ -1079,7 +1073,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 @@ -1096,7 +1090,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x, mask, val) \ @@ -1104,7 +1098,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 @@ -1133,7 +1127,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ @@ -1141,7 +1135,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 @@ -1155,7 +1149,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ @@ -1163,7 +1157,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 @@ -1177,7 +1171,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ @@ -1185,7 +1179,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 @@ -1205,7 +1199,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ @@ -1213,7 +1207,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 @@ -1227,7 +1221,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ @@ -1235,7 +1229,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 @@ -1250,12 +1244,12 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ @@ -1263,9 +1257,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER //// @@ -1277,7 +1271,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ @@ -1285,7 +1279,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 @@ -1299,7 +1293,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ @@ -1307,7 +1301,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 @@ -1324,7 +1318,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ @@ -1332,7 +1326,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 @@ -1346,7 +1340,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ @@ -1354,7 +1348,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 @@ -1371,7 +1365,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x, mask, val) \ @@ -1379,7 +1373,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 @@ -1388,12 +1382,12 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_SHFT 0 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ @@ -1401,9 +1395,9 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) -#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL //// @@ -1415,7 +1409,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x, mask, val) \ @@ -1423,7 +1417,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x00000010 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 @@ -1449,7 +1443,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x, mask, val) \ @@ -1457,7 +1451,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x00000010 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 @@ -1483,7 +1477,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x, mask, val) \ @@ -1491,7 +1485,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 @@ -1508,7 +1502,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x, mask, val) \ @@ -1516,7 +1510,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 @@ -1530,7 +1524,7 @@ #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask) #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, val) \ out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), val) #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x, mask, val) \ @@ -1538,7 +1532,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0x0000ffff #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 @@ -1557,7 +1551,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUTM(x, mask, val) \ @@ -1565,7 +1559,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xffffffff #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0x0 @@ -1579,7 +1573,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUTM(x, mask, val) \ @@ -1587,7 +1581,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0x000000ff #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0x0 @@ -1601,7 +1595,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUTM(x, mask, val) \ @@ -1609,7 +1603,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 @@ -1629,7 +1623,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ @@ -1637,7 +1631,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 @@ -1651,7 +1645,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ @@ -1659,7 +1653,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f @@ -1676,7 +1670,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUTM(x, mask, val) \ @@ -1684,7 +1678,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 @@ -1707,7 +1701,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUTM(x, mask, val) \ @@ -1715,7 +1709,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 @@ -1735,7 +1729,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ @@ -1743,7 +1737,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 @@ -1766,7 +1760,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ @@ -1774,7 +1768,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 @@ -1797,7 +1791,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x, mask, val) \ @@ -1805,7 +1799,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 @@ -1831,7 +1825,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ @@ -1839,7 +1833,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 @@ -1856,7 +1850,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUTM(x, mask, val) \ @@ -1864,7 +1858,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 @@ -1878,7 +1872,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ @@ -1886,7 +1880,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 @@ -1903,7 +1897,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x, mask, val) \ @@ -1911,7 +1905,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x01000000 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 0x18 @@ -1931,7 +1925,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x, mask, val) \ @@ -1939,7 +1933,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0x00000fff #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0x0 @@ -1953,7 +1947,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x, mask, val) \ @@ -1961,7 +1955,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0x00fff000 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 0xc @@ -1978,7 +1972,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x, mask, val) \ @@ -1986,7 +1980,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x01000000 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 0x18 @@ -2006,7 +2000,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x, mask, val) \ @@ -2014,7 +2008,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0x00000fff #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0x0 @@ -2028,7 +2022,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x, mask, val) \ @@ -2036,7 +2030,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xffffffff #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0x0 @@ -2050,7 +2044,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x, mask, val) \ @@ -2058,7 +2052,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0x00000001 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0x0 @@ -2072,7 +2066,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUTM(x, mask, val) \ @@ -2080,7 +2074,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xffffffff #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0x0 @@ -2094,7 +2088,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUTM(x, mask, val) \ @@ -2102,7 +2096,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xffffffff #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0x0 @@ -2116,7 +2110,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUTM(x, mask, val) \ @@ -2124,7 +2118,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xffffffff #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0x0 @@ -2138,7 +2132,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUTM(x, mask, val) \ @@ -2146,7 +2140,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xffffffff #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0x0 @@ -2160,7 +2154,7 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK) #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUTM(x, mask, val) \ @@ -2168,7 +2162,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_BMSK 0x80000000 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_SHFT 0x1f @@ -2188,6 +2182,28 @@ #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_BMSK 0x00000fff #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_SHFT 0x0 +//// Register WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR //// + +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x) (x+0x00000064) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_PHYS(x) (x+0x00000064) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_SHFT 0 +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_INM(x, mask) \ + in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUT(x, val) \ + out_dword( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), val) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_BMSK 0xffffffff +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_SHFT 0x0 + //// Register WFSS_CE_COMMON_R1_TESTBUS_CTRL //// #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x) (x+0x00000400) @@ -2197,7 +2213,7 @@ #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ @@ -2205,7 +2221,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0x000000ff #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0x0 @@ -2219,7 +2235,7 @@ #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK) #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ @@ -2227,7 +2243,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 @@ -2241,7 +2257,7 @@ #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK) #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ @@ -2249,7 +2265,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 @@ -2263,7 +2279,7 @@ #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUTM(x, mask, val) \ @@ -2271,7 +2287,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0x0 @@ -2285,7 +2301,7 @@ #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ @@ -2293,7 +2309,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0x0 @@ -2307,7 +2323,7 @@ #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ @@ -2315,7 +2331,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 @@ -2338,7 +2354,7 @@ #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x) \ in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK) #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, mask) \ - in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask) + in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask) #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, val) \ out_dword( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), val) #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ @@ -2346,7 +2362,7 @@ HWIO_INTLOCK(); \ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)); \ HWIO_INTFREE();\ - } while (0) + } while (0) #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0