From aec578f099567e91d6627a33293de7cd0ac7c115 Mon Sep 17 00:00:00 2001 From: Archana Sriram Date: Tue, 23 Feb 2021 12:39:12 +0530 Subject: [PATCH] msm: kgsl: Set correct values for SMMU protect register for A3xx For programming the CP Protect register for SMMU in A3xx GPU, pass correct values for SMMU registers base offset and the count of registers to be protected. Change-Id: I9fa809db79efc79bb7a59304fa2b4607ed1fc567 Signed-off-by: Archana Sriram --- drivers/gpu/msm/adreno_a3xx.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/msm/adreno_a3xx.c b/drivers/gpu/msm/adreno_a3xx.c index 8b3e872d06c0..b99023f3949e 100644 --- a/drivers/gpu/msm/adreno_a3xx.c +++ b/drivers/gpu/msm/adreno_a3xx.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -857,8 +857,14 @@ static struct { { A3XX_CP_PROTECT_REG_0 + 13, 0x0cc0, 0 }, /* VBIF */ { A3XX_CP_PROTECT_REG_0 + 14, 0x3000, 6 }, - /* SMMU */ - { A3XX_CP_PROTECT_REG_0 + 15, 0xa000, 12 }, + /* + * SMMU + * For A3xx, base offset for smmu region is 0xa000 and length is + * 0x1000 bytes. Offset must be in dword and length of the block + * must be ilog2(dword length). + * 0xa000 >> 2 = 0x2800, ilog2(0x1000 >> 2) = 10. + */ + { A3XX_CP_PROTECT_REG_0 + 15, 0x2800, 10 }, /* There are no remaining protected mode registers for a3xx */ };