From 3b21dd7bf7717d7f72eba5be74f36b67acb934d7 Mon Sep 17 00:00:00 2001
From: Krishna Manikandan <mkrishn@qti.qualcomm.com>
Date: Fri, 4 Sep 2020 09:41:30 +0530
Subject: [PATCH] ARM: dts: msm: add trusted vm dtsi files for shima target

Add trusted vm dt files for shima target. Common
device tree bindings for shima are inherited in
these files.

Change-Id: I67e2191f964e5193c84652c8a2064ff64aadcdff
---
 display/trustedvm-shima-sde.dtsi | 68 ++++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 display/trustedvm-shima-sde.dtsi

diff --git a/display/trustedvm-shima-sde.dtsi b/display/trustedvm-shima-sde.dtsi
new file mode 100644
index 000000000000..86166909fcd5
--- /dev/null
+++ b/display/trustedvm-shima-sde.dtsi
@@ -0,0 +1,68 @@
+#include "shima-sde-common.dtsi"
+#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
+
+&soc {
+	/* dummy display clock provider */
+	clock_cpucc: qcom,cpucc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "cpucc_clocks";
+		#clock-cells = <1>;
+	};
+};
+
+&mdss_mdp {
+	reg = <0xae00000 0x84208>,
+		<0xaeb0000 0x2008>,
+		<0xaeac000 0x214>,
+		<0xaf50000 0x038>;
+	reg-names = "mdp_phys",
+		"vbif_phys",
+		"regdma_phys",
+		"swfuse_phys";
+
+	qcom,sde-hw-version = <0x60070000>;
+	clocks =
+		<&clock_cpucc GCC_DISP_AHB_CLK>,
+		<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
+		<&clock_cpucc GCC_DISP_SF_AXI_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
+	clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
+			"iface_clk", "core_clk", "vsync_clk",
+			"lut_clk";
+	qcom,sde-trusted-vm-env;
+	qcom,vram-size = <0x200000>;
+};
+
+&mdss_dsi0 {
+	clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+		<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+		<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
+	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+			"pixel_clk", "pixel_clk_rcg", "esc_clk";
+};
+
+&mdss_dsi1 {
+	clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+		<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
+		<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
+		<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
+	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+			"pixel_clk", "pixel_clk_rcg", "esc_clk";
+};
+
+
+&mdss_dsi_phy0 {
+	qcom,dsi-pll-in-trusted-vm;
+};
+
+&mdss_dsi_phy1 {
+	qcom,dsi-pll-in-trusted-vm;
+};