From dafef6833197d9d2ca539f65804abfc2de03019d Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Thu, 24 Sep 2020 17:33:55 -0700 Subject: [PATCH 01/61] ARM: dts: msm: Update USB3 DP QMP Phy sequence for Lahaina to v1.10 Update the QMP USB3 DP PHY init sequence to v1.10 of the HSR. This is a minor update with only two register updates which addresses USB SuperSpeedPlus Gen2 RX compliance testing. Change-Id: I1f4de5c2657bb65861c94eadcde83a2cbe9be9ef --- qcom/lahaina-usb.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index c0b48ff2a264..919d251063d6 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -232,7 +232,7 @@ USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0 USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0 USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A 0 - USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0 + USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x03 0 USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0 USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0 USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0 @@ -278,7 +278,7 @@ USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0 USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0 USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21 0 - USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0 + USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x03 0 USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A 0 USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0 USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0 From 2ae24ea0e9af2a9bce545b381ccce04236f59a4a Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Thu, 8 Oct 2020 15:10:54 +0530 Subject: [PATCH 02/61] ARM: dts: msm: Add Bus voting support Add bus voting support for sdxlemur nand node. Change-Id: I2fc4e0aab98125353f49855fab9fffa7a014bae5 --- qcom/sdxlemur.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index dab380a836bb..1b50a41d8d5d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -400,6 +400,16 @@ clock-names = "core_clk"; clocks = <&rpmhcc RPMH_QPIC_CLK>; + interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>; + interconnect-names = "nand-ddr"; + qcom,msm-bus,name = "qpic_nand"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <0 0>, + /* Voting for max b/w on PNOC bus for now */ + <400000 400000>; + status = "disabled"; }; From 10a6c2d43182f7fb93e3ad13c02d6d10515bc043 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 21 Oct 2020 14:55:15 +0530 Subject: [PATCH 03/61] dt-bindings: LLCC: Add compatible property for Yupik Add "qcom,yupik-llcc" compatible property which matches the driver for Yupik platform. Change-Id: Ie95d00496deeab35bfe42c5c4f9b14b9daee70ce --- bindings/arm/msm/qcom,llcc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index 9d722dcf4c72..64e1fe37e270 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -13,6 +13,7 @@ Properties: Value type: Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,sdxlemur-llcc" + or "qcom,yupik-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: From 2a61ae11a60e8436a9154699cb9eb1910a5d5476 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 21 Oct 2020 15:10:49 +0530 Subject: [PATCH 04/61] ARM: dts: msm: Add LLCC entry for Yupik Add Last Level Cache Controller (LLCC) device tree node for Yupik. Change-Id: Ic6cda9514922f004dc1f8225c03ed0e3f8150855 --- qcom/yupik.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index d5d4682d9a13..080c7c5bd909 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -700,6 +700,15 @@ }; }; + cache-controller@9200000 { + compatible = "qcom,yupik-llcc","qcom,llcc-v2"; + reg = <0x9200000 0xd0000>, <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + clocks = <&aopcc QDSS_CLK>; + clock-names = "qdss_clk"; + }; + clk_virt: interconnect { compatible = "qcom,yupik-clk_virt"; #interconnect-cells = <1>; From 0883d0ce61866a3ec7f115729acc8569a2de3212 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Wed, 21 Oct 2020 19:33:12 +0530 Subject: [PATCH 05/61] ARM: dts: msm: Add ipcc test nodes for Yupik Add IPCC test nodes for adsp, cdsp for Yupik. This allows testing IPCC ping from APPS to these subsystems. Change-Id: Id7a9f5be7d827cf41fbf69d72aa28f4b50c14b79 --- qcom/ipcc-test-yupik.dtsi | 5 +++++ qcom/yupik.dtsi | 1 + 2 files changed, 6 insertions(+) create mode 100644 qcom/ipcc-test-yupik.dtsi diff --git a/qcom/ipcc-test-yupik.dtsi b/qcom/ipcc-test-yupik.dtsi new file mode 100644 index 000000000000..9809b5abf881 --- /dev/null +++ b/qcom/ipcc-test-yupik.dtsi @@ -0,0 +1,5 @@ +#include "ipcc-test.dtsi" + +&soc { + /delete-node/ ipcc-self-ping-slpi; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 080c7c5bd909..b12fe24ad080 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -773,6 +773,7 @@ #include "shima-gdsc.dtsi" #include "yupik-pinctrl.dtsi" #include "yupik-stub-regulator.dtsi" +#include "ipcc-test-yupik.dtsi" &gcc_pcie_0_gdsc { compatible = "regulator-fixed"; From 0fe1fb06058644710b63e6b5659b72a522f00382 Mon Sep 17 00:00:00 2001 From: NITHEESH MUTHURAJ Date: Tue, 13 Oct 2020 16:45:17 -0700 Subject: [PATCH 06/61] ARM: dts: msm: Add a new power level for supported devices Add speed bin node for efuse check and create speed bins to include TURBO_L2 on supported devices. Change-Id: I9ae248a599d53134b5e7b8a71ad109a34f1dfa0d --- qcom/lahaina-gpu.dtsi | 3 + qcom/lahaina-v2-gpu.dtsi | 435 ++++++++++++++++++++++++++++----------- qcom/lahaina.dtsi | 14 ++ 3 files changed, 330 insertions(+), 122 deletions(-) diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index 305d9f3b348f..34caf29704f3 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -51,6 +51,9 @@ qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; diff --git a/qcom/lahaina-v2-gpu.dtsi b/qcom/lahaina-v2-gpu.dtsi index 46b86a1604f0..194a286726f2 100644 --- a/qcom/lahaina-v2-gpu.dtsi +++ b/qcom/lahaina-v2-gpu.dtsi @@ -1,173 +1,364 @@ &msm_gpu { qcom,chipid = <0x06060001>; - qcom,initial-pwrlevel = <9>; + /delete-property/qcom,initial-pwrlevel; + /delete-node/qcom,gpu-pwrlevels; - /* Power levels */ - qcom,gpu-pwrlevels { + /* Power levels bins */ + qcom,gpu-pwrlevel-bins { + compatible="qcom,gpu-pwrlevel-bins"; #address-cells = <1>; #size-cells = <0>; - compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <0>; + qcom,initial-pwrlevel = <9>; - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <840000000>; - qcom,level = ; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <840000000>; + qcom,level = ; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,bus-freq-ddr8 = <11>; - qcom,bus-min-ddr8 = <11>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882a5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <778000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <738000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82a5ffd>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <676000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0x882b5ffd>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <608000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; + + qcom,acd-level = <0xa82b5ffd>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <540000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <491000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82c5ffd>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <443000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; - qcom,acd-level = <0x882a5ffd>; }; - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <778000000>; - qcom,level = ; + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <1>; + qcom,initial-pwrlevel = <10>; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <900000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <11>; - qcom,bus-min-ddr8 = <11>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82a5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <738000000>; - qcom,level = ; + qcom,acd-level = <0x882a5ffd>; + }; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <840000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <11>; - qcom,bus-min-ddr8 = <11>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82a5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <676000000>; - qcom,level = ; + qcom,acd-level = <0x882a5ffd>; + }; - qcom,bus-freq-ddr7 = <11>; - qcom,bus-min-ddr7 = <11>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <778000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <10>; - qcom,bus-min-ddr8 = <10>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0x882b5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <608000000>; - qcom,level = ; + qcom,acd-level = <0xa82a5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <7>; - qcom,bus-max-ddr7 = <11>; + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <738000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <7>; - qcom,bus-max-ddr8 = <11>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82b5ffd>; - }; + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <11>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <540000000>; - qcom,level = ; + qcom,acd-level = <0xa82a5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <7>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <676000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <7>; - qcom,bus-max-ddr8 = <9>; + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82c5ffd>; - }; + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <491000000>; - qcom,level = ; + qcom,acd-level = <0x882b5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <6>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <608000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <5>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <11>; - qcom,acd-level = <0xa82c5ffd>; - }; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <11>; - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <443000000>; - qcom,level = ; + qcom,acd-level = <0xa82b5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <6>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <540000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <7>; - qcom,bus-min-ddr8 = <5>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <10>; - qcom,acd-level = <0xa82d5ffd>; - }; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <379000000>; - qcom,level = ; + qcom,acd-level = <0xa82c5ffd>; + }; - qcom,bus-freq-ddr7 = <8>; - qcom,bus-min-ddr7 = <6>; - qcom,bus-max-ddr7 = <10>; + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <491000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <6>; - qcom,bus-min-ddr8 = <5>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; - qcom,acd-level = <0x882e5ffd>; - }; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; - qcom,gpu-pwrlevel@9 { - reg = <9>; - qcom,gpu-freq = <315000000>; - qcom,level = ; + qcom,acd-level = <0xa82c5ffd>; + }; - qcom,bus-freq-ddr7 = <2>; - qcom,bus-min-ddr7 = <2>; - qcom,bus-max-ddr7 = <9>; + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <443000000>; + qcom,level = ; - qcom,bus-freq-ddr8 = <2>; - qcom,bus-min-ddr8 = <2>; - qcom,bus-max-ddr8 = <7>; + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; - qcom,acd-level = <0x882f5ffd>; + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; + }; + + qcom,gpu-pwrlevel@9 { + reg = <9>; + qcom,gpu-freq = <379000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <10>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; + }; + + qcom,gpu-pwrlevel@10 { + reg = <10>; + qcom,gpu-freq = <315000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <2>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; + }; }; }; }; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 5a1ef7f0b987..87178b02c004 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5657,6 +5657,20 @@ qcom,use-ap-power-save; status = "disabled"; }; + + qfprom: qfprom@784000 { + compatible = "qcom,qfprom"; + reg = <0x784000 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + gpu_speed_bin: gpu_speed_bin@17b { + reg = <0x17b 0x1>; + bits = <5 3>; + }; + }; }; #include "ipcc-test.dtsi" From 95191f2f9d09de66cb90629680a88b502194f028 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 22 Oct 2020 09:59:35 +0530 Subject: [PATCH 07/61] ARM: dts: msm: Add core hang detection for Yupik Add qcom,core-hang-detect to device tree to enable MSM Core Hang Detection for all cores. Change-Id: I90907ab37a8c90512dd99b36c4f6e7b28ec60d08 --- qcom/yupik.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index b12fe24ad080..f3308be53bd5 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -700,6 +700,15 @@ }; }; + qcom,chd { + compatible = "qcom,core-hang-detect"; + label = "core"; + qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058 + 0x18040058 0x18050058 0x18060058 0x18070058>; + qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060 + 0x18040060 0x18050060 0x18060060 0x18070060>; + }; + cache-controller@9200000 { compatible = "qcom,yupik-llcc","qcom,llcc-v2"; reg = <0x9200000 0xd0000>, <0x9600000 0x50000>; From 373317c434752c7235cca3dba536644d9c342ea6 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 22 Oct 2020 10:19:37 +0530 Subject: [PATCH 08/61] ARM: dts: msm: Enable Kryo erp driver for Yupik Add Kryo error reporting device tree node for Yupik SOC. Change-Id: I34247cf9cfe69c3096ce583c4036dc6bc0295832 --- qcom/yupik.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index f3308be53bd5..1b351a0b7cf8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -709,6 +709,13 @@ 0x18040060 0x18050060 0x18060060 0x18070060>; }; + kryo-erp { + compatible = "arm,arm64-kryo-cpu-erp"; + interrupts = , + ; + interrupt-names = "l1-l2-faultirq","l3-scu-faultirq"; + }; + cache-controller@9200000 { compatible = "qcom,yupik-llcc","qcom,llcc-v2"; reg = <0x9200000 0xd0000>, <0x9600000 0x50000>; From 7c7cb1bae557b972bb4b4f495c8d01d7a6fff488 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 22 Oct 2020 10:40:50 +0530 Subject: [PATCH 09/61] ARM: dts: msm: Add ARM PMU node for Yupik Add ARM Performance Monitor Unit (PMU) device tree node for Yupik SOC. Change-Id: I8813c4cbaec2a4f58ae1ab48c80c866c4f38c7dc --- qcom/yupik.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 1b351a0b7cf8..386322742738 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -700,6 +700,12 @@ }; }; + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + qcom,chd { compatible = "qcom,core-hang-detect"; label = "core"; From ca2905c68e0fbdd43536c6905f562f02f90b7b2a Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 26 Oct 2020 15:27:56 -0700 Subject: [PATCH 10/61] dt-bindings: arm: msm: add MX entries for PCIe There are chipsets which require explicit votes for MX rails and its corners based on PCIe Gen speed. Add a entries for MX in DT so PCIe bus driver can properly vote and scale corners for MX. Change-Id: Ib7891ab528594f4f8a81568daafbe6297fcb60be --- bindings/pci/pci-msm.txt | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 8a9fa1e1c6fe..8d64a0fc0b9c 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -123,6 +123,7 @@ Main node - "vreg-1.8-supply" power supply for PCIe PHY - "vreg-0.9-supply" power supply for PCIe PHY - "vreg-cx-supply" power supply for PCIe core + - "vreg-mx-supply" power supply for PCIe core/PHY - "vreg-3.3-supply" (opt) power supply for PCIe endpoint - qcom,-voltage-level: @@ -134,8 +135,10 @@ Main node - qcom,bw-scale: Usage: optional Value type: - Definition: List of CX voltage corner and rate change clock frequency - pair for each PCIe GEN speed + Definition: Tuple consisting of CX and MX voltage corners, and rate + change clock frequencies for each supported PCIe Gen speed. + ex: + <[min CX voltage] [min MX voltage] [Rate change clk frequency]> interconnect-names: Usage: optional @@ -461,14 +464,30 @@ Example vreg-1.8-supply = <&pm8150l_l3>; vreg-0.9-supply = <&pm8150_l5>; vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; vreg-3.3-supply = <&pm8150_l1>; qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>; qcom,vreg-0.9-voltage-level = <950000 950000 24000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = ; /* Gen3 */ + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; From c64a98fe4e5df1407f156119c449db750a2716dc Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 26 Oct 2020 15:39:06 -0700 Subject: [PATCH 11/61] ARM: dts: msm: add MX entries to qcom,bw-scale for PCIe on lahaina Explicit MX voting and scaling is required for PCIe on some chipsets and there are updates to PCIe bus driver to support this. Although PCIe on lahaina does not need to explicitly vote for MX, updates to lahaina PCIe DT nodes are required to be compatible with the new qcom,bw-scale structure. Therefore, add MX entries to qcom,bw-scale for both PCIe nodes on lahaina. Change-Id: If707f61f78e4d99df118ebbfb516d639e5b4f851 --- qcom/lahaina-pcie.dtsi | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 9c106f0bd059..c72e6031377f 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -53,10 +53,18 @@ qcom,vreg-0p9-voltage-level = <880000 880000 47900>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen3 */ + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; @@ -284,10 +292,18 @@ qcom,vreg-0p9-voltage-level = <880000 880000 99000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen3 */ + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; From d2ee6936a7cd5b083152847f2939bb43bf3b68c9 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 27 Oct 2020 11:25:58 -0700 Subject: [PATCH 12/61] ARM: dts: msm: add MX entries to qcom,bw-scale for PCIe on shima Explicit MX voting and scaling is required for PCIe on some chipsets and there are updates to PCIe bus driver to support this. Although PCIe on shima does not need to explicitly vote for MX, updates to shima PCIe DT node are required to be compatible with the new qcom,bw-scale structure. Therefore, add MX entries to qcom,bw-scale for PCIe on shima. Change-Id: I4b93b92ee8e401c554e17e769432d3c22998ad98 --- qcom/shima-pcie.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 32573d6def76..eb3c0f409669 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -53,10 +53,18 @@ qcom,vreg-0p9-voltage-level = <880000 880000 47900>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen3 */ + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; From eb3c1b3847a5c0e806249c77f5bf3bd5f9fa2f53 Mon Sep 17 00:00:00 2001 From: Srinivas Rao L Date: Fri, 30 Oct 2020 20:38:31 +0530 Subject: [PATCH 13/61] ARM: dts: msm: Add Wakeup interrupt controller for scuba-iot Add wakeup interrupt controller node to support wakeup- capabale interrupts. Change-Id: Ibf4edc60adcdbeaf976cfb2eb97e689978d099d2 --- bindings/interrupt-controller/qcom,mpm.txt | 1 + qcom/scuba-iot.dtsi | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt index 1d5997bfb61c..257f2a7da9fc 100644 --- a/bindings/interrupt-controller/qcom,mpm.txt +++ b/bindings/interrupt-controller/qcom,mpm.txt @@ -24,6 +24,7 @@ Properties: Definition: Should contain "qcom,mpm-gic" and the respective target compatible flag from below ones. "qcom,mpm-gic-holi" + "qcom,mpm-gic-scuba" - interrupts: Usage: required diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 7ea545d63717..b9cb3f478e69 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -276,6 +276,17 @@ interrupts = <1 9 4>; }; + wakegic: wake-gic { + compatible = "qcom,mpm-gic-scuba", "qcom,mpm"; + interrupts = ; + reg = <0x45f01b8 0x1000>, + <0x0f40000c 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; timer { compatible = "arm,armv8-timer"; From 66008f5ae6e4b60671114d35ab558e7787471f0b Mon Sep 17 00:00:00 2001 From: Lingutla Chandrasekhar Date: Thu, 5 Nov 2020 16:08:32 +0530 Subject: [PATCH 14/61] ARM: dts: msm: Add dmips and dynamic power co-efficient for Yupik Add capacity-dmips-mhz and dynamic power coefficient for Yupik, these are used by Energy aware scheduler for taskplacement decisions. Change-Id: I922e56d3df8f9c1cfb40ab8cfd77366375875006 --- qcom/yupik.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index be693f53cd92..fe0bc64891df 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -63,6 +63,8 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -82,6 +84,8 @@ reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -96,6 +100,8 @@ reg = <0x0 0x200>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "arm,arch-cache"; @@ -110,6 +116,8 @@ reg = <0x0 0x300>; enable-method = "psci"; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "arm,arch-cache"; @@ -124,6 +132,8 @@ reg = <0x0 0x400>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "arm,arch-cache"; @@ -138,6 +148,8 @@ reg = <0x0 0x500>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "arm,arch-cache"; @@ -152,6 +164,8 @@ reg = <0x0 0x600>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "arm,arch-cache"; @@ -166,6 +180,8 @@ reg = <0x0 0x700>; enable-method = "psci"; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + capacity-dmips-mhz = <1985>; + dynamic-power-coefficient = <552>; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "arm,arch-cache"; From 9c620c73d1d00199c3ae3d84789cab7e96b8092e Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 9 Nov 2020 12:53:57 +0530 Subject: [PATCH 15/61] ARM: dts: msm: Change the node location for optimization for Shima Optimise for boot up time since it will use special node and dt property before unflat and put those in the beginning of the device tree can make it search fast. Also, bootloader need to update property in firmware, so move firmware node ahead can improve the bootloader search dt and update property time. Change-Id: I2fd58fdac57608b57a3996581397104168440ed0 --- qcom/shima.dtsi | 518 ++++++++++++++++++++++++------------------------ 1 file changed, 262 insertions(+), 256 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 8246b5473d9d..c042de94a110 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -31,7 +31,13 @@ #address-cells = <2>; #size-cells = <2>; + + chosen { + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + reserved_memory: reserved-memory { }; mem-offline { compatible = "qcom,mem-offline"; @@ -51,7 +57,9 @@ swr2 = &swr2; serial0 = &qupv3_se13_2uart; hsuart0 = &qupv3_se15_4uart; - }; + }; + + firmware: firmware {}; cpus { #address-cells = <2>; @@ -248,272 +256,270 @@ }; }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: hyp@80000000 { - no-map; - reg = <0x0 0x80000000 0x0 0x600000>; - }; - - xbl_aop_mem: xbl_aop_mem@80700000 { - no-map; - reg = <0x0 0x80700000 0x0 0x160000>; - }; - - cmd_db: reserved-memory@80860000 { - compatible = "qcom,cmd-db"; - no-map; - reg = <0x0 0x80860000 0x0 0x20000>; - }; - - reserved_xbl_uefi: reserved_xbl_uefi@80880000 { - no-map; - reg = <0x0 0x80880000 0x0 0x14000>; - }; - - smem_mem: smem@80900000 { - no-map; - reg = <0x0 0x80900000 0x0 0x200000>; - }; - - fw_mem: fw_mem@80b00000 { - no-map; - reg = <0x0 0x80b00000 0x0 0x100000>; - }; - - cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { - no-map; - reg = <0x0 0x80c00000 0x0 0x4600000>; - }; - - pil_camera_mem: camera@85800000 { - no-map; - reg = <0x0 0x85800000 0x0 0x500000>; - }; - - pil_video_mem: video@85d00000 { - no-map; - reg = <0x0 0x85d00000 0x0 0x500000>; - }; - - pil_cvp_mem: cvp@86200000 { - no-map; - reg = <0x0 0x86200000 0x0 0x500000>; - }; - - pil_adsp_mem: adsp@86700000 { - no-map; - reg = <0x0 0x86700000 0x0 0x2800000>; - }; - - pil_cdsp_mem: cdsp@88f00000 { - no-map; - reg = <0x0 0x88f00000 0x0 0x1e00000>; - }; - - adsp_mem: adsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0xC00000>; - }; - - pil_wlan_mem: wlan@8ad00000 { - no-map; - reg = <0x0 0x8ad00000 0x0 0xa00000>; - }; - - pil_ipa_fw_mem: ipa_fw@8b700000 { - no-map; - reg = <0x0 0x8b700000 0x0 0x10000>; - }; - - pil_ipa_gsi_mem: ipa_gsi@8b710000 { - no-map; - reg = <0x0 0x8b710000 0x0 0xa000>; - }; - - pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { - no-map; - reg = <0x0 0x8b71a000 0x0 0x2000>; - }; - - pil_mpss_wlan_mem: mpss_wlan@8b800000 { - no-map; - reg = <0x0 0x8b800000 0x0 0x10000000>; - }; - - removed_mem: removed_region@c0000000 { - no-map; - reg = <0x0 0xc0000000 0x0 0x5100000>; - }; - - pil_trustedvm_mem: pil_trustedvm_region@d0800000 { - no-map; - reg = <0x0 0xd0800000 0x0 0x76f7000>; - }; - - qrtr_shbuf: qrtr-shmem { - no-map; - reg = <0x0 0xd7ef7000 0x0 0x9000>; - }; - - chan0_shbuf: neuron_block@0 { - no-map; - reg = <0x0 0xd7f00000 0x0 0x80000>; - }; - - chan1_shbuf: neuron_block@1 { - no-map; - reg = <0x0 0xd7f80000 0x0 0x80000>; - }; - - user_contig_mem: user_contig_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - qseecom_mem: qseecom_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - qseecom_ta_mem: qseecom_ta_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - secure_display_memory: secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0xA000000>; - }; - - cnss_wlan_mem: cnss_wlan_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - qcom: ramoops { - compatible = "ramoops"; - reg = <0x0 0xa9000000 0x0 0x200000>; - pmsg-size = <0x200000>; - mem-type = <2>; - }; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; - linux,cma-default; - }; - - cdsp_mem: cdsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x400000>; - }; - - memshare_mem: memshare_region { - compatible = "shared-dma-pool"; - no-map; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - alignment = <0x0 0x100000>; - size = <0x0 0x800000>; - }; - - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - size = <0 0x2c00000>; - }; - - audio_cma_mem: audio_cma_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1C00000>; - }; - - splash_memory: splash_region { - reg = <0x0 0xe1000000 0x0 0x02300000>; - label = "cont_splash_region"; - }; - - dfps_data_memory: dfps_data_memory { - reg = <0x0 0xe3300000 0x0 0x0100000>; - label = "dfps_data_memory"; - }; - - non_secure_display_memory: non_secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x6400000>; - }; - }; - - chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; - }; soc: soc { }; - firmware: firmware { - scm { - compatible = "qcom,scm"; - qcom,dload-mode = <&tcsr 0x13000>; +}; + +&firmware { + scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; }; - android { - compatible = "android,firmware"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; - - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect,avb"; - status = "ok"; - }; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; }; }; }; }; +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: reserved-memory@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + reserved_xbl_uefi: reserved_xbl_uefi@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + + smem_mem: smem@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + fw_mem: fw_mem@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x4600000>; + }; + + pil_camera_mem: camera@85800000 { + no-map; + reg = <0x0 0x85800000 0x0 0x500000>; + }; + + pil_video_mem: video@85d00000 { + no-map; + reg = <0x0 0x85d00000 0x0 0x500000>; + }; + + pil_cvp_mem: cvp@86200000 { + no-map; + reg = <0x0 0x86200000 0x0 0x500000>; + }; + + pil_adsp_mem: adsp@86700000 { + no-map; + reg = <0x0 0x86700000 0x0 0x2800000>; + }; + + pil_cdsp_mem: cdsp@88f00000 { + no-map; + reg = <0x0 0x88f00000 0x0 0x1e00000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + pil_wlan_mem: wlan@8ad00000 { + no-map; + reg = <0x0 0x8ad00000 0x0 0xa00000>; + }; + + pil_ipa_fw_mem: ipa_fw@8b700000 { + no-map; + reg = <0x0 0x8b700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi@8b710000 { + no-map; + reg = <0x0 0x8b710000 0x0 0xa000>; + }; + + pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { + no-map; + reg = <0x0 0x8b71a000 0x0 0x2000>; + }; + + pil_mpss_wlan_mem: mpss_wlan@8b800000 { + no-map; + reg = <0x0 0x8b800000 0x0 0x10000000>; + }; + + removed_mem: removed_region@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x5100000>; + }; + + pil_trustedvm_mem: pil_trustedvm_region@d0800000 { + no-map; + reg = <0x0 0xd0800000 0x0 0x76f7000>; + }; + + qrtr_shbuf: qrtr-shmem { + no-map; + reg = <0x0 0xd7ef7000 0x0 0x9000>; + }; + + chan0_shbuf: neuron_block@0 { + no-map; + reg = <0x0 0xd7f00000 0x0 0x80000>; + }; + + chan1_shbuf: neuron_block@1 { + no-map; + reg = <0x0 0xd7f80000 0x0 0x80000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0xA000000>; + }; + + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qcom: ramoops { + compatible = "ramoops"; + reg = <0x0 0xa9000000 0x0 0x200000>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + cdsp_mem: cdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x2c00000>; + }; + + audio_cma_mem: audio_cma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1C00000>; + }; + + splash_memory: splash_region { + reg = <0x0 0xe1000000 0x0 0x02300000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_memory { + reg = <0x0 0xe3300000 0x0 0x0100000>; + label = "dfps_data_memory"; + }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x6400000>; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; From db099333eb07df542a96825b164a8b2c970daa4e Mon Sep 17 00:00:00 2001 From: Imran Ahmad Date: Tue, 3 Nov 2020 12:12:43 +0530 Subject: [PATCH 16/61] ARM: dts: msm: Include stub regulators for Monaco Include stub regulators for Monaco to allow consumers to register and vote for the regulators. Change-Id: Ib5d22709bb6e1e7ac324b0ab4b1d9cb337d39279 --- qcom/monaco-rumi.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index 58b95639be9e..d6ea70d56500 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -12,3 +12,5 @@ }; }; + +#include "monaco-stub-regulator.dtsi" From 9cc950721974f1658a0fdbbaebd0609fc8c74d8d Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 11 Nov 2020 17:23:18 +0800 Subject: [PATCH 17/61] dt-bindings: arm: Add FUSE and DBGUI support Add binding document for FUSE and DBGUI feature. Change-Id: I3908ba891f6d093b4ebeeedffbdbe4ff46bc3407 --- bindings/arm/coresight.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/arm/coresight.txt b/bindings/arm/coresight.txt index 1fadc1b562cc..fc00b47abcd6 100644 --- a/bindings/arm/coresight.txt +++ b/bindings/arm/coresight.txt @@ -101,6 +101,14 @@ its hardware characteristcs. - Coresight remote ETM: "qcom,coresight-remote-etm" + - Coresight dbgui device: + "qcom,coresight-dbgui" + + - Coresight fuse device: + "arm,coresight-fuse" + "arm,coresight-fuse-v2" + "arm,coresight-fuse-v3" + * port or ports: see "Graph bindings for Coresight" below. * Additional required property for coresight-tgu devices: From 92cec7f6a9c903b763cbb2c7d83ce4a08cac7dca Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 12 Nov 2020 11:21:58 -0800 Subject: [PATCH 18/61] ARM: dts: msm: Update PCIe PHY settings to v1.02 for sdxlemur Update PCIe PHY setting to version v1.02 based on hardware recommendation for sdxlemur. Change-Id: I3204ed8030f3f3e11a52d690794c4e04b93f3cca --- qcom/sdxlemur-pcie.dtsi | 52 +++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 35e34a9c4b2d..cfaf0f7cc936 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -95,7 +95,7 @@ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; - qcom,pcie-phy-ver = <1101>; + qcom,pcie-phy-ver = <1102>; qcom,phy-status-offset = <0x1214>; qcom,phy-status-bit = <7>; qcom,phy-power-down-offset = <0x1240>; @@ -147,43 +147,49 @@ 0x0a20 0x16 0x0 0x0bc0 0x38 0x0 0x0364 0xcc 0x0 + 0x0368 0x12 0x0 0x036c 0xcc 0x0 - 0x0378 0x31 0x0 + 0x0374 0x4a 0x0 + 0x0378 0x29 0x0 0x037c 0xc5 0x0 - 0x0380 0xcc 0x0 + 0x0380 0xac 0x0 0x0384 0xb6 0x0 - 0x0388 0xc2 0x0 - 0x038c 0x17 0x0 + 0x0388 0xc0 0x0 + 0x038c 0x07 0x0 0x0390 0xfb 0x0 - 0x0394 0x0f 0x0 + 0x0394 0x0d 0x0 + 0x0398 0xc5 0x0 0x039c 0xee 0x0 0x03a0 0xbf 0x0 - 0x03a4 0x80 0x0 + 0x03a4 0xa0 0x0 0x03a8 0x81 0x0 - 0x03ac 0xdf 0x0 - 0x03b0 0x5f 0x0 + 0x03ac 0xde 0x0 + 0x03b0 0x7f 0x0 0x0b64 0xcc 0x0 + 0x0b68 0x12 0x0 0x0b6c 0xcc 0x0 - 0x0b78 0x31 0x0 + 0x0b74 0x4a 0x0 + 0x0b78 0x29 0x0 0x0b7c 0xc5 0x0 - 0x0b80 0xcc 0x0 + 0x0b80 0xac 0x0 0x0b84 0xb6 0x0 - 0x0b88 0xc2 0x0 - 0x0b8c 0x17 0x0 + 0x0b88 0xc0 0x0 + 0x0b8c 0x07 0x0 0x0b90 0xfb 0x0 - 0x0b94 0x0f 0x0 + 0x0b94 0x0d 0x0 + 0x0b98 0xc5 0x0 0x0b9c 0xee 0x0 0x0ba0 0xbf 0x0 - 0x0ba4 0x80 0x0 + 0x0ba4 0xa0 0x0 0x0ba8 0x81 0x0 - 0x0bac 0xdf 0x0 - 0x0bb0 0x5f 0x0 + 0x0bac 0xde 0x0 + 0x0bb0 0x7f 0x0 0x03b4 0x20 0x0 0x022c 0x3f 0x0 - 0x0230 0x2d 0x0 + 0x0230 0x37 0x0 0x0bb4 0x20 0x0 0x0a2c 0x3f 0x0 - 0x0a30 0x2d 0x0 + 0x0a30 0x37 0x0 0x0078 0x05 0x0 0x007c 0xf6 0x0 0x0878 0x05 0x0 @@ -216,12 +222,12 @@ 0x0adc 0x0a 0x0 0x0308 0x0b 0x0 0x0b08 0x0b 0x0 - 0x027c 0x1f 0x0 - 0x0a7c 0x1f 0x0 + 0x027c 0x10 0x0 + 0x0a7c 0x10 0x0 0x02b4 0x00 0x0 0x0ab4 0x00 0x0 - 0x02ec 0x0d 0x0 - 0x0aec 0x0d 0x0 + 0x02ec 0x0f 0x0 + 0x0aec 0x0f 0x0 0x02c4 0x00 0x0 0x02c8 0x1f 0x0 0x0ac4 0x00 0x0 From 89db130d8d46284775595eea53cf067cb465f621 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Tue, 27 Oct 2020 14:00:23 +0530 Subject: [PATCH 19/61] ARM: dts: msm: Enable touch for Dual DSI video mode on shima Enable touch for Dual DSI video mode panel on shima target. Change-Id: I4d7316f34d6e9a2051213435bfe22a576e667ba7 --- qcom/shima-idp.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index dd34ac6cbd57..584af558244e 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -217,7 +217,8 @@ irq-gpios = <&tlmm 23 0x2008>; atmel,panel-coords = <0 0 479 799>; atmel,display-coords = <0 0 339 729>; - panel = <&dsi_sharp_qhd_plus_dsc_cmd>; + panel = <&dsi_sharp_qhd_plus_dsc_cmd + &dsi_sharp_qhd_plus_dsc_video>; }; }; From 1ce3af36b4f4e50507d868323105f72835786641 Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Mon, 9 Nov 2020 16:01:00 +0530 Subject: [PATCH 20/61] ARM: dts: msm: Change the node location for optimise Optimise for boot up time since it will use special node and dt property before unflat and put those in the beginning of the device tree can make it search fast. Change-Id: I655c0ff8ac720c16b61da680b8e389585b5a01a6 --- qcom/holi.dtsi | 341 +++++++++++++++++++++++++------------------------ 1 file changed, 172 insertions(+), 169 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e106fc3161c4..9487018bbdad 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -22,7 +22,13 @@ #address-cells = <2>; #size-cells = <2>; + + chosen { + bootargs = "log_buf_len=256K rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; + }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + reserved_memory: reserved-memory { }; mem-offline { compatible = "qcom,mem-offline"; @@ -238,173 +244,6 @@ }; }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: hyp@80000000 { - no-map; - reg = <0x0 0x80000000 0x0 0x600000>; - }; - - xbl_aop_mem: xbl_aop_mem@80700000 { - no-map; - reg = <0x0 0x80700000 0x0 0x160000>; - }; - - cmd_db: reserved-memory@80860000 { - no-map; - reg = <0x0 0x80860000 0x0 0x20000>; - }; - - smem_mem: smem@80900000 { - no-map; - reg = <0x0 0x80900000 0x0 0x200000>; - }; - - fw_mem: fw_mem@80b00000 { - no-map; - reg = <0x0 0x80b00000 0x0 0x100000>; - }; - - cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { - no-map; - reg = <0x0 0x80c00000 0x0 0x4600000>; - }; - - pil_wlan_mem: wlan@86500000 { - no-map; - reg = <0x0 0x86500000 0x0 0x200000>; - }; - - pil_adsp_mem: adsp@86700000 { - no-map; - reg = <0x0 0x86700000 0x0 0x2800000>; - }; - - pil_cdsp_mem: cdsp@88f00000 { - no-map; - reg = <0x0 0x88f00000 0x0 0x1e00000>; - }; - - pil_camera_mem: camera@8ad00000 { - no-map; - reg = <0x0 0x8ad00000 0x0 0x500000>; - }; - - pil_video_mem: video@8b200000 { - no-map; - reg = <0x0 0x8b200000 0x0 0x500000>; - }; - - pil_ipa_fw_mem: ipa_fw@8b700000 { - no-map; - reg = <0x0 0x8b700000 0x0 0x10000>; - }; - - pil_ipa_gsi_mem: ipa_gsi@8b710000 { - no-map; - reg = <0x0 0x8b710000 0x0 0xa000>; - }; - - pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { - no-map; - reg = <0x0 0x8b71a000 0x0 0x2000>; - }; - - pil_mpss_wlan_mem: mpss_wlan@8b800000 { - no-map; - reg = <0x0 0x8b800000 0x0 0x10000000>; - }; - - removed_mem: removed_region@c0000000 { - no-map; - reg = <0x0 0xc0000000 0x0 0x5100000>; - }; - - secure_display_memory: secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x5c00000>; - }; - - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - size = <0 0x800000>; - }; - - splash_memory: splash_region@0x85200000 { - reg = <0x0 0x85200000 0x0 0x00c00000>; - label = "cont_splash_region"; - }; - - dfps_data_memory: dfps_data_region@85e00000 { - reg = <0x0 0x85e00000 0x0 0x00100000>; - label = "dfps_data_region"; - }; - - qcom: ramoops { - compatible = "ramoops"; - reg = <0x0 0xd0000000 0x0 0x200000>; - pmsg-size = <0x200000>; - mem-type = <2>; - }; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; - linux,cma-default; - }; - - adsp_mem: adsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x800000>; - }; - - user_contig_mem: user_contig_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - qseecom_mem: qseecom_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - qseecom_ta_mem: qseecom_ta_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - memshare_mem: memshare_region { - compatible = "shared-dma-pool"; - no-map; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - alignment = <0x0 0x100000>; - size = <0x0 0x800000>; - }; - }; soc: soc { }; @@ -446,9 +285,173 @@ reg = <0x0 0x0 0x0 0x80>; }; }; +}; - chosen { - bootargs = "log_buf_len=256K rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: reserved-memory@80860000 { + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + smem_mem: smem@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + fw_mem: fw_mem@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x4600000>; + }; + + pil_wlan_mem: wlan@86500000 { + no-map; + reg = <0x0 0x86500000 0x0 0x200000>; + }; + + pil_adsp_mem: adsp@86700000 { + no-map; + reg = <0x0 0x86700000 0x0 0x2800000>; + }; + + pil_cdsp_mem: cdsp@88f00000 { + no-map; + reg = <0x0 0x88f00000 0x0 0x1e00000>; + }; + + pil_camera_mem: camera@8ad00000 { + no-map; + reg = <0x0 0x8ad00000 0x0 0x500000>; + }; + + pil_video_mem: video@8b200000 { + no-map; + reg = <0x0 0x8b200000 0x0 0x500000>; + }; + + pil_ipa_fw_mem: ipa_fw@8b700000 { + no-map; + reg = <0x0 0x8b700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi@8b710000 { + no-map; + reg = <0x0 0x8b710000 0x0 0xa000>; + }; + + pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { + no-map; + reg = <0x0 0x8b71a000 0x0 0x2000>; + }; + + pil_mpss_wlan_mem: mpss_wlan@8b800000 { + no-map; + reg = <0x0 0x8b800000 0x0 0x10000000>; + }; + + removed_mem: removed_region@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x5100000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x5c00000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x800000>; + }; + + splash_memory: splash_region@0x85200000 { + reg = <0x0 0x85200000 0x0 0x00c00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@85e00000 { + reg = <0x0 0x85e00000 0x0 0x00100000>; + label = "dfps_data_region"; + }; + + qcom: ramoops { + compatible = "ramoops"; + reg = <0x0 0xd0000000 0x0 0x200000>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; }; }; From 0529d8ca2f1c8310cd54f1aa6c33c0cd11cc3e24 Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Mon, 9 Nov 2020 16:35:19 +0530 Subject: [PATCH 21/61] ARM: dts: msm: Move firmware node ahead Bootloader need to update property in firmware, so move firmware node ahead can improve the bootloader search dt and update property time. Change-Id: Iae35be08cae1e514d6b6ad051e5e42137f99db8b --- qcom/holi.dtsi | 55 +++++++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 9487018bbdad..8053abd609dd 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -49,6 +49,8 @@ swr1 = &swr1; }; + firmware: firmware {}; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -244,35 +246,8 @@ }; }; - soc: soc { }; - firmware: firmware { - scm { - compatible = "qcom,scm"; - }; - - android { - compatible = "android,firmware"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect,avb"; - status = "ok"; - }; - }; - }; - }; - sram: sram@fd04480 { #address-cells = <2>; #size-cells = <2>; @@ -287,6 +262,32 @@ }; }; +&firmware { + scm { + compatible = "qcom,scm"; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; +}; + &reserved_memory { #address-cells = <2>; #size-cells = <2>; From 7a99e2e0d8e037a81ee7312e21e4b27cf4b454c5 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 14 Sep 2020 16:40:38 +0530 Subject: [PATCH 22/61] dt-bindings: clock: Add support for YUPIK clock controllers Update the GCC, GPUCC, CAMCC, DISPCC, VIDEOCC and debug clock controller bindings for YUPIK device. Change-Id: Id5e12fa1671030dc183b7a9cabda7a9dca198f52 --- bindings/clock/qcom,camcc.txt | 1 + bindings/clock/qcom,debugcc.txt | 1 + bindings/clock/qcom,dispcc.txt | 1 + bindings/clock/qcom,gcc.txt | 1 + bindings/clock/qcom,gpucc.txt | 11 ++++++----- bindings/clock/qcom,videocc.txt | 1 + 6 files changed, 11 insertions(+), 5 deletions(-) diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt index b9e3105751a5..cc72c85575d0 100644 --- a/bindings/clock/qcom,camcc.txt +++ b/bindings/clock/qcom,camcc.txt @@ -11,6 +11,7 @@ Required properties : "qcom,sm8150-camcc-v2" "qcom,sa8155-camcc" "qcom,sa8155-camcc-v2" + "qcom,yupik-camcc" - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index c7d82f90a3c8..59290aa6d1a4 100644 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -9,6 +9,7 @@ Required properties : "qcom,holi-debugcc" "qcom,sdxlemur-debugcc" "qcom,sm8150-debugcc" + "qcom,yupik-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index 80bbef3710ec..8341e8b8c742 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -11,6 +11,7 @@ Required properties : "qcom,holi-dispcc" "qcom,sm8150-dispcc" "qcom,sm8150-dispcc-v2" + "qcom,yupik-dispcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index f72a8ff537e6..c15e9b6800b7 100644 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -31,6 +31,7 @@ Required properties : "qcom,shima-gcc" "qcom,holi-gcc" "qcom,sdxlemur-gcc" + "qcom,yupik-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index 726c24257d24..efd611826979 100644 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -3,11 +3,12 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding Required properties : - compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc", - "qcom,lahaina-gpucc", - "qcom,shima-gpucc", - "qcom,holi-gpucc", - "qcom,sm8150-gpucc", - "qcom,sa8155-gpucc". + "qcom,lahaina-gpucc" + "qcom,shima-gpucc" + "qcom,holi-gpucc" + "qcom,sm8150-gpucc" + "qcom,sa8155-gpucc" + "qcom,yupik-gpucc" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,videocc.txt b/bindings/clock/qcom,videocc.txt index e46fa2db829b..64f41ad07942 100644 --- a/bindings/clock/qcom,videocc.txt +++ b/bindings/clock/qcom,videocc.txt @@ -11,6 +11,7 @@ Required properties : "qcom,sm8150-videocc-v2" "qcom,sa8155-videocc" "qcom,sa8155-videocc-v2" + "qcom,yupik-videocc" - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1. From 6638f17f131be817cf9bcf80d162874557e8c0e3 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Fri, 13 Nov 2020 16:04:36 -0800 Subject: [PATCH 23/61] ARM: dts: msm: Add eMMC device tree files for sdxlemur Add eMMC device tree files for sdxlemur. Change-Id: I834b09d948478862fe6191a62e3e8c8db2bb3eae --- qcom/sdxlemur-mtp-mbb-emmc.dts | 12 ++++++++++++ qcom/sdxlemur-mtp-mbb-emmc.dtsi | 6 ++++++ 2 files changed, 18 insertions(+) create mode 100644 qcom/sdxlemur-mtp-mbb-emmc.dts create mode 100644 qcom/sdxlemur-mtp-mbb-emmc.dtsi diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dts b/qcom/sdxlemur-mtp-mbb-emmc.dts new file mode 100644 index 000000000000..acdb4853a32a --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-emmc.dts @@ -0,0 +1,12 @@ +/dts v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-emmc.dtsi" +#include "sdxlemur-1024mb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x2010108 0> +}; diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi new file mode 100644 index 000000000000..768d9aaa521c --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -0,0 +1,6 @@ +#include "sdxlemur-pmic-overlay.dtsi" + +&soc { + +}; + From de5645824c27c1925164f3958ed221c3add4ae01 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 17 Nov 2020 08:25:43 -0800 Subject: [PATCH 24/61] ARM: dts: msm: Include sdxlemur-mtp dt on all mtp trees Added include statement for the sdxlemur-mtp device tree on all the mtp device trees. Change-Id: Id6e72b0095c36b0601d7046b72b49ba6e50f14ec --- qcom/sdxlemur-mtp-cpe.dtsi | 2 +- qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 2 +- qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 1 + qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 2 +- qcom/sdxlemur-mtp-mbb.dtsi | 2 +- 5 files changed, 5 insertions(+), 4 deletions(-) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 768d9aaa521c..e39236090d51 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -1,4 +1,4 @@ -#include "sdxlemur-pmic-overlay.dtsi" +#include "sdxlemur-mtp.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index 768d9aaa521c..e39236090d51 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -1,4 +1,4 @@ -#include "sdxlemur-pmic-overlay.dtsi" +#include "sdxlemur-mtp.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi index cc3a833f430e..e39236090d51 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-mtp.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index 768d9aaa521c..e39236090d51 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -1,4 +1,4 @@ -#include "sdxlemur-pmic-overlay.dtsi" +#include "sdxlemur-mtp.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index b0e02b918f81..25ea231003cb 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -1,5 +1,5 @@ -#include "sdxlemur-pmic-overlay.dtsi" #include "pm7250b.dtsi" +#include "sdxlemur-mtp.dtsi" &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; From 6f9c6f456548b65206336cff7309d3f9d085e5ef Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Mon, 9 Nov 2020 10:05:35 +0530 Subject: [PATCH 25/61] ARM: dts: msm: Add IOMMU Geometry property for storage Add IOMMU Geometry property to help save SMMU page table memory saving for UFS/eMMC. No functional change but helps saving memory table space. Change-Id: I94f9c4c58ca58f3491209bb8f12c1f080810dceb --- qcom/holi.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 34fd9f97a15b..3f6054571a56 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2111,6 +2111,23 @@ iommus = <&apps_smmu 0x60 0x0>; qcom,iommu-dma = "fastmap"; + /* + * iommu-dma-addr-pool- Indicate the range of data addresses which will be + * used in dma allocation. + * + * iommu-geometry - This is specific for fastmap which Allow clients + * to save SMMU page table memory. + * + * The 2nd parameter indicates size of the smmu page table memory. + * If its exceeds beyond this size, last unused entry from page table + * memory will be invalidated. + * + * It's better to provide range of dma address, hence provide + * iommu-dma-addr-pool property along with iommu-geometry property. + */ + + qcom,iommu-dma-addr-pool = <0x40000000 0x40000000>; + qcom,iommu-geometry = <0x40000000 0x40000000>; reset-gpios = <&tlmm 156 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_UFS_PHY_BCR>; @@ -2137,6 +2154,24 @@ iommus = <&apps_smmu 0x20 0x0>; qcom,iommu-dma = "fastmap"; + /* + * iommu-dma-addr-pool- Indicate the range of data addresses which will be + * used in dma allocation. + * + * iommu-geometry - This is specific for fastmap which Allow clients + * to save SMMU page table memory. + * + * The 2nd parameter indicates size of the smmu page table memory. + * If its exceeds beyond this size, last unused entry from page table + * memory will be invalidated. + * + * It's better to provide range of dma address, hence provide + * iommu-dma-addr-pool property along with iommu-geometry property. + */ + + qcom,iommu-dma-addr-pool = <0x40000000 0x40000000>; + qcom,iommu-geometry = <0x40000000 0x40000000>; + interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; From 1b866d34e2c5eb8f9597a9ae9f2bdaa8cec0935b Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 26 Oct 2020 17:10:28 -0700 Subject: [PATCH 26/61] ARM: dts: msm: add MX entries for PCIe on sdxlemur To properly support PCIe Gen4 on sdxlemur, PCIe needs to vote and scale MX rails accordingly. Add the required MX entries to enable PCIe bus driver to do so for sdxlemur. Change-Id: Ia56142013d07c9a811f5357e8ce29fdb3c76dd39 --- qcom/sdxlemur-pcie.dtsi | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 2ea8fedc36bb..2ab0fd2ceba7 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -46,15 +46,30 @@ vreg-1p8-supply = <&pmx65_l1>; vreg-0p9-supply = <&pmx65_l4>; vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; qcom,vreg-0p9-voltage-level = <912000 912000 132000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen4 */ + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; From d37c0931341137a01ea913b0c3c584bc31a7af34 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 27 Oct 2020 20:24:01 -0700 Subject: [PATCH 27/61] dt-bindings: arm: msm: add support for tuning PCIe EQ Master Phase Add DT entry to determine the minimum amount of time PCIe needs to remain in equalization master phase. Change-Id: I14f0e0b28dd69b8b38ac7be1cae282635ef11fe5 --- bindings/pci/pci-msm.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 6c6285f4e714..6f3e41eac5bc 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -290,6 +290,13 @@ interconnects: Definition: L1.2 LTR threshold value to be multipled with scale to define L1.2 latency tolerance reporting (LTR) +- qcom,eq-fmdc-t-min-phase23: + Usage: optional + Value type: + Definition: Determines minimum time (ms) to remain in equalization + master phase before checking for convergence of the + coefficients. + - qcom,slv-addr-space-size: Usage: required Value type: @@ -519,6 +526,7 @@ Example qcom,no-l1-supported; qcom,no-l1ss-supported; qcom,no-aux-clk-sync; + qcom,eq-fmdc-t-min-phase23 = <1>; /* 1ms */ qcom,slv-addr-space-size = <0x1000000>; /* 16MB */ qcom,wr-halt-size = <0xa>; /* 1KB */ qcom,tlp-rd-size = <0x5>; /* 4KB */ From 08a5b7bc69e8ee92fca57e0e1824f0ddd9cf87e3 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 27 Oct 2020 20:27:46 -0700 Subject: [PATCH 28/61] ARM: dts: msm: keep PCIe in EQ Master Phase for at least 1ms on sdxlemur PCIe PHY on sdxlemur requires the equalization master phase of link training to be at least 1ms long before proceeding to the next LTSSM state. Add the corresponding DT entry to configure the controller to meet this requirement on sdxlemur. Change-Id: Ied893d27cdc7a62c8a9284a9f16348ab8122094a --- qcom/sdxlemur-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 2ab0fd2ceba7..9e13fe07f23d 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -107,6 +107,7 @@ <0x100 &apps_smmu 0x0201 0x1>; qcom,aux-clk-freq = <17>; /* 16.6 MHz */ + qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; From fc54767186df903ef76cfcaf3315bf4773e8358d Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Wed, 11 Nov 2020 21:06:43 +0530 Subject: [PATCH 29/61] ARM: dts: msm: Remove display clock as client for CX SDPM for SHIMA Remove display clock as client for CX sdpm configuration for SHIMA as support not available. Change-Id: Ifabe6c7c5554179185e7a60cdc2dda0b3ec95619 --- qcom/shima-thermal.dtsi | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 0568cabd69b5..6a5999deec8b 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -79,14 +79,12 @@ cx_sdpm@0x00634000 { compatible = "qcom,sdpm"; reg = <0x00634000 0x1000>; - clock-names = "cam_cc_csi0phytiimer", "video_cc_mvs0", "disp_cc_mdss_mdp"; + clock-names = "cam_cc_csi0phytiimer", "video_cc_mvs0"; clocks = <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, - <&videocc VIDEO_CC_MVS0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&videocc VIDEO_CC_MVS0_CLK_SRC>; cam_cc_csi0phytiimer-supply = <&cam_cc_titan_top_gdsc>; video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; - disp_cc_mdss-mdp-supply = <&disp_cc_mdss_core_gdsc>; - csr-id = <0 2 5>; + csr-id = <0 2>; }; mx_pe: mx_rdpm_pe@0x00637000 { From 772f7eedab05a02fd04a5831bdbaa8eebdca578b Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 17 Nov 2020 00:28:27 +0530 Subject: [PATCH 30/61] ARM: dts: qcom: Update skin and cx thermal config for HOLI Add quiet-therm,pa-therm0 and xo-therm skin sensors thermal config for HOLI based on latest recomondations. Add q6-hvx sensor thermal config mitigation for HOLI based on latest recomondations. Change-Id: If534b2c11786f89e165f3bae28b1f4b8c927c1ce --- qcom/holi-qrd.dtsi | 201 +++++++++++++++++++++++++++++++++++++---- qcom/holi-thermal.dtsi | 35 +++---- 2 files changed, 199 insertions(+), 37 deletions(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 776be0b0286c..e941e3c47126 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -326,64 +326,231 @@ &thermal_zones { quiet-therm-step { - polling-delay-passive = <0>; + polling-delay-passive = <2000>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO4_100K_PU>; - trips { - quiet_modem_trip0: quiet-modem-trip0 { + battery_trip0: battery-trip0 { + temperature = <42000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip0: modem-skin-trip0 { temperature = <42000>; hysteresis = <4000>; type = "passive"; }; - quiet_modem_trip1: quiet-modem-trip1 { + gold_trip: gold-trip { + temperature = <43000>; + hysteresis = <0>; + type = "passive"; + }; + + battery_trip1: battery-trip1 { + temperature = <44000>; + hysteresis = <2000>; + type = "passive"; + }; + + modem_skin_trip1: modem-skin-trip1 { temperature = <44000>; hysteresis = <4000>; type = "passive"; }; - quiet_cx_trip: quiet-cx-trip { - temperature = <55000>; - hysteresis = <5000>; + silver_trip: silver-trip { + temperature = <45000>; + hysteresis = <0>; type = "passive"; }; - quiet_modem_trip2: quiet-modem-trip2 { - temperature = <56000>; + battery_trip2: battery-trip2 { + temperature = <46000>; hysteresis = <2000>; type = "passive"; }; + + battery_trip3: battery-trip3 { + temperature = <47000>; + hysteresis = <1000>; + type = "passive"; + }; + + battery_trip4: battery-trip4 { + temperature = <48000>; + hysteresis = <1000>; + type = "passive"; + }; + + cx_trip: cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; }; cooling-maps { - gpu-cdev { - trip = <&quiet_cx_trip>; + cdsp-cdev { + trip = <&cx_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + gpu-cdev0 { + trip = <&modem_skin_trip1>; + /* throttle to 650000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + gpu-cdev1 { + trip = <&cx_trip>; /* throttle to 565000000Hz */ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) (THERMAL_MAX_LIMIT-3)>; }; - cdsp-cdev0 { - trip = <&quiet_cx_trip>; - cooling-device = <&cdsp_sw 4 4>; + silver-cdev { + trip = <&silver_trip>; + /* throttle to 1478400KHz */ + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + + gold-cdev { + trip = <&gold_trip>; + /* throttle to 1536000KHz */ + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; modem-skin-cdev0 { - trip = <&quiet_modem_trip0>; + trip = <&modem_skin_trip0>; cooling-device = <&modem_skin 1 1>; }; modem-skin-cdev1 { - trip = <&quiet_modem_trip1>; + trip = <&modem_skin_trip1>; cooling-device = <&modem_skin 2 2>; }; modem-skin-cdev2 { - trip = <&quiet_modem_trip2>; + trip = <&cx_trip>; cooling-device = <&modem_skin 3 3>; }; + + battery-cdev0 { + trip = <&battery_trip0>; + cooling-device = <&pm7250b_charger 6 6>; + }; + + battery-cdev1 { + trip = <&battery_trip1>; + cooling-device = <&pm7250b_charger 10 10>; + }; + + battery-cdev2 { + trip = <&battery_trip2>; + cooling-device = <&pm7250b_charger 14 14>; + }; + + battery-cdev3 { + trip = <&battery_trip3>; + cooling-device = <&pm7250b_charger 16 16>; + }; + + battery-cdev4 { + trip = <&battery_trip4>; + cooling-device = <&pm7250b_charger 18 18>; + }; + }; + }; + + pa-therm0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_adc_tm ADC5_AMUX_THM3_100K_PU>; + trips { + modem_trip0: modem-trip0 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip1: modem-trip1 { + temperature = <47000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_trip2: modem-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem-cdev0 { + trip = <&modem_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + modem-cdev1 { + trip = <&modem_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + modem-cdev2 { + trip = <&modem_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; + + xo-therm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + trips { + modem_pa_fr1_trip0: modem-pa-fr1-trip0 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip1: modem-pa-fr1-trip1 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + modem_pa_fr1_trip2: modem-pa-fr1-trip2 { + temperature = <56000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_pa_fr1_cdev0 { + trip = <&modem_pa_fr1_trip0>; + cooling-device = <&modem_pa_fr1 1 1>; + }; + + modem_pa_fr1_cdev1 { + trip = <&modem_pa_fr1_trip1>; + cooling-device = <&modem_pa_fr1 2 2>; + }; + + modem_pa_fr1_cdev2 { + trip = <&modem_pa_fr1_trip2>; + cooling-device = <&modem_pa_fr1 3 3>; + }; }; }; }; diff --git a/qcom/holi-thermal.dtsi b/qcom/holi-thermal.dtsi index 13cb49406f32..c98479d3b71a 100644 --- a/qcom/holi-thermal.dtsi +++ b/qcom/holi-thermal.dtsi @@ -905,13 +905,13 @@ thermal-governor = "step_wise"; trips { - cdsp_trip0: cdsp-trip0 { + q6_hvx_trip0: q6-hvx-trip0 { temperature = <95000>; hysteresis = <0>; type = "passive"; }; - cdsp_cx_mon: cdsp-cx-mon { + q6_hvx_cx_mon: q6-hvx-cx-mon { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -919,32 +919,27 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&cdsp_trip0>; + q6-hvx-cdev0 { + trip = <&q6_hvx_trip0>; cooling-device = <&cdsp_sw THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; - cdsp-cx-cdev0 { - trip = <&cdsp_cx_mon>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + q6-hvx-cx-cdev0 { + trip = <&q6_hvx_cx_mon>; + /* throttle to 565000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; }; - cdsp-cx-cdev1 { - trip = <&cdsp_cx_mon>; - cooling-device = <&modem_tj 3 3>; + q6-hvx-cx-cdev1 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&modem_skin 3 3>; }; - cdsp-cx-cdev2 { - trip = <&cdsp_cx_mon>; - cooling-device = <&modem_pa 3 3>; - }; - - cdsp-cx-cdev3 { - trip = <&cdsp_cx_mon>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + q6-hvx-cx-cdev2 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&cdsp_sw 4 4>; }; }; }; From fd9c852a45e2f38a97fe542f6974e81665769c84 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Wed, 18 Nov 2020 12:47:56 -0800 Subject: [PATCH 31/61] ARM: dts: msm: Add PMX65 die temperature channel Add the appropriate ADC channel so that the pmx65_tz thermal zone may obtain the right value of PMIC die temperature for monitoring purposes. Change-Id: Ib67624ddcafc7e46d94e8b9ca83938bde32005b9 --- qcom/sdxlemur-pmic-overlay.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/sdxlemur-pmic-overlay.dtsi b/qcom/sdxlemur-pmic-overlay.dtsi index ea528c0ccbbf..36bac4c770ee 100644 --- a/qcom/sdxlemur-pmic-overlay.dtsi +++ b/qcom/sdxlemur-pmic-overlay.dtsi @@ -62,6 +62,14 @@ qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; + + pmx65_die_temp { + reg = ; + label = "pmx65_die_temp"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; }; &pmk8350_adc_tm { @@ -216,3 +224,8 @@ nvmem-cell-names = "restart_reason"; }; }; + +&pmx65_tz { + io-channels = <&pmk8350_vadc PMX65_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; From 6cdfb0dd43265e023d6f44c4bd4cd722ce0f82b1 Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Thu, 5 Nov 2020 15:48:18 +0530 Subject: [PATCH 32/61] ARM: dts: msm: Add QUPv3 SE and GPI DT nodes for yupik Add QUPv3(I2C, SPI and UART) and GPI DT node on yupik Change-Id: I6f62861c20f8c3778d087506efea75bd52957d78 --- qcom/yupik-pinctrl.dtsi | 1005 +++++++++++++++++++++++++++++++++++++++ qcom/yupik-qupv3.dtsi | 735 ++++++++++++++++++++++++++++ 2 files changed, 1740 insertions(+) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 01404eb41ded..acc672a31e62 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -9,6 +9,306 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup01"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "qup01"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio8", "gpio9"; + function = "qup02"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "qup02"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio12", "gpio13"; + function = "qup03"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "qup03"; + }; + + config { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio16", "gpio17"; + function = "qup04"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "qup04"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + qupv3_se5_2uart_pins: qupv3_se5_2uart_pins { qupv3_se5_2uart_active: qupv3_se5_2uart_active { mux { @@ -36,5 +336,710 @@ }; }; }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio24", "gpio25"; + function = "qup06"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "qup06"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_4uart_pins: qupv3_se7_4uart_pins { + qupv3_se7_default_cts: + qupv3_se7_default_cts { + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_default_rtsrx: + qupv3_se7_default_rtsrx { + mux { + pins = "gpio29", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio29", "gpio31"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se7_default_tx: + qupv3_se7_default_tx { + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_ctsrx: qupv3_se7_ctsrx { + mux { + pins = "gpio28", "gpio31"; + function = "qup07"; + }; + + config { + pins = "gpio28", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_rts: qupv3_se7_rts { + mux { + pins = "gpio29"; + function = "qup07"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se7_tx: qupv3_se7_tx { + mux { + pins = "gpio30"; + function = "qup07"; + }; + + config { + pins = "gpio30"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio32", "gpio33"; + function = "qup10"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "qup10"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio36", "gpio37"; + function = "qup11"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "qup11"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio40", "gpio41"; + function = "qup12"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio40", "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "qup12"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { + qupv3_se10_default_txrx: qupv3_se10_default_txrx { + mux { + pins = "gpio42", "gpio43"; + function = "qup12"; + }; + + config { + pins = "gpio42", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_2uart_active: qupv3_se6_2uart_active { + mux { + pins = "gpio42", "gpio43"; + function = "qup12"; + }; + + config { + pins = "gpio42", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep { + mux { + pins = "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio42", "gpio31"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio44", "gpio45"; + function = "qup13"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "qup13"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio48", "gpio49"; + function = "qup14"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio48", "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_active: qupv3_se12_spi_active { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "qup14"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio52", "gpio53"; + function = "qup15"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_active: qupv3_se13_spi_active { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "qup15"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio56", "gpio57"; + function = "qup16"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "qup16"; + }; + + config { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se14_2uart_pins: qupv3_se14_2uart_pins { + qupv3_se14_default_txrx: qupv3_se14_default_txrx { + mux { + pins = "gpio58", "gpio59"; + function = "qup16"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_2uart_active: qupv3_se14_2uart_active { + mux { + pins = "gpio58", "gpio59"; + function = "qup16"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_2uart_sleep: qupv3_se14_2uart_sleep { + mux { + pins = "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_active: qupv3_se15_i2c_active { + mux { + pins = "gpio60", "gpio61"; + function = "qup17"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio60", "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_active: qupv3_se15_spi_active { + mux { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + function = "qup17"; + }; + + config { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + drive-strength = <6>; + bias-disable; + }; + }; + }; }; }; diff --git a/qcom/yupik-qupv3.dtsi b/qcom/yupik-qupv3.dtsi index a593d4406eda..4d11215b0327 100644 --- a/qcom/yupik-qupv3.dtsi +++ b/qcom/yupik-qupv3.dtsi @@ -1,6 +1,25 @@ #include &soc { + /* QUPv3 SE Instances + * Qup1 0: SE 0 + * Qup1 1: SE 1 + * Qup1 2: SE 2 + * Qup1 3: SE 3 + * Qup1 4: SE 4 + * Qup1 5: SE 5 + * Qup1 6: SE 6 + * Qup1 7: SE 7 + * Qup0 0: SE 8 + * Qup0 1: SE 9 + * Qup0 2: SE 10 + * Qup0 3: SE 11 + * Qup0 4: SE 12 + * Qup0 5: SE 13 + * Qup0 6: SE 14 + * Qup0 7: SE 15 + */ + /* QUPv3_0 wrapper instance */ qupv3_0: qcom,qupv3_0_geni_se@9c0000 { compatible = "qcom,qupv3-geni-se"; @@ -16,6 +35,33 @@ status = "ok"; }; + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x900000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x136 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xff>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + /* Debug UART Instance */ qupv3_se5_2uart: qcom,qup_uart@994000 { compatible = "qcom,msm-geni-console"; @@ -32,4 +78,693 @@ qcom,wrapper-core = <&qupv3_0>; status = "ok"; }; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@980000 { + compatible = "qcom,spi-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@984000 { + compatible = "qcom,spi-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@990000 { + compatible = "qcom,spi-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@998000 { + compatible = "qcom,i2c-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@998000 { + compatible = "qcom,spi-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se7_4uart: qcom,qup_uart@99c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x99c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se7_default_cts>, + <&qupv3_se7_default_rtsrx>, <&qupv3_se7_default_tx>; + pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>; + pinctrl-2 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + iommus = <&apps_smmu 0x43 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x56 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xff>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + qupv3_se8_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se8_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_2uart: qcom,qup_uart@a88000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se10_default_txrx>; + pinctrl-1 = <&qupv3_se10_2uart_active>; + pinctrl-2 = <&qupv3_se10_2uart_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + dmas = <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + dmas = <&gpi_dma1 0 4 1 64 0>, + <&gpi_dma1 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + dmas = <&gpi_dma1 0 5 3 64 0>, + <&gpi_dma1 1 5 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + qcom,shared; + status = "disabled"; + }; + + qupv3_se13_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + dmas = <&gpi_dma1 0 5 1 64 0>, + <&gpi_dma1 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* Travel adapter over 2-wire HSUART, no wakeup */ + qupv3_se14_2uart: qcom,qup_uart@a98000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa98000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se14_default_txrx>; + pinctrl-1 = <&qupv3_se14_2uart_active>; + pinctrl-2 = <&qupv3_se14_2uart_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se14_i2c: i2c@a98000 { + compatible = "qcom,i2c-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + dmas = <&gpi_dma1 0 6 3 64 0>, + <&gpi_dma1 1 6 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se14_spi: spi@a98000 { + compatible = "qcom,spi-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + dmas = <&gpi_dma1 0 6 1 64 0>, + <&gpi_dma1 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@a9c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + dmas = <&gpi_dma1 0 7 3 64 0>, + <&gpi_dma1 1 7 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se15_spi: spi@a9c000 { + compatible = "qcom,spi-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + dmas = <&gpi_dma1 0 7 1 64 0>, + <&gpi_dma1 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; }; From 2a4c9134a26d55779461649ec4668af49b9918df Mon Sep 17 00:00:00 2001 From: Archit Saxena Date: Mon, 16 Nov 2020 17:30:27 +0530 Subject: [PATCH 33/61] ARM: dts: msm: Enable SMMU and PSCI for scuba Enable SMMU, PSCI and correct compatible string for scuba 32 bit target. Change-Id: Ie4b35e7609d851146af4bb42ff46ff6ceae8cfe2 --- qcom/msm-arm-smmu-scuba.dtsi | 2 -- qcom/scuba-iot-idp-overlay.dts | 2 +- qcom/scuba-iot.dtsi | 6 ++++++ 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/qcom/msm-arm-smmu-scuba.dtsi b/qcom/msm-arm-smmu-scuba.dtsi index 2876f6370a71..bb960362ef1a 100644 --- a/qcom/msm-arm-smmu-scuba.dtsi +++ b/qcom/msm-arm-smmu-scuba.dtsi @@ -2,7 +2,6 @@ &soc { kgsl_smmu: kgsl-smmu@0x59a0000 { - status = "disabled"; compatible = "qcom,qsmmu-v500"; reg = <0x59a0000 0x10000>, <0x59c2000 0x20>; @@ -40,7 +39,6 @@ }; apps_smmu: apps-smmu@0xc600000 { - status = "disabled"; compatible = "qcom,qsmmu-v500"; reg = <0xc600000 0x80000>, <0xc782000 0x20>; diff --git a/qcom/scuba-iot-idp-overlay.dts b/qcom/scuba-iot-idp-overlay.dts index 7f356c2e6abf..1121781ca5f1 100644 --- a/qcom/scuba-iot-idp-overlay.dts +++ b/qcom/scuba-iot-idp-overlay.dts @@ -6,7 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Scuba IDP"; - compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp"; + compatible = "qcom,scuba-idp", "qcom,scuba", "qcom,idp"; qcom,msm-id = <441 0x10000>, <471 0x10000>; qcom,board-id = <34 0>; }; diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index cd431074d371..82571a44c271 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -9,6 +9,8 @@ #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&intc>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; mem-offline { @@ -120,6 +122,10 @@ }; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; reserved-memory { #address-cells = <2>; From 9a381b30f80df711f5728cfb5b5d89c1b193562c Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 16 Nov 2020 12:27:36 +0530 Subject: [PATCH 34/61] ARM: dts: msm: Add scm pas node Add scm pas node for Yupik platform. Change-Id: Id1c1e3032a57a5aef617baa80eeacf4411bf6192 --- qcom/yupik.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index cc04ff320e6e..fdb89bb4acec 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1154,6 +1154,11 @@ qcom-secure-buffer { compatible = "qcom,secure-buffer"; }; + + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + }; }; #include "shima-gdsc.dtsi" From e3b04e8a9de01e77dab5baac52a954be29a3e245 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 29 Oct 2020 17:50:34 +0530 Subject: [PATCH 35/61] ARM: dts: msm: Add LPASS pil node for Yupik Add LPASS pil node to support LPASS subsystem for Yupik platform. Change-Id: I9d38b38f38e0fffa79844949d98fd9bf83ee6779 --- qcom/yupik.dtsi | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index fdb89bb4acec..5da945d70e97 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Yupik"; @@ -1159,6 +1160,52 @@ compatible = "qcom,pil-tz-scm-pas"; interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; }; + + qcom,lpass@3700000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x3700000 0x00100>; + + vdd_cx-supply = <&VDD_LPI_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_LPI_MX_LEVEL>; + qcom,vdd_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx","vdd_mx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,complete-ramdump; + + /* Inputs from lpass */ + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; }; #include "shima-gdsc.dtsi" From 775a317ccf30dbc4ec469789ec3f569ae79f2ffe Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 29 Oct 2020 18:05:26 +0530 Subject: [PATCH 36/61] ARM: dts: msm: Add CDSP pil node for Yupik Add CDSP pil node to support CDSP subsystem for Yupik. Change-Id: I9b21026a278aa3794e89ae5fac425a644035ab41 --- qcom/yupik.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 5da945d70e97..61a0912b69a1 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1206,6 +1206,54 @@ mboxes = <&qmp_aop 0>; mbox-names = "adsp-pil"; }; + + qcom,turing@a300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xa300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_MX_LEVEL>; + qcom,vdd_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx","vdd_mx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,complete-ramdump; + + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>, + <&cdsp_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; }; #include "shima-gdsc.dtsi" From f2d0535fb897c9d585edf28a66c1a40e4358f671 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Wed, 11 Nov 2020 17:00:24 +0530 Subject: [PATCH 37/61] ARM: dts: msm: Enable eMMC for sdxlemur target Enable eMMC for sdxlemur target. Change-Id: I984fec01e0b99b189d1f2e299239336e77af966d --- qcom/sdxlemur-mtp-mbb-emmc.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi index 768d9aaa521c..0e75a90da2b4 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dtsi +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -4,3 +4,30 @@ }; +&sdhc_1 { + reg = <0x08804000 0x1000>, <0x08805000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + bus-width = <8>; + non-removable; + supports-cqe; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L6B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 200000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "ok"; +}; From 7840876856aa1dbdb2f38bcb7cb6b68038ca0c01 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Thu, 12 Nov 2020 21:54:40 -0800 Subject: [PATCH 38/61] ARM: dts: msm: update pm7250b devices for sdxlemur platforms Add necessary configurations needed for charger, QG, PD_PHY devices present on PM7250B to support sdxlemur platforms that uses them. Since, it needs some VADC channels from PM7250B, add them as well. Change-Id: I065f1365b7278a92e0a8646a32e955d5e168c70c --- qcom/sdxlemur-mtp-mbb.dtsi | 161 ++++++++++++++++++++++++++++++++++++- qcom/sdxlemur-rcm-rc.dtsi | 159 +++++++++++++++++++++++++++++++++++- 2 files changed, 317 insertions(+), 3 deletions(-) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index c104dfebb64d..d477797ee914 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -1,5 +1,6 @@ -#include "pm7250b.dtsi" #include "sdxlemur-mtp.dtsi" +#include "pm7250b.dtsi" +#include &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; @@ -7,7 +8,10 @@ }; &soc { - + mbb_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + }; }; &pcie0 { @@ -47,3 +51,156 @@ status = "disabled"; }; + +&pm7250b_vadc { + charger_skin_therm { + reg = ; + label = "charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm7250b_charger { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,battery-data = <&mbb_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; + dpdm-supply = <&usb2_phy>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_qg { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,battery-data = <&mbb_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L10B>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 0eb9848df6f1..4293e321bd09 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -1,5 +1,6 @@ #include "sdxlemur-pmic-overlay.dtsi" #include "pm7250b.dtsi" +#include &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; @@ -7,7 +8,10 @@ }; &soc { - + rcm_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + }; }; &pcie0 { @@ -15,3 +19,156 @@ qcom,l1-2-th-scale = <2>; /* 1us */ qcom,l1-2-th-value = <70>; }; + +&pm7250b_vadc { + charger_skin_therm { + reg = ; + label = "charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm7250b_charger { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_qg PSY_IIO_RESISTANCE_ID>, + <&pm7250b_qg PSY_IIO_VOLTAGE_NOW>, + <&pm7250b_qg PSY_IIO_TEMP>, + <&pm7250b_qg PSY_IIO_CAPACITY>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_VOLTAGE_AVG>, + <&pm7250b_qg PSY_IIO_DEBUG_BATTERY>, + <&pm7250b_qg PSY_IIO_REAL_CAPACITY>, + <&pm7250b_qg PSY_IIO_CC_SOC>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>, + <&pm7250b_qg PSY_IIO_VOLTAGE_MAX>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL>, + <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, + <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, + <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,battery-data = <&rcm_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; + dpdm-supply = <&usb2_phy>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_qg { + #io-channel-cells = <1>; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>, + <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, + <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, + <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done"; + qcom,battery-data = <&rcm_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3300>; + qcom,bass-enable; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L10B>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + + #io-channel-cells = <1>; + io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>, + <&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_PR_SWAP>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_TYPEC_MODE>, + <&pm7250b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; From 1b2dafb3b21057e091e44fb38f7d975abd319d0c Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Thu, 19 Nov 2020 17:49:23 -0800 Subject: [PATCH 39/61] ARM: dts: msm: add spmi_debug_bus for sdxlemur Add spmi_debug_bus so that PMIC peripherals can be accessed via debug bus on sdxlemur devices where the fuse is not blown. This is useful for debugging. Change-Id: Ica647e8eee31028d25363aec88dd102cc0780ab6 --- qcom/sdxlemur-mtp-mbb.dtsi | 11 +++++++++++ qcom/sdxlemur-rcm-rc.dtsi | 11 +++++++++++ qcom/sdxlemur.dtsi | 28 ++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index d477797ee914..de785008447c 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -1,6 +1,7 @@ #include "sdxlemur-mtp.dtsi" #include "pm7250b.dtsi" #include +#include &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; @@ -14,6 +15,16 @@ }; }; +&spmi_debug_bus { + qcom,pm7250b-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + &pcie0 { qcom,boot-option = <0x1>; qcom,l1-2-th-scale = <2>; /* 1us */ diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 4293e321bd09..79a7e4a576da 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -1,6 +1,7 @@ #include "sdxlemur-pmic-overlay.dtsi" #include "pm7250b.dtsi" #include +#include &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; @@ -14,6 +15,16 @@ }; }; +&spmi_debug_bus { + qcom,pm7250b-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + &pcie0 { qcom,boot-option = <0x1>; qcom,l1-2-th-scale = <2>; /* 1us */ diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 6aa9e75a2eed..c761d1ea5c55 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -904,6 +905,33 @@ qcom,ee = <0>; }; + spmi_debug_bus: qcom,spmi-debug@6b12000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x6b12000 0x60>, <0x7820a8 0x4>; + reg-names = "core", "fuse"; + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + qcom,fuse-disable-bit = <24>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,pmk8350-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pmx65-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + thermal_zones: thermal-zones { }; From 156ccb23cf89a329f09dba621c1e2bc1236c9f61 Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Tue, 3 Nov 2020 12:45:35 +0530 Subject: [PATCH 40/61] ARM: dts: msm: add gfx smmu node on yupik Add the SMMU devicetree node for gfx that can be used by the respective clients for VA to PA translations. Change-Id: Ib0894591aff1be8fcdf50b0d57f7533efc67350c --- qcom/msm-arm-smmu-yupik.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/qcom/msm-arm-smmu-yupik.dtsi b/qcom/msm-arm-smmu-yupik.dtsi index 22ee8245eb6e..06c00b29cadf 100644 --- a/qcom/msm-arm-smmu-yupik.dtsi +++ b/qcom/msm-arm-smmu-yupik.dtsi @@ -2,7 +2,6 @@ &soc { kgsl_smmu: kgsl-smmu@3da0000 { - status = "disabled"; compatible = "qcom,qsmmu-v500"; reg = <0x3da0000 0x20000>, <0x3dd6000 0x20>; @@ -10,11 +9,30 @@ #iommu-cells = <2>; qcom,skip-init; qcom,use-3-lvl-tables; + qcom,split-tables; #global-interrupts = <2>; #size-cells = <1>; #address-cells = <1>; ranges; dma-coherent; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + interrupts = , , , @@ -43,7 +61,6 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; }; - }; apps_smmu: apps-smmu@15000000 { @@ -216,14 +233,13 @@ }; kgsl_iommu_test_device { - status = "disabled"; compatible = "iommu-debug-test"; iommus = <&kgsl_smmu 0x7 0>; qcom,iommu-dma = "disabled"; }; kgsl_iommu_coherent_test_device { - status = "disabled"; + status= "disabled"; compatible = "iommu-debug-test"; iommus = <&kgsl_smmu 0x407 0>; qcom,iommu-dma = "disabled"; From 650dbd60dc2b6ba30d6be4f14aa1ac0d30669039 Mon Sep 17 00:00:00 2001 From: Vishwanath Raju K Date: Wed, 11 Nov 2020 12:50:21 +0530 Subject: [PATCH 41/61] ARM: dts: msm: Add initial v1 memory map for Monaco Added initial memory map and created regured cma areas for monaco. Change-Id: I3355fa9b9ec9b95b658e8f252b238cde2294c7fa --- qcom/monaco.dtsi | 87 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index f33ea540e53e..864b5e1ab4eb 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -115,6 +115,93 @@ soc: soc { }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_region: hyp_region@45700000 { + no-map; + reg = <0x0 0x45700000 0x0 0x600000>; + }; + + rpmbackup_mem: rpmbackup_mem@45D00000 { + no-map; + reg = <0x0 0x45D00000 0x0 0x100000>; + }; + + xbl_aop_mem: xbl_aop_mem@45e00000 { + no-map; + reg = <0x0 0x45e00000 0x0 0x110000>; + }; + + sec_apps_mem: sec_apps_region@45fff000 { + no-map; + reg = <0x0 0x45fff000 0x0 0x1000>; + }; + + smem_region: smem@46000000 { + no-map; + reg = <0x0 0x46000000 0x0 0x200000>; + }; + + pil_modem_mem: modem_region@4ab00000 { + no-map; + reg = <0x0 0x4ab00000 0x0 0x6900000>; + }; + + pil_video_mem: pil_video_region@51400000 { + no-map; + reg = <0x0 0x51400000 0x0 0x500000>; + }; + + wlan_msa_mem: wlan_msa_region@51900000 { + no-map; + reg = <0x0 0x51900000 0x0 0x100000>; + }; + + pil_adsp_mem: adsp_regions@51a00000 { + no-map; + reg = <0x0 0x51a00000 0x0 0x1c00000>; + }; + + pil_ipa_fw_mem: ips_fw_region@53600000 { + no-map; + reg = <0x0 0x53600000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@53610000 { + no-map; + reg = <0x0 0x53610000 0x0 0x5000>; + }; + + pil_gpu_mem: gpu_region@53615000 { + no-map; + reg = <0x0 0x53615000 0x0 0x2000>; + }; + + removed_region: removed_region@5f800000 { + no-map; + reg = <0x0 0x5f800000 0x0 0x2700000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + chosen { bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; }; From 0cd8bc6a549ac46a94ea24adecd2a2914855dda7 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 18 Nov 2020 21:19:56 -0800 Subject: [PATCH 42/61] ARM: dts: msm: specify thermal mitigation levels for sdxlemur platforms Specify thermal mitigation levels for sdxlemur platforms based on the battery used. This is used to limit charging current when thermal SW requests different levels through charge_control_limit property in battery power supply. Change-Id: I2fe6142f110701b47d9f9f467a02632b20f1d7bb --- qcom/sdxlemur-mtp-mbb.dtsi | 1 + qcom/sdxlemur-rcm-rc.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index d477797ee914..150af268d702 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -130,6 +130,7 @@ qcom,fcc-stepping-enable; qcom,fcc-step-delay-ms = <100>; qcom,fcc-step-size-ua = <100000>; + qcom,thermal-mitigation = <3600000 3000000 1500000 1000000 500000>; qcom,smb-internal-pull-kohm = <0>; qcom,en-skin-therm-mitigation; qcom,hvdcp3-standalone-config; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 4293e321bd09..9790544a1f02 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -98,6 +98,7 @@ qcom,fcc-stepping-enable; qcom,fcc-step-delay-ms = <100>; qcom,fcc-step-size-ua = <100000>; + qcom,thermal-mitigation = <3600000 3000000 1500000 1000000 500000>; qcom,smb-internal-pull-kohm = <0>; qcom,en-skin-therm-mitigation; qcom,hvdcp3-standalone-config; From 55aba0a4a2145be1cf0131508d8d8d3a09c2df7b Mon Sep 17 00:00:00 2001 From: Vishwanath Raju K Date: Wed, 11 Nov 2020 14:15:14 +0530 Subject: [PATCH 43/61] ARM: dts: msm: Add ion heap for monaco Describe the memory region reserved for the ion allocator. Change-Id: I53ce5c36dc77909fdbd8e1b2b24bd7292e6ef728 --- qcom/monaco-ion.dtsi | 17 +++++++++++++++++ qcom/monaco.dtsi | 2 ++ 2 files changed, 19 insertions(+) create mode 100644 qcom/monaco-ion.dtsi diff --git a/qcom/monaco-ion.dtsi b/qcom/monaco-ion.dtsi new file mode 100644 index 000000000000..a0a50ce4dbd2 --- /dev/null +++ b/qcom/monaco-ion.dtsi @@ -0,0 +1,17 @@ +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + system_secure_heap: qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 864b5e1ab4eb..cc7e290d0da2 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -474,3 +474,5 @@ }; #include "monaco-pinctrl.dtsi" +#include "monaco-ion.dtsi" + From 3e646840d9b13a7c0fac6ad7703d2ea7bc76f414 Mon Sep 17 00:00:00 2001 From: nishant chaubey Date: Fri, 20 Nov 2020 13:32:49 +0530 Subject: [PATCH 44/61] ARM: dts: msm: Reduce secure heap to 30MB 30MB memory is sufficient for fastrpc securepd usecase. Reduce secure heap to 30MB. Change-Id: Ic680bfb74ff6ac37925a2c9b4edae275acc9d260 --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 28c75c04dada..47a95eaeb137 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -320,7 +320,7 @@ cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { no-map; - reg = <0x0 0x80c00000 0x0 0x4600000>; + reg = <0x0 0x80c00000 0x0 0x1e00000>; }; pil_wlan_mem: wlan@86500000 { From be1f95bbcdeda891892b6a47a307d9de52f99630 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Fri, 20 Nov 2020 12:52:42 -0800 Subject: [PATCH 45/61] ARM: dts: msm: Disable PMX65 VBUS_DET on sdxlemur MTP-MBB and RCM-RC boards On these boards, VBUS detection is through PM7250B, so disable the VBUS_DET peripheral. Change-Id: If408b620c296df6bf1fbfeafb96b3e720de83114 --- qcom/sdxlemur-mtp-mbb.dtsi | 4 ++++ qcom/sdxlemur-rcm-rc.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index d477797ee914..c28a01a0a5fe 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -204,3 +204,7 @@ "typec_mode", "pe_start"; }; + +&vbus_detect { + status = "disabled"; +}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 4293e321bd09..b5cd20db732c 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -172,3 +172,7 @@ "typec_mode", "pe_start"; }; + +&vbus_detect { + status = "disabled"; +}; From b625000a5d446a100da0f81cebee93f444d32e6d Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Thu, 19 Nov 2020 11:44:59 -0800 Subject: [PATCH 46/61] ARM: dts: msm: Add missing memory map region for sdxlemur Correct the memory map to match version 1. Change-Id: I2da959263e0d0805b75ecc78c79b76ffaa08f41b --- qcom/sdxlemur-512mb.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur-512mb.dtsi b/qcom/sdxlemur-512mb.dtsi index 4e48c97523d0..29098f1f0707 100644 --- a/qcom/sdxlemur-512mb.dtsi +++ b/qcom/sdxlemur-512mb.dtsi @@ -46,6 +46,11 @@ reg = <0x8fced000 0x10000>; }; + tz_heap_mem: tz_heap_region@8fcad000 { + no-map; + reg = <0x8fcad000 0x40000>; + }; + mpss_dsm: mpss_dsm_region@8c400000 { no-map; reg = <0x8c400000 0x3200000>; From 03fea8ad8a0cf1f964e8f0efcb6bf2e10a307d92 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Thu, 24 Sep 2020 14:42:14 +0530 Subject: [PATCH 47/61] ARM: dts: msm: Update GCC clock node and GDSC for YUPIK Update the global clock controller node and the corresponding GDSC's of YUPIK. While at it, move the qcom,retain-regs property from platform specific shima dtsi file to generic shima gdsc dtsi file which is used by SHIMA and YUPIK. Change-Id: Idbeea95e2a5c2cf7ac69b1f764325b2464713b18 --- qcom/shima-gdsc.dtsi | 19 +++++++++++++++++++ qcom/shima.dtsi | 17 ----------------- qcom/yupik-rumi.dtsi | 4 ++++ qcom/yupik.dtsi | 18 ++++++------------ 4 files changed, 29 insertions(+), 29 deletions(-) diff --git a/qcom/shima-gdsc.dtsi b/qcom/shima-gdsc.dtsi index d6d058295306..0686c9dfeb67 100644 --- a/qcom/shima-gdsc.dtsi +++ b/qcom/shima-gdsc.dtsi @@ -6,6 +6,7 @@ regulator-name = "gcc_pcie_0_gdsc"; qcom,gds-timeout = <500>; qcom,no-status-check-on-disable; + qcom,retain-regs; status = "disabled"; }; @@ -15,6 +16,7 @@ regulator-name = "gcc_pcie_1_gdsc"; qcom,gds-timeout = <500>; qcom,no-status-check-on-disable; + qcom,retain-regs; status = "disabled"; }; @@ -22,6 +24,7 @@ compatible = "qcom,gdsc"; reg = <0x177004 0x4>; regulator-name = "gcc_ufs_phy_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -29,6 +32,7 @@ compatible = "qcom,gdsc"; reg = <0x10f004 0x4>; regulator-name = "gcc_usb30_prim_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -36,6 +40,7 @@ compatible = "qcom,gdsc"; reg = <0x19e004 0x4>; regulator-name = "gcc_usb30_sec_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -116,6 +121,7 @@ compatible = "qcom,gdsc"; reg = <0xad0c120 0x4>; regulator-name = "cam_cc_titan_top_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -123,6 +129,7 @@ compatible = "qcom,gdsc"; reg = <0xad07004 0x4>; regulator-name = "cam_cc_bps_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -130,6 +137,7 @@ compatible = "qcom,gdsc"; reg = <0xad0a004 0x4>; regulator-name = "cam_cc_ife_0_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -137,6 +145,7 @@ compatible = "qcom,gdsc"; reg = <0xad0b004 0x4>; regulator-name = "cam_cc_ife_1_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -144,6 +153,7 @@ compatible = "qcom,gdsc"; reg = <0xad0b070 0x4>; regulator-name = "cam_cc_ife_2_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -151,6 +161,7 @@ compatible = "qcom,gdsc"; reg = <0xad08004 0x4>; regulator-name = "cam_cc_ipe_0_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -161,6 +172,7 @@ regulator-name = "disp_cc_mdss_core_gdsc"; proxy-supply = <&disp_cc_mdss_core_gdsc>; qcom,proxy-consumer-enable; + qcom,retain-regs; status = "disabled"; }; @@ -186,6 +198,7 @@ regulator-name = "gpu_cx_gdsc"; hw-ctrl-addr = <&gpu_cx_hw_ctrl>; qcom,no-status-check-on-disable; + qcom,retain-regs; status = "disabled"; }; @@ -196,6 +209,7 @@ sw-reset = <&gpu_gx_sw_reset>; domain-addr = <&gpu_gx_domain_addr>; qcom,reset-aon-logic; + qcom,retain-regs; status = "disabled"; }; @@ -204,6 +218,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0d18 0x4>; regulator-name = "video_cc_mvs0_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -211,6 +226,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0bf8 0x4>; regulator-name = "video_cc_mvs0c_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -218,6 +234,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0d98 0x4>; regulator-name = "video_cc_mvs1_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -225,6 +242,7 @@ compatible = "qcom,gdsc"; reg = <0xabf0c98 0x4>; regulator-name = "video_cc_mvs1c_gdsc"; + qcom,retain-regs; status = "disabled"; }; @@ -232,6 +250,7 @@ compatible = "qcom,gdsc"; reg = <0xaaf2004 0x4>; regulator-name = "video_cc_mvsc_gdsc"; + qcom,retain-regs; status = "disabled"; }; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 44ab78339e3f..0fef6712174d 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3890,22 +3890,18 @@ }; &gcc_pcie_0_gdsc { - qcom,retain-regs; status = "ok"; }; &gcc_pcie_1_gdsc { - qcom,retain-regs; status = "ok"; }; &gcc_ufs_phy_gdsc { - qcom,retain-regs; status = "ok"; }; &gcc_usb30_prim_gdsc { - qcom,retain-regs; status = "ok"; }; @@ -3945,7 +3941,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3954,7 +3949,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3962,7 +3956,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3970,7 +3963,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3978,7 +3970,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3987,7 +3978,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -3996,7 +3986,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -4004,7 +3993,6 @@ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -4012,7 +4000,6 @@ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_GFX_LEVEL>; - qcom,retain-regs; qcom,skip-disable-before-sw-enable; status = "ok"; }; @@ -4022,7 +4009,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -4030,7 +4016,6 @@ clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -4039,7 +4024,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; @@ -4047,7 +4031,6 @@ clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - qcom,retain-regs; status = "ok"; }; diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 1efb6b32bfaa..3cf06415ef73 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -75,3 +75,7 @@ &qupv3_se5_2uart { qcom,rumi_platform; }; + +&gcc { + clocks = <&bi_tcxo>, <&sleep_clk>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 59808e07e047..317092da3274 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -600,8 +600,12 @@ }; gcc: clock-controller@100000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,yupik-gcc", "syscon"; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1304,56 +1308,46 @@ #include "ipcc-test-yupik.dtsi" &gcc_pcie_0_gdsc { - compatible = "regulator-fixed"; qcom,support-hw-trigger; status = "ok"; }; &gcc_pcie_1_gdsc { - compatible = "regulator-fixed"; qcom,support-hw-trigger; status = "ok"; }; &gcc_ufs_phy_gdsc { - compatible = "regulator-fixed"; qcom,support-hw-trigger; status = "ok"; }; &gcc_usb30_prim_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &gcc_usb30_sec_gdsc { - compatible = "regulator-fixed"; qcom,support-hw-trigger; status = "ok"; }; &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &hlos1_vote_turing_mmu_tbu0_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &hlos1_vote_turing_mmu_tbu1_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; From 6719abb50ee49f345d74cc0c2fa2d83ab24d7610 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Tue, 27 Oct 2020 10:35:49 +0530 Subject: [PATCH 48/61] ARM: dts: msm: Update GPUCC clock node and GDSC for YUPIK Update GPUCC clock node and corresponding GDSC's for YUPIK. Change-Id: Ib5c4e21fa3e8da086689c16a3f766a869d459969 --- qcom/yupik-rumi.dtsi | 7 +++++++ qcom/yupik.dtsi | 22 ++++++++++++++++++---- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 3cf06415ef73..138f7c0482f8 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -1,3 +1,5 @@ +#include + &soc { timer { clock-frequency = <5000000>; @@ -79,3 +81,8 @@ &gcc { clocks = <&bi_tcxo>, <&sleep_clk>; }; + +&gpucc { + clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 317092da3274..53621f3c4afc 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -625,8 +625,15 @@ }; gpucc: clock-controller@3d90000 { - compatible = "qcom,dummycc"; - clock-output-names = "gpucc_clocks"; + compatible = "qcom,yupik-gpucc", "syscon"; + reg = <0x3d90000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src", "cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1392,12 +1399,19 @@ }; &gpu_cx_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; &gpu_gx_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_GFX_LEVEL>; + qcom,retain-regs; + qcom,skip-disable-before-sw-enable; status = "ok"; }; From 696feed44ec4cf74380fc0ee1bf94069f951316b Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Sun, 22 Nov 2020 10:59:45 +0530 Subject: [PATCH 49/61] ARM: dts: msm: Disable scaling for SD and eMMC on sdxlemur Disable scaling for SD and eMMC as for SD card the clocks were not getting scaled properly. Change-Id: Ic90f783ad141a9cb8e8bde10aacfd365aac3b3dc --- qcom/sdxlemur.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 6aa9e75a2eed..fde7c5e79304 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -459,8 +459,6 @@ /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; - qcom,devfreq,freq-table = <50000000 200000000>; - status = "disabled"; qos0 { From 17cf51a99a48a15167de8d38a156024865ea9eaa Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Tue, 27 Oct 2020 17:12:35 +0530 Subject: [PATCH 50/61] ARM: dts: msm: Add dummy clock nodes for MONACO Dummy clock nodes are required for clocks client to request, so add support for the same. Also add the dummy GDSCs required by clients for monaco. Change-Id: I16e204fb2c04cbe750db25af4364a8af0b252404 --- qcom/monaco-gdsc.dtsi | 91 +++++++++++++++++++++++++++++++++++++ qcom/monaco.dtsi | 101 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 192 insertions(+) create mode 100644 qcom/monaco-gdsc.dtsi diff --git a/qcom/monaco-gdsc.dtsi b/qcom/monaco-gdsc.dtsi new file mode 100644 index 000000000000..e1bf1597ede3 --- /dev/null +++ b/qcom/monaco-gdsc.dtsi @@ -0,0 +1,91 @@ +&soc { + /* GDSCs in GCC */ + gcc_camss_top_gdsc: qcom,gdsc@1458004 { + compatible = "regulator-fixed"; + reg = <0x1458004 0x4>; + regulator-name = "gcc_camss_top_gdsc"; + status = "disabled"; + }; + + gcc_usb20_prim_gdsc: qcom,gdsc@141c004 { + compatible = "regulator-fixed"; + reg = <0x141c004 0x4>; + regulator-name = "gcc_usb20_prim_gdsc"; + status = "disabled"; + }; + + gcc_vcodec0_gdsc: qcom,gdsc@14580a8 { + compatible = "regulator-fixed"; + reg = <0x14580a8 0x4>; + regulator-name = "gcc_vcodec0_gdsc"; + status = "disabled"; + }; + + gcc_venus_gdsc: qcom,gdsc@1458084 { + compatible = "regulator-fixed"; + reg = <0x1458084 0x4>; + regulator-name = "gcc_venus_gdsc"; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 { + compatible = "regulator-fixed"; + reg = <0x147d078 0x4>; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 { + compatible = "regulator-fixed"; + reg = <0x147d074 0x4>; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + /* GDSCs in DISPCC */ + mdss_core_gdsc: qcom,gdsc@5f03000 { + compatible = "regulator-fixed"; + reg = <0x5f03000 0x4>; + regulator-name = "mdss_core_gdsc"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + status = "disabled"; + }; + + /* GDSCs in GPUCC */ + gpu_gx_sw_reset: syscon@5994008 { + compatible = "syscon"; + reg = <0x5994008 0x4>; + }; + + gpu_cx_hw_ctrl: syscon@5994540 { + compatible = "syscon"; + reg = <0x5994540 0x4>; + }; + + gpu_gx_domain_addr: syscon@5994508 { + compatible = "syscon"; + reg = <0x5994508 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@5994064 { + compatible = "regulator-fixed"; + reg = <0x5994064 0x4>; + regulator-name = "gpu_cx_gdsc"; + hw-ctl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@599400c { + compatible = "regulator-fixed"; + reg = <0x599400c 0x4>; + regulator-name = "gpu_gx_gdsc"; + sw-reset = <&gpu_gx_sw_reset>; + domain-addr = <&gpu_gx_domain_addr>; + qcom,reset-aon-logic; + status = "disabled"; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index cc7e290d0da2..f15bcb2b78b3 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1,4 +1,8 @@ #include +#include +#include +#include +#include / { model = "Qualcomm Technologies, Inc. Monaco"; @@ -471,8 +475,105 @@ qcom,dump-id = <0x123>; }; }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <1>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <1>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + rpmcc: qcom,rpmcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@1410000 { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@5f00000 { + compatible = "qcom,dummycc"; + clock-output-names = "dispcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@5994000 { + compatible = "qcom,dummycc"; + clock-output-names = "gpucc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; #include "monaco-pinctrl.dtsi" #include "monaco-ion.dtsi" +#include "monaco-gdsc.dtsi" +&gcc_camss_top_gdsc { + status = "ok"; +}; + +&gcc_usb20_prim_gdsc { + status = "ok"; +}; + +&gcc_vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_venus_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + status = "ok"; +}; + +&gpu_cx_gdsc { + status = "ok"; +}; + +&gpu_gx_gdsc { + status = "ok"; +}; From 68d9dff9f9ef0e830be95811d148f689aba5cf0b Mon Sep 17 00:00:00 2001 From: Wu Gao Date: Thu, 22 Oct 2020 02:07:28 -0700 Subject: [PATCH 51/61] ARM: dts: msm: Support CNSS WLAN device for sdxlemur Support CNSS WLAN device for sdxlemur. Change-Id: I152ecbd2064b63f15ea38cc300531371d4c0d925 --- qcom/sdxlemur-cdp.dtsi | 1 + qcom/sdxlemur-cnss.dtsi | 196 +++++++++++++++++++++++++++++++++++++ qcom/sdxlemur-mtp-mbb.dtsi | 1 + qcom/sdxlemur-pinctrl.dtsi | 30 ++++++ qcom/sdxlemur-rcm-rc.dtsi | 1 + qcom/sdxlemur.dtsi | 8 ++ 6 files changed, 237 insertions(+) create mode 100644 qcom/sdxlemur-cnss.dtsi diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index b59aa174c58a..fc20abab6a3d 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -1,4 +1,5 @@ #include "sdxlemur-pmic-overlay.dtsi" +#include "sdxlemur-cnss.dtsi" &soc { diff --git a/qcom/sdxlemur-cnss.dtsi b/qcom/sdxlemur-cnss.dtsi new file mode 100644 index 000000000000..bcbdd6ec0501 --- /dev/null +++ b/qcom/sdxlemur-cnss.dtsi @@ -0,0 +1,196 @@ + +&soc { + wlan: qcom,cnss-qca6490@b0000000 { + compatible = "qcom,cnss-qca6490"; + reg = <0xb0000000 0x10000>, + <0xb2e5510 0x690>; + reg-names = "smmu_iova_ipa", "tcs_cmd"; + wlan-en-gpio = <&tlmm 91 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x420000>; + clocks = <&rpmhcc RPMH_RF_CLK3>; + clock-names = "rf_clk"; + + use-pm-domain; + cnss-enable-self-recovery; + + vdd-wlan-aon-supply = <&S7B>; + qcom,vdd-wlan-aon-config = <1012000 1012000 0 0 1>; + vdd-wlan-rfa1-supply = <&S4B>; + qcom,vdd-wlan-rfa1-config = <1900000 1900000 0 0 1>; + vdd-wlan-rfa2-supply = <&S2B>; + qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>; + + interconnects = + <&system_noc MASTER_PCIE_0 &system_noc SLAVE_SNOC_MEM_NOC_GC>, + <&mem_noc MASTER_SNOC_GC_MEM_NOC &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; + + qcom,icc-path-count = <2>; + qcom,bus-bw-cfg-count = <7>; + qcom,bus-bw-cfg = + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */ + <2250 390000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */ + <7500 390000>, + /* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */ + <30000 790000>, + /* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */ + <100000 790000>, + /* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */ + <175000 1600000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz + * ddr: 547.2 MHz + */ + <7500 390000>, + /** ICC Path 2 **/ + <0 0>, + <2250 1804800>, + <7500 1804800>, + <30000 1804800>, + <100000 1804800>, + <175000 6220800>, + <7500 2188800>; + + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,buffer-len = <0x8000>; + mhi,m2-no-db-access; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <1>; + mhi,priority = <0>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <0>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <32>; + mhi,intmod = <0>; + mhi,msi = <0>; + mhi,priority = <2>; + mhi,brstmode = <2>; + mhi,data-type = <3>; + }; + }; + + mhi_devices { + mhi_qrtr { + mhi,chan = "IPCR"; + qcom,net-id = <0>; + qcom,low-latency; + }; + }; + }; +}; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + cnss_pci: cnss_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&cnss_pci_iommu_group>; + memory-region = <&cnss_wlan_mem>; + + #address-cells = <1>; + #size-cells = <1>; + + cnss_pci_iommu_group: cnss_pci_iommu_group { + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE", + "non-fatal"; + }; + }; +}; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 6b5d5c919674..5b77ee6bc08b 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -2,6 +2,7 @@ #include "pm7250b.dtsi" #include #include +#include "sdxlemur-cnss.dtsi" &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 7acc8527e1b9..f4d0c0e303f2 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -186,6 +186,36 @@ }; }; + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + i2c_1 { i2c_1_active: i2c_1_active { mux { diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 824582ac94dc..5c036cf23b5f 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -2,6 +2,7 @@ #include "pm7250b.dtsi" #include #include +#include "sdxlemur-cnss.dtsi" &pm7250b_clkdiv { clocks = <&rpmhcc RPMH_CXO_CLK>; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c761d1ea5c55..0e98cafa1c0d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -55,6 +55,14 @@ no-map; size = <0x400000>; }; + + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0x1400000>; + }; }; cpus { From 343beb8375faa8ba3908f68be2ef2a621961c3cc Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Mon, 23 Nov 2020 16:06:53 -0800 Subject: [PATCH 52/61] ARM: dts: msm: DDR cooling device no mitigation for lahaina DDR cooling device right now votes for the lowest bandwidth when there is no request from cooling device. Instead of voting to lowest level, vote for zero bandwidth, so that it doesn't prevent sleep. Change-Id: Ibf7895568f7c102bd4dc7267327b7decf45362e8 --- qcom/lahaina-thermal.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index fb753c87f2dd..30711401984a 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -57,7 +57,7 @@ ddr_cdev: qcom,ddr-cdev { compatible = "qcom,ddr-cooling-device"; #cooling-cells = <2>; - qcom,ddr-freq = <762000>, + qcom,ddr-freq = <0>, <1720000>, <2086000>, <2597000>, From 5e9e8bc32655dbb64c0d9cce45a4d7075c554a10 Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Mon, 23 Nov 2020 10:13:08 +0800 Subject: [PATCH 53/61] ARM: dts: msm: Add label for bluetooth bootstrap pin EDL_MODE on sdxlemur GPIO17 also drives bluetooth bootstrap pin EDL_MODE for sdxlemur, so add a label for bluetooth. CRs-Fixed: 2824381 Change-Id: I3779e8fa26e9a41b6a0a378b4ed97b7b985bd2c1 --- qcom/sdxlemur-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 7acc8527e1b9..a5d5e1e8261f 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -1417,7 +1417,7 @@ }; pmx_sec_mi2s_aux_din { - sec_din_sleep: sec_din_sleep { + bt_edl_default: sec_din_sleep: sec_din_sleep { mux { pins = "gpio17"; function = "gpio"; From 0e4ed0f33548674d9d29d287985def521d9261aa Mon Sep 17 00:00:00 2001 From: Zijun Hu Date: Mon, 23 Nov 2020 11:00:48 +0800 Subject: [PATCH 54/61] ARM: dts: msm: Enable bluetooth for sdxlemur Enable bluetooth for sdxlemur. CRs-Fixed: 2824381 Change-Id: I37762923eb49bfb3b3bbb19a5f088540f473f4e4 --- qcom/sdxlemur-bluetooth.dtsi | 40 ++++++++++++++++++++++++++++++++++ qcom/sdxlemur-cdp.dts | 1 + qcom/sdxlemur-mtp-mbb-emmc.dts | 1 + qcom/sdxlemur-mtp-mbb.dts | 1 + qcom/sdxlemur-rcm-rc.dts | 1 + 5 files changed, 44 insertions(+) create mode 100644 qcom/sdxlemur-bluetooth.dtsi diff --git a/qcom/sdxlemur-bluetooth.dtsi b/qcom/sdxlemur-bluetooth.dtsi new file mode 100644 index 000000000000..d4848e87ad4c --- /dev/null +++ b/qcom/sdxlemur-bluetooth.dtsi @@ -0,0 +1,40 @@ +#include + +&pmx65_gpios { + bt_en { + bt_en_default: bt_en_default { + pins = "gpio15"; + function = "normal"; + output-low; + bias-pull-down; + qcom,drive-strength = <2>; + power-source = <1>; + }; + }; +}; + +&soc { + bluetooth: bt_qca6490 { + compatible = "qcom,qca6490"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_default &bt_edl_default>; + qcom,bt-reset-gpio = <&pmx65_gpios 15 0>; /* BT_EN */ + qcom,bt-sw-ctrl-gpio = <&pmx65_gpios 2 0>; /* SW_CTRL */ + + clocks = <&rpmhcc RPMH_RF_CLK3>; + clock-names = "ref3_clk"; + + qcom,bt-vdd-aon-supply = <&S7B>; + qcom,bt-vdd-aon-config = <1012000 1012000 0 0>; + qcom,bt-vdd-io-supply = <&L6B>; + qcom,bt-vdd-io-config = <1800000 1800000 0 0>; + }; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; + +&i2c_6 { + status = "disabled"; +}; diff --git a/qcom/sdxlemur-cdp.dts b/qcom/sdxlemur-cdp.dts index 93cd0f92dd66..68c99b5dd58d 100644 --- a/qcom/sdxlemur-cdp.dts +++ b/qcom/sdxlemur-cdp.dts @@ -3,6 +3,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-cdp.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR CDP"; compatible = "qcom,sdxlemur-cdp", diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dts b/qcom/sdxlemur-mtp-mbb-emmc.dts index acdb4853a32a..734bb19c3f1b 100644 --- a/qcom/sdxlemur-mtp-mbb-emmc.dts +++ b/qcom/sdxlemur-mtp-mbb-emmc.dts @@ -3,6 +3,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-emmc.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB eMMC"; diff --git a/qcom/sdxlemur-mtp-mbb.dts b/qcom/sdxlemur-mtp-mbb.dts index e9bc21eb4200..bdcc2ce058b1 100644 --- a/qcom/sdxlemur-mtp-mbb.dts +++ b/qcom/sdxlemur-mtp-mbb.dts @@ -3,6 +3,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB"; diff --git a/qcom/sdxlemur-rcm-rc.dts b/qcom/sdxlemur-rcm-rc.dts index 990224dd464a..a5fd339b9fa4 100644 --- a/qcom/sdxlemur-rcm-rc.dts +++ b/qcom/sdxlemur-rcm-rc.dts @@ -3,6 +3,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-rcm-rc.dtsi" #include "sdxlemur-1024mb.dtsi" +#include "sdxlemur-bluetooth.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex"; From aaf5337d6323ee77861d98d83ef1c42e88a0c7b9 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Sun, 22 Nov 2020 11:02:03 +0530 Subject: [PATCH 55/61] ARM: dts: msm: Enable NAND and SD card for sdxlemur target Enable NAND and SD card for all the boards available on sdxlemur target. Change-Id: I17b3321bde161fbfbec8950d9893854912297ba9 --- qcom/sdxlemur-cdp.dtsi | 2 +- qcom/sdxlemur-mtp-mbb.dtsi | 32 -------------------------------- qcom/sdxlemur-rcm-pcie-ep.dtsi | 21 +++++++++++++++++++++ qcom/sdxlemur-rcm-rc.dtsi | 22 ++++++++++++++++++++++ 4 files changed, 44 insertions(+), 33 deletions(-) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index b59aa174c58a..fe6531308f6c 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -9,7 +9,7 @@ }; &sdhc_1 { - status = "disabled"; + status = "ok"; vdd-supply = <&vreg_sd_vdd>; qcom,vdd-voltage-level = <2950000 2950000>; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 6b5d5c919674..a11b05d3ad25 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -31,38 +31,6 @@ qcom,l1-2-th-value = <70>; }; -&qnand_1 { - status = "ok"; -}; - -&sdhc_1 { - reg = <0x08804000 0x1000>, <0x08805000 0x1000>; - reg-names = "hc_mem", "cqhci_mem"; - - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - bus-width = <8>; - non-removable; - supports-cqe; - - vdd-supply = <&vreg_sd_vdd>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <0 570000>; - - vdd-io-supply = <&L6B>; - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <0 200000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - - status = "disabled"; -}; - &pm7250b_vadc { charger_skin_therm { reg = ; diff --git a/qcom/sdxlemur-rcm-pcie-ep.dtsi b/qcom/sdxlemur-rcm-pcie-ep.dtsi index 768d9aaa521c..e61e86ac8459 100644 --- a/qcom/sdxlemur-rcm-pcie-ep.dtsi +++ b/qcom/sdxlemur-rcm-pcie-ep.dtsi @@ -4,3 +4,24 @@ }; +&qnand_1 { + status = "ok"; +}; + +&sdhc_1 { + status = "ok"; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 824582ac94dc..765f3859f4c3 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -31,6 +31,28 @@ qcom,l1-2-th-value = <70>; }; +&qnand_1 { + status = "ok"; +}; + +&sdhc_1 { + status = "ok"; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pm7250b_vadc { charger_skin_therm { reg = ; From ae8150eac6573c0caff8153bfb4db7c0221dcfd6 Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Fri, 6 Nov 2020 10:43:35 +0800 Subject: [PATCH 56/61] ARM: dts: msm: Add dma-coherent for tmc-etr on Lahaina Add dma-coherent for tmc-etr to avoid cache flush issue between etr and usb. Change-Id: Iba762e88442294c93c22675f2b4d2c2937c1e9dd --- qcom/lahaina-coresight.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi index ff7750e6f034..b773c609af39 100644 --- a/qcom/lahaina-coresight.dtsi +++ b/qcom/lahaina-coresight.dtsi @@ -154,6 +154,7 @@ arm,buffer-size = <0x400000>; arm,scatter-gather; + dma-coherent; qcom,sw-usb; coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti3_swao>; From e8ca9d4eee66a37e15493abca64f463712ba5eb5 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Fri, 6 Nov 2020 09:22:55 +0530 Subject: [PATCH 57/61] ARM: dts: msm: Add clock controller and gdsc nodes for sm8150 Add support for all the clock controllers and also add gdsc regulators. Change-Id: Ic313db887845e43c1d69b82f6bd8af4154145832 --- qcom/sa8155-regulator.dtsi | 1 + qcom/sa8155-v1.dtsi | 20 +++ qcom/sa8155-v2.dtsi | 20 +++ qcom/sa8155.dtsi | 13 ++ qcom/sm8150-gdsc.dtsi | 254 +++++++++++++++++++++++++++++++ qcom/sm8150-regulator.dtsi | 1 + qcom/sm8150-v2.dtsi | 24 +++ qcom/sm8150.dtsi | 296 +++++++++++++++++++++++++++++++++++-- 8 files changed, 620 insertions(+), 9 deletions(-) create mode 100644 qcom/sm8150-gdsc.dtsi diff --git a/qcom/sa8155-regulator.dtsi b/qcom/sa8155-regulator.dtsi index a3575be84b12..5685f98c665a 100644 --- a/qcom/sa8155-regulator.dtsi +++ b/qcom/sa8155-regulator.dtsi @@ -344,6 +344,7 @@ rpmh-regulator-gfxlvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: S3C_LEVEL: pm8150_2_s3_level: regulator-pm8150-2-s3-level { regulator-name = "pm8150_2_s3_level"; qcom,set = ; diff --git a/qcom/sa8155-v1.dtsi b/qcom/sa8155-v1.dtsi index 50d09d7a5ba4..1e52e3797265 100644 --- a/qcom/sa8155-v1.dtsi +++ b/qcom/sa8155-v1.dtsi @@ -7,3 +7,23 @@ qcom,msm-name = "SA8155 V1"; qcom,msm-id = <362 0x10000>; }; + +&scc { + compatible = "qcom,sa8155-scc", "syscon"; +}; + +&gcc { + compatible = "qcom,sa8155-gcc", "syscon"; +}; + +&videocc { + compatible = "qcom,sa8155-videocc", "syscon"; +}; + +&npucc { + compatible = "qcom,sa8155-npucc", "syscon"; +}; + +&camcc { + compatible = "qcom,sa8155-camcc", "syscon"; +}; diff --git a/qcom/sa8155-v2.dtsi b/qcom/sa8155-v2.dtsi index 09d9488c0872..f995a319af99 100644 --- a/qcom/sa8155-v2.dtsi +++ b/qcom/sa8155-v2.dtsi @@ -6,3 +6,23 @@ qcom,msm-name = "SA8155 V2"; qcom,msm-id = <362 0x20000>; }; + +&scc { + compatible = "qcom,sa8155-scc-v2", "syscon"; +}; + +&gcc { + compatible = "qcom,sa8155-gcc-v2", "syscon"; +}; + +&videocc { + compatible = "qcom,sa8155-videocc-v2", "syscon"; +}; + +&npucc { + compatible = "qcom,sa8155-npucc-v2", "syscon"; +}; + +&camcc { + compatible = "qcom,sa8155-camcc-v2", "syscon"; +}; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index b048176d4cbb..a3fcc5063c04 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -55,3 +55,16 @@ /* Add regulator nodes specific to SA8155 */ #include "sa8155-regulator.dtsi" + +&gpucc { + compatible = "qcom,sa8155-gpucc", "syscon"; +}; + +&scc { + vdd_scc_cx-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_GFX_LEVEL>; +}; diff --git a/qcom/sm8150-gdsc.dtsi b/qcom/sm8150-gdsc.dtsi new file mode 100644 index 000000000000..07d8e929ce7a --- /dev/null +++ b/qcom/sm8150-gdsc.dtsi @@ -0,0 +1,254 @@ +&soc { + /* GDSCs in Global CC */ + emac_gdsc: qcom,gdsc@106004 { + compatible = "qcom,gdsc"; + regulator-name = "emac_gdsc"; + reg = <0x106004 0x4>; + status = "disabled"; + }; + + pcie_0_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_0_gdsc"; + reg = <0x16b004 0x4>; + status = "disabled"; + }; + + pcie_1_gdsc: qcom,gdsc@18d004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_1_gdsc"; + reg = <0x18d004 0x4>; + status = "disabled"; + }; + + ufs_card_gdsc: qcom,gdsc@175004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_card_gdsc"; + reg = <0x175004 0x4>; + status = "disabled"; + }; + + ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_phy_gdsc"; + reg = <0x177004 0x4>; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_prim_gdsc"; + reg = <0x10f004 0x4>; + status = "disabled"; + }; + + usb30_sec_gdsc: qcom,gdsc@110004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_sec_gdsc"; + reg = <0x110004 0x4>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; + reg = <0x17d040 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; + reg = <0x17d044 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; + reg = <0x17d048 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; + reg = <0x17d04c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + reg = <0x17d050 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + reg = <0x17d054 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + reg = <0x17d058 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; + reg = <0x17d05c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@17d060 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; + reg = <0x17d060 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + bps_gdsc: qcom,gdsc@ad07004 { + compatible = "qcom,gdsc"; + regulator-name = "bps_gdsc"; + reg = <0xad07004 0x4>; + status = "disabled"; + }; + + ipe_0_gdsc: qcom,gdsc@ad08004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_0_gdsc"; + reg = <0xad08004 0x4>; + status = "disabled"; + }; + + ipe_1_gdsc: qcom,gdsc@ad09004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_1_gdsc"; + reg = <0xad09004 0x4>; + status = "disabled"; + }; + + ife_0_gdsc: qcom,gdsc@ad0a004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_0_gdsc"; + reg = <0xad0a004 0x4>; + status = "disabled"; + }; + + ife_1_gdsc: qcom,gdsc@ad0b004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_1_gdsc"; + reg = <0xad0b004 0x4>; + status = "disabled"; + }; + + titan_top_gdsc: qcom,gdsc@ad0c1bc { + compatible = "qcom,gdsc"; + regulator-name = "titan_top_gdsc"; + reg = <0xad0c1bc 0x4>; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@af03000 { + compatible = "qcom,gdsc"; + regulator-name = "mdss_core_gdsc"; + reg = <0xaf03000 0x4>; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@2c91540 { + compatible = "syscon"; + reg = <0x2c91540 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@2c9106c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_cx_gdsc"; + reg = <0x2c9106c 0x4>; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,skip-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + mboxes = <&qmp_aop 0>; + status = "disabled"; + }; + + gpu_gx_domain_addr: syscon@2c91508 { + compatible = "syscon"; + reg = <0x2c91508 0x4>; + }; + + gpu_gx_sw_reset: syscon@2c91008 { + compatible = "syscon"; + reg = <0x2c91008 0x4>; + }; + + gpu_gx_gdsc: qcom,gdsc@2c9100c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_gx_gdsc"; + reg = <0x2c9100c 0x4>; + domain-addr = <&gpu_gx_domain_addr>; + sw-reset = <&gpu_gx_sw_reset>; + qcom,reset-aon-logic; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + mvsc_gdsc: qcom,gdsc@ab00814 { + compatible = "qcom,gdsc"; + regulator-name = "mvsc_gdsc"; + reg = <0xab00814 0x4>; + status = "disabled"; + }; + + mvs0_gdsc: qcom,gdsc@ab00874 { + compatible = "qcom,gdsc"; + regulator-name = "mvs0_gdsc"; + reg = <0xab00874 0x4>; + status = "disabled"; + }; + + mvs1_gdsc: qcom,gdsc@ab008b4 { + compatible = "qcom,gdsc"; + regulator-name = "mvs1_gdsc"; + reg = <0xab008b4 0x4>; + status = "disabled"; + }; + + /* GDSCs in NPU CC */ + npu_core_gdsc: qcom,gdsc@9911028 { + compatible = "qcom,gdsc"; + regulator-name = "npu_core_gdsc"; + reg = <0x9911028 0x4>; + status = "disabled"; + }; +}; diff --git a/qcom/sm8150-regulator.dtsi b/qcom/sm8150-regulator.dtsi index b03ebd06ffe3..8cb0baf556e8 100644 --- a/qcom/sm8150-regulator.dtsi +++ b/qcom/sm8150-regulator.dtsi @@ -450,6 +450,7 @@ rpmh-regulator-gfxlvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: S2C_LEVEL: pm8150l_s2_level: regulator-pm8150l-s2-level { regulator-name = "pm8150l_s2_level"; qcom,set = ; diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index 3f6b99c92e77..a7ec31ec4fa3 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -5,3 +5,27 @@ qcom,msm-name = "SM8150 V2"; qcom,msm-id = <339 0x20000>; }; + +&gcc { + compatible = "qcom,sm8150-gcc-v2", "syscon"; +}; + +&camcc { + compatible = "qcom,sm8150-camcc-v2", "syscon"; +}; + +&dispcc { + compatible = "qcom,sm8150-dispcc-v2", "syscon"; +}; + +&videocc { + compatible = "qcom,sm8150-videocc-v2", "syscon"; +}; + +&npucc { + compatible = "qcom,sm8150-npucc-v2", "syscon"; +}; + +&scc { + compatible = "qcom,sm8150-scc-v2", "syscon"; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index fcb8a87066b1..50f901d5282a 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1,3 +1,11 @@ +#include +#include +#include +#include +#include +#include +#include +#include #include #include #include @@ -701,24 +709,138 @@ }; + aopcc: qcom,aopcc { + compatible = "qcom,aop-qmp-clk"; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; + #clock-cells = <1>; + }; + gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x00100000 0x1f0000>; + compatible = "qcom,sm8150-gcc", "syscon"; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,sm8150-videocc", "syscon"; + reg = <0xab00000 0x10000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb_clk", "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,sm8150-camcc", "syscon"; + reg = <0xad00000 0x10000>; + reg-names = "cc_base"; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb_clk", "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8150-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb_clk", "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + npucc: clock-controller@9910000 { + compatible = "qcom,sm8150-npucc", "syscon"; + reg = <0x9910000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_gdsc-supply = <&npu_core_gdsc>; + clocks = + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_NPU_GPLL0_CLK_SRC>, + <&gcc GCC_NPU_AXI_CLK>; + clock-names = + "bi_tcxo", + "gcc_npu_gpll0_div_clk_src", + "gcc_npu_gpll0_clk_src", + "gcc_npu_axi_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@2c90000 { + compatible = "qcom,sm8150-gpucc", "syscon"; + reg = <0x2c90000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + scc: clock-controller@2b10000 { + compatible = "qcom,sm8150-scc", "syscon"; + reg = <0x2b10000 0x30000>; + vdd_scc_cx-supply = <&pm8150_l8_level>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + status = "disabled"; + }; + + cpucc: syscon@182a0018 { + compatible = "syscon"; + reg = <0x182a0000 0x4>; + }; + + mccc: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x1000>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,sm8150-debugcc"; + qcom,gcc = <&gcc>; + qcom,videocc = <&videocc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,npucc = <&npucc>; + qcom,gpucc = <&gpucc>; + qcom,cpucc = <&cpucc>; + qcom,mccc = <&mccc>; + clock-names = "xo_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; }; qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x00ac0000 0x6000>; clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc 123>, - <&gcc 124>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; ranges; #address-cells = <2>; #size-cells = <2>; @@ -729,7 +851,7 @@ compatible = "qcom,geni-debug-uart"; reg = <0x0 0x00a90000 0x0 0x4000>; clock-names = "se"; - clocks = <&gcc 105>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; interrupts = ; status = "ok"; }; @@ -1112,3 +1234,159 @@ #include "sm8150-pm.dtsi" #include "sm8150-slpi-pinctrl.dtsi" #include "sm8150-smp2p.dtsi" +#include "sm8150-gdsc.dtsi" + +&emac_gdsc { + status = "ok"; +}; + +&pcie_0_gdsc { + status = "ok"; +}; + +&pcie_1_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&ufs_card_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&usb30_sec_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&bps_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ipe_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ipe_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ife_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ife_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&titan_top_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&mdss_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_DISP_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_GFX_LEVEL>; + status = "ok"; +}; + +&mvsc_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&mvs0_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&mvs1_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&npu_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_NPU_CFG_AHB_CLK>; + status = "ok"; +}; From 6236ec35c7a1d93c97fe119e64d7ba8e7ae71a2d Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 2 Mar 2020 16:08:59 +0530 Subject: [PATCH 58/61] ARM: dts: msm: add interconnect devices for sm8150 Add stub interconnect devices for aggre1_noc, aggre2_noc, camnoc_virt, compute_noc, config_noc, dc_noc, gem_noc, ipa_virt, mc_virt, mmss_noc, system_noc, gem_noc_display, mc_virt_display, mmss_noc_display. This will allow consumers to get their path and set bandwidth constraints on them. And add bcm voter devices that live under RSC devices to allow interconnect providers to target their votes for meeting bandwidth constraints. Change-Id: I6c46d36928ecfbeaa5b568a61d3dfee9e9e0349d --- qcom/sm8150.dtsi | 99 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 50f901d5282a..cc62d8d3f78e 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include #include #include @@ -681,6 +683,10 @@ , ; + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + rpmhcc: clock-controller { compatible = "qcom,sm8150-rpmh-clk"; #clock-cells = <1>; @@ -707,6 +713,11 @@ , ; + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + }; + }; aopcc: qcom,aopcc { @@ -835,6 +846,94 @@ #clock-cells = <1>; }; + config_noc: interconnect@1500000 { + reg = <0x1500000 0x7400>; + compatible = "qcom,sm8150-config_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + reg = <0x1620000 0x19400>; + compatible = "qcom,sm8150-system_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + camnoc_virt: interconnect@1630000 { + compatible = "qcom,sm8150-camnoc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ipa_virt: interconnect@1640000 { + compatible = "qcom,sm8150-ipa_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + reg = <0x16E0000 0xD080>; + compatible = "qcom,sm8150-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; + }; + + aggre2_noc: interconnect@1700000 { + reg = <0x1700000 0x3B100>; + compatible = "qcom,sm8150-aggre2_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + compute_noc: interconnect@1710000 { + compatible = "qcom,sm8150-compute_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x1C100>; + compatible = "qcom,sm8150-mmss_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + dc_noc: interconnect@9160000 { + reg = <0x9160000 0x3200>; + compatible = "qcom,sm8150-dc_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + reg = <0x9680000 0x3E200>; + compatible = "qcom,sm8150-gem_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + mc_virt: interconnect@9690000 { + compatible = "qcom,sm8150-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x00ac0000 0x6000>; From 24f8b6eb0b0acbe4d701c8515777daae1cb7bbba Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 13 Apr 2020 15:28:57 +0530 Subject: [PATCH 59/61] ARM: dts: msm: Add UFS support for SA8155 Add UFS host controller and UFS PHY (attached to embedded UFS card) for SM8150 platform and SA8155. Change-Id: I2f58f3bd2457fed0baaffa5233bbd2c92ec22c12 --- qcom/sa8155-adp-common.dtsi | 25 +++++++ qcom/sa8155.dtsi | 4 ++ qcom/sm8150.dtsi | 140 ++++++++++++++++++++++++++++++++++++ 3 files changed, 169 insertions(+) diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index 44b2ac0d79b8..fc99f15ac51c 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -1,2 +1,27 @@ #include #include + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-pll-supply = <&pm8150_2_l8>; + vdda-phy-max-microamp = <87100>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_1_l10>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm8150_1_s4>; + vcc-max-microamp = <750000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150_2_l5>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index a3fcc5063c04..8f7a349e5ad9 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -68,3 +68,7 @@ &gpu_gx_gdsc { parent-supply = <&VDD_GFX_LEVEL>; }; + +&ufsphy_mem { + vdda-phy-supply = <&pm8150_2_l18>; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index cc62d8d3f78e..593cdf061a10 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ memory { device_type = "memory"; reg = <0 0 0 0>; }; aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ serial0 = &uart2; }; @@ -934,6 +936,144 @@ }; + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xda8>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x2500>, + <0x1d90000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <2097152 0>, <102400 0>, /* HS G3 RA */ + <4194304 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <4194304 0>, <204800 0>, /* HS G3 RA L2 */ + <8388608 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <2097152 0>, <102400 0>, /* HS G3 RB */ + <4194304 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <4194304 0>, <204800 409600>, /* HS G3 RB L2 */ + <8388608 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "disabled"; + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x00ac0000 0x6000>; From 61540c97ebea006f6d72108d1ed6700027e33478 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 24 Nov 2020 17:53:15 +0800 Subject: [PATCH 60/61] ARM: dts: msm: refine QDSS config for sdxlemur Add reset and flush trigger number for etr and etf. Change-Id: Iec420ee00ac45ca37e525f3736e0204d6c36e71b --- qcom/sdxlemur-coresight.dtsi | 8 ++++++-- qcom/sdxlemur.dtsi | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index 2e977b84e52b..073cfa4332f9 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -107,7 +107,9 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0_swao &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -147,7 +149,9 @@ arm,scatter-gather; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0 &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <3>; coresight-csr = <&csr>; clocks = <&aopcc QDSS_CLK>; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c761d1ea5c55..0553ed188bfc 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -946,6 +946,7 @@ #include "sdxlemur-pinctrl.dtsi" #include "sdxlemur-regulators.dtsi" +#include "sdxlemur-coresight.dtsi" #include "msm-arm-smmu-sdxlemur.dtsi" #include "sdxlemur-ion.dtsi" #include "sdxlemur-usb.dtsi" From 46d06ca5d9e86fbeb05abbd88a523b981220f17d Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 24 Nov 2020 17:57:07 +0800 Subject: [PATCH 61/61] ARM: dts: msm: modify dcc_ram_offset for sdxlemur Modify dcc_ram_offset to 0x12000 on sdxlemur. Change-Id: Iadb7d0ce55976cb9a29fdc6d57b4ea46783bc6b1 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c761d1ea5c55..f31fbbd269c9 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -185,7 +185,7 @@ qcom,transaction_timeout = <0>; reg-names = "dcc-base", "dcc-ram-base"; - dcc-ram-offset = <0x800>; + dcc-ram-offset = <0x12000>; }; wdog: qcom,wdt@17817000 {