diff --git a/bindings/interconnect/qcom,epss-l3.txt b/bindings/interconnect/qcom,epss-l3.txt
index 8bd41c0a753e..d3a31ad4e6df 100644
--- a/bindings/interconnect/qcom,epss-l3.txt
+++ b/bindings/interconnect/qcom,epss-l3.txt
@@ -10,6 +10,7 @@ Required properties :
 			"qcom,lahaina-epss-l3-cpu",
 			"qcom,shima-epss-l3-cpu",
 			"qcom,shima-epss-l3-shared";
+			"qcom,yupik-epss-l3-cpu",
 - reg : Address and length of the register set for the device
 - clock-names: should contain "xo", "alternate"
 - clocks: list of phandle and clock specifier pairs corresponding to
diff --git a/bindings/interconnect/qcom,yupik.txt b/bindings/interconnect/qcom,yupik.txt
new file mode 100644
index 000000000000..f60a0b12fe7e
--- /dev/null
+++ b/bindings/interconnect/qcom,yupik.txt
@@ -0,0 +1,31 @@
+Qualcomm Technologies, Inc. Yupik Network-On-Chip interconnect driver binding
+-----------------------------------------------------------
+
+Yupik interconnect providers support system bandwidth requirements through
+RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+able to communicate with the BCM through the Resource State Coordinator (RSC)
+associated with each execution environment. Provider nodes must point to at
+least one RPMh device child node pertaining to their RSC and each provider
+can map to multiple RPMh resources.
+
+Required properties :
+- compatible : shall contain only one of the following:
+			"qcom,yupik-aggre1_noc",
+			"qcom,yupik-aggre2_noc",
+			"qcom,yupik-clk_virt",
+			"qcom,yupik-config_noc",
+			"qcom,yupik-dc_noc",
+			"qcom,yupik-gem_noc",
+			"qcom,yupik-lpass_ag_noc",
+			"qcom,yupik-mc_virt",
+			"qcom,yupik-mmss_noc",
+			"qcom,yupik-nsp_noc",
+			"qcom,yupik-system_noc",
+- #interconnect-cells : should contain 1
+
+Examples:
+
+aggre1_noc: interconnect@16e0000 {
+	compatible = "qcom,yupik-aggre1_noc";
+	interconnect-cells = <1>;
+};