From 87467acc80010f9dbab1587f3d072b4a48ceed5c Mon Sep 17 00:00:00 2001
From: Taniya Das <tdas@qti.qualcomm.com>
Date: Wed, 8 Jul 2020 12:23:49 +0530
Subject: [PATCH] ARM: dts: msm: Update DISPCC debug CC and GDSC for HOLI

Display Clock controller and Debug clock controller
and change to real gdsc for mdss_core_gdsc for HOLI.

Change-Id: I18b01734f2dff412c8b124dcc050649f3c1bf6e9
---
 qcom/holi-gdsc.dtsi |  2 +-
 qcom/holi.dtsi      | 43 +++++++++++++++++++++++++++++++++++--------
 2 files changed, 36 insertions(+), 9 deletions(-)

diff --git a/qcom/holi-gdsc.dtsi b/qcom/holi-gdsc.dtsi
index bd1ac6f985ef..5e2346aab191 100644
--- a/qcom/holi-gdsc.dtsi
+++ b/qcom/holi-gdsc.dtsi
@@ -73,7 +73,7 @@
 
 	/* GDSCs in DISPCC */
 	mdss_core_gdsc: qcom,gdsc@5f01004 {
-		compatible = "regulator-fixed";
+		compatible = "qcom,gdsc";
 		reg = <0x5f01004 0x4>;
 		regulator-name = "mdss_core_gdsc";
 		proxy-supply = <&mdss_core_gdsc>;
diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi
index 75a13db1df14..dd8699d4663f 100644
--- a/qcom/holi.dtsi
+++ b/qcom/holi.dtsi
@@ -888,14 +888,14 @@
 		};
 	};
 
-	rpmcc: qcom,rpmcc {
+	rpmcc: clock-controller {
 		compatible = "qcom,rpmcc-holi";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
 
-	gcc: qcom,gcc@1400000 {
-		compatible = "qcom,holi-gcc";
+	gcc: clock-controller@1400000 {
+		compatible = "qcom,holi-gcc", "syscon";
 		reg = <0x1400000 0x1f0000>;
 		reg_names = "cc_base";
 		vdd_cx-supply = <&VDD_CX_LEVEL>;
@@ -908,15 +908,20 @@
 		#reset-cells = <1>;
 	};
 
-	dispcc: qcom,dispcc@5f00000 {
-		compatible = "qcom,dummycc";
-		clock-output-names = "dispcc_clocks";
+	dispcc: clock-controller@5f00000 {
+		compatible = "qcom,holi-dispcc", "syscon";
+		reg = <0x5f00000 0x20000>;
+		reg-names = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+			 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+		clock-names = "bi_tcxo", "gcc_disp_gpll0_clk";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
 
-	gpucc: qcom,gpucc@5990000 {
-		compatible = "qcom,holi-gpucc";
+	gpucc: clock-controller@5990000 {
+		compatible = "qcom,holi-gpucc", "syscon";
 		reg = <0x5990000 0x9000>;
 		reg-names = "cc_base";
 		vdd_cx-supply = <&VDD_CX_LEVEL>;
@@ -932,6 +937,28 @@
 		#reset-cells = <1>;
 	};
 
+	cpucc: syscon@faa0018 {
+		compatible = "syscon";
+		reg = <0x0faa0018 0x4>;
+	};
+
+	mccc: syscon@0447d200 {
+		compatible = "syscon";
+		reg = <0x0447d200 0x100>;
+	};
+
+	debugcc: clock-controller@0 {
+		compatible = "qcom,holi-debugcc";
+		qcom,gcc = <&gcc>;
+		qcom,dispcc = <&dispcc>;
+		qcom,gpucc = <&gpucc>;
+		qcom,cpucc = <&cpucc>;
+		qcom,mccc = <&mccc>;
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+		clock-names = "xo_clk_src";
+		#clock-cells = <1>;
+	};
+
 	cpufreq_hw: qcom,cpufreq-hw {
 		compatible = "qcom,cpufreq-hw-epss";
 		reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>;