From 1b866d34e2c5eb8f9597a9ae9f2bdaa8cec0935b Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 26 Oct 2020 17:10:28 -0700 Subject: [PATCH 1/3] ARM: dts: msm: add MX entries for PCIe on sdxlemur To properly support PCIe Gen4 on sdxlemur, PCIe needs to vote and scale MX rails accordingly. Add the required MX entries to enable PCIe bus driver to do so for sdxlemur. Change-Id: Ia56142013d07c9a811f5357e8ce29fdb3c76dd39 --- qcom/sdxlemur-pcie.dtsi | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 2ea8fedc36bb..2ab0fd2ceba7 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -46,15 +46,30 @@ vreg-1p8-supply = <&pmx65_l1>; vreg-0p9-supply = <&pmx65_l4>; vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; qcom,vreg-0p9-voltage-level = <912000 912000 132000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = - ; /* Gen4 */ + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; interconnect-names = "icc_path"; interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; From d37c0931341137a01ea913b0c3c584bc31a7af34 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 27 Oct 2020 20:24:01 -0700 Subject: [PATCH 2/3] dt-bindings: arm: msm: add support for tuning PCIe EQ Master Phase Add DT entry to determine the minimum amount of time PCIe needs to remain in equalization master phase. Change-Id: I14f0e0b28dd69b8b38ac7be1cae282635ef11fe5 --- bindings/pci/pci-msm.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 6c6285f4e714..6f3e41eac5bc 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -290,6 +290,13 @@ interconnects: Definition: L1.2 LTR threshold value to be multipled with scale to define L1.2 latency tolerance reporting (LTR) +- qcom,eq-fmdc-t-min-phase23: + Usage: optional + Value type: + Definition: Determines minimum time (ms) to remain in equalization + master phase before checking for convergence of the + coefficients. + - qcom,slv-addr-space-size: Usage: required Value type: @@ -519,6 +526,7 @@ Example qcom,no-l1-supported; qcom,no-l1ss-supported; qcom,no-aux-clk-sync; + qcom,eq-fmdc-t-min-phase23 = <1>; /* 1ms */ qcom,slv-addr-space-size = <0x1000000>; /* 16MB */ qcom,wr-halt-size = <0xa>; /* 1KB */ qcom,tlp-rd-size = <0x5>; /* 4KB */ From 08a5b7bc69e8ee92fca57e0e1824f0ddd9cf87e3 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 27 Oct 2020 20:27:46 -0700 Subject: [PATCH 3/3] ARM: dts: msm: keep PCIe in EQ Master Phase for at least 1ms on sdxlemur PCIe PHY on sdxlemur requires the equalization master phase of link training to be at least 1ms long before proceeding to the next LTSSM state. Add the corresponding DT entry to configure the controller to meet this requirement on sdxlemur. Change-Id: Ied893d27cdc7a62c8a9284a9f16348ab8122094a --- qcom/sdxlemur-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 2ab0fd2ceba7..9e13fe07f23d 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -107,6 +107,7 @@ <0x100 &apps_smmu 0x0201 0x1>; qcom,aux-clk-freq = <17>; /* 16.6 MHz */ + qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>;