From afdf7df1027dda58a0daf50991737666bd988601 Mon Sep 17 00:00:00 2001 From: Jeff LaBundy Date: Tue, 20 Feb 2018 13:32:36 -0600 Subject: [PATCH] misc: cs40l20: Regmap updates Corrected various register default values, updated the list of registers marked as volatile and removed some inapplicable register macros. Change-Id: I51ca890aaa98001e85728a113670a391911b00a1 Signed-off-by: Jeff LaBundy Signed-off-by: Ravi Vembu --- drivers/misc/cs40l20-tables.c | 20 +++++++++----------- drivers/misc/cs40l20.h | 5 +---- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/drivers/misc/cs40l20-tables.c b/drivers/misc/cs40l20-tables.c index 4ab1e039d4c3..12f52999bf13 100644 --- a/drivers/misc/cs40l20-tables.c +++ b/drivers/misc/cs40l20-tables.c @@ -32,9 +32,7 @@ const unsigned char cs40l20_bst_slope_table[4] = {0x75, 0x6B, 0x3B, 0x28}; const struct reg_default cs40l20_reg[CS40L20_MAX_CACHE_REG] = { {CS40L20_TEST_KEY_CTL, 0x00000000}, {CS40L20_USER_KEY_CTL, 0x00000000}, - {CS40L20_OTP_MEM0, 0x00000000}, - {CS40L20_OTP_MEM31, 0x00000000}, - {CS40L20_OTP_CTRL0, 0x00006419}, + {CS40L20_OTP_CTRL0, 0x00006418}, {CS40L20_OTP_CTRL1, 0x00000000}, {CS40L20_OTP_CTRL3, 0x00000000}, {CS40L20_OTP_CTRL4, 0x00000000}, @@ -43,18 +41,16 @@ const struct reg_default cs40l20_reg[CS40L20_MAX_CACHE_REG] = { {CS40L20_OTP_CTRL7, 0x00000000}, {CS40L20_OTP_CTRL8, 0x00000000}, {CS40L20_PWR_CTRL1, 0x00000000}, - {CS40L20_PWR_CTRL2, 0x00003321}, - {CS40L20_PWR_CTRL3, 0x01000011}, + {CS40L20_PWR_CTRL3, 0x01000010}, {CS40L20_CTRL_OVRRIDE, 0x00000002}, {CS40L20_AMP_OUT_MUTE, 0x00000000}, {CS40L20_PROTECT_REL_ERR_IGN, 0x00000000}, - {CS40L20_GPIO_PAD_CONTROL, 0x00000000}, {CS40L20_JTAG_CONTROL, 0x00000000}, {CS40L20_PLL_CLK_CTRL, 0x00000010}, {CS40L20_DSP_CLK_CTRL, 0x00000003}, {CS40L20_GLOBAL_CLK_CTRL, 0x00000003}, {CS40L20_DATA_FS_SEL, 0x00000000}, - {CS40L20_MDSYNC_EN, 0x00000000}, + {CS40L20_MDSYNC_EN, 0x00000200}, {CS40L20_MDSYNC_TX_ID, 0x00000000}, {CS40L20_MDSYNC_PWR_CTRL, 0x00000002}, {CS40L20_MDSYNC_DATA_TX, 0x00000000}, @@ -75,12 +71,12 @@ const struct reg_default cs40l20_reg[CS40L20_MAX_CACHE_REG] = { {CS40L20_BSTCVRT_DCM_CTRL, 0x00002001}, {CS40L20_BSTCVRT_DCM_MODE_FORCE, 0x00000000}, {CS40L20_BSTCVRT_OVERVOLT_CTRL, 0x00000130}, - {CS40L20_VI_VOL_POL, 0x080C0806}, + {CS40L20_VI_VOL_POL, 0x08000800}, {CS40L20_DTEMP_WARN_THLD, 0x00000002}, {CS40L20_DTEMP_EN, 0x00000000}, {CS40L20_VPVBST_FS_SEL, 0x00000001}, {CS40L20_SP_ENABLES, 0x00000000}, - {CS40L20_SP_RATE_CTRL, 0x01000028}, + {CS40L20_SP_RATE_CTRL, 0x00000028}, {CS40L20_SP_FORMAT, 0x18180200}, {CS40L20_SP_HIZ_CTRL, 0x00000002}, {CS40L20_SP_FRAME_TX_SLOT, 0x03020100}, @@ -115,8 +111,6 @@ const struct reg_default cs40l20_reg[CS40L20_MAX_CACHE_REG] = { {CS40L20_NG_CFG, 0x00000033}, {CS40L20_AMP_GAIN_CTRL, 0x00000273}, {CS40L20_DAC_MSM_CFG, 0x00580000}, - {CS40L20_GPIO_STATUS1, 0x00000000}, - {CS40L20_GPIO1_CTRL1, 0xE1000001}, {CS40L20_GPIO2_CTRL1, 0xE1000001}, {CS40L20_MIXER_NGATE_CFG, 0x00000000}, {CS40L20_MIXER_NGATE_CH1_CFG, 0x00000303}, @@ -618,6 +612,8 @@ bool cs40l20_volatile_reg(struct device *dev, unsigned int reg) case CS40L20_SFT_RESET: case CS40L20_FABID: case CS40L20_REVID: + case CS40L20_PWR_CTRL2: + case CS40L20_GPIO_PAD_CONTROL: case CS40L20_IRQ1_STATUS: case CS40L20_IRQ1_STATUS1: case CS40L20_IRQ1_STATUS2: @@ -666,6 +662,8 @@ bool cs40l20_volatile_reg(struct device *dev, unsigned int reg) case CS40L20_IRQ2_POL3: case CS40L20_IRQ2_POL4: case CS40L20_IRQ2_DB3: + case CS40L20_GPIO_STATUS1: + case CS40L20_GPIO1_CTRL1: case CS40L20_DSP1_XMEM_PACK_0 ... CS40L20_DSP1_XMEM_PACK_3068: case CS40L20_DSP1_XMEM_UNPACK32_0 ... CS40L20_DSP1_XMEM_UNPACK32_2046: case CS40L20_DSP1_XMEM_UNPACK24_0 ... CS40L20_DSP1_XMEM_UNPACK24_4093: diff --git a/drivers/misc/cs40l20.h b/drivers/misc/cs40l20.h index c25848300af2..c16078766aea 100644 --- a/drivers/misc/cs40l20.h +++ b/drivers/misc/cs40l20.h @@ -527,7 +527,7 @@ #define CS40L20_OTP_TRIM_35 0x0000400C #define CS40L20_OTP_TRIM_36 0x00002030 -#define CS40L20_MAX_CACHE_REG 0x0000006F +#define CS40L20_MAX_CACHE_REG 0x00000069 #define CS40L20_SCLK_MSTR_MASK 0x10 #define CS40L20_SCLK_MSTR_SHIFT 4 @@ -554,9 +554,6 @@ #define CS40L20_TEMP_THLD_MASK 0x03 -#define CS40L20_PDM_MODE_MASK 0x01 -#define CS40L20_PDM_MODE_SHIFT 0 - #define CS40L20_CH_MEM_DEPTH_MASK 0x07 #define CS40L20_CH_MEM_DEPTH_SHIFT 0 #define CS40L20_CH_HDRM_CTL_MASK 0x007F0000