From b00cba19fc98db950a3d522a8506ea671b2d9b9e Mon Sep 17 00:00:00 2001
From: Nitin Rawat <nitirawa@qti.qualcomm.com>
Date: Wed, 8 Jul 2020 02:42:53 +0530
Subject: [PATCH] ARM: dts: msm: Enable SMMU bypass mode for stage 1 of UFS

Enable SMMU in bypass mode for stage1 of UFS.

Change-Id: I0515f1d69ec225c382d12a5e05e10a326e16382c
---
 qcom/shima.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 985830d4a0d1..0d7124e3a9f4 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -1167,6 +1167,11 @@
 		 reset-gpios = <&tlmm 204 GPIO_ACTIVE_LOW>;
 		 resets = <&gcc GCC_UFS_PHY_BCR>;
 		 reset-names = "rst";
+
+		 iommus = <&apps_smmu 0x80 0x0>;
+		 qcom,iommu-dma = "bypass";
+		 dma-coherent;
+
 		 status = "disabled";
 	};