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ASoC: wcd938x: Do not enable hold_off while enabling watchdog

Browse source 
Hold_off bit for enabling watchdog will enable mute until
there is a block reset and watchdog bits aren't toggled.
Disable hold_off bit so that wcd is recovered from mute
instantly once watchdog occurred.

Change-Id: Ia87593ead05dde4e31a0afefd6ffaca89bb95448
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
This commit is contained in:
Vatsal Bucha 2020-04-01 21:25:25 +05:30 • committed by Gerrit - the friendly Code Review server
commit b00df5a5c7
1 changed files with 10 additions and 10 deletions
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20
asoc/codecs/wcd938x/wcd938x.c
View file

@ -801,7 +801,7 @@ static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
usleep_range(100, 110);
set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
break;
case SND_SOC_DAPM_POST_PMU:
/*
@ -881,7 +881,7 @@ static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
0x10, 0x00);
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
wcd_cls_h_fsm(component, &wcd938x->clsh_info,
WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_HPHR,
@ -937,7 +937,7 @@ static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
usleep_range(100, 110);
set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
break;
case SND_SOC_DAPM_POST_PMU:
/*
@ -1017,7 +1017,7 @@ static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
0x20, 0x00);
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
wcd_cls_h_fsm(component, &wcd938x->clsh_info,
WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_HPHL,
@ -1050,7 +1050,7 @@ static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
wcd938x->rx_swr_dev->dev_num,
true);
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
break;
case SND_SOC_DAPM_POST_PMU:
/* 1 msec delay as per HW requirement */
@ -1078,7 +1078,7 @@ static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
/* 1 msec delay as per HW requirement */
usleep_range(1000, 1010);
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
wcd_cls_h_fsm(component, &wcd938x->clsh_info,
WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_AUX,
@ -1122,11 +1122,11 @@ static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_PDM_WD_CTL2,
0x05, 0x05);
0x01, 0x01);
else
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_PDM_WD_CTL0,
0x17, 0x13);
0x07, 0x03);
if (!wcd938x->comp1_enable)
snd_soc_component_update_bits(component,
WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
@ -1181,11 +1181,11 @@ static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_PDM_WD_CTL2,
0x05, 0x00);
0x01, 0x00);
else
snd_soc_component_update_bits(component,
WCD938X_DIGITAL_PDM_WD_CTL0,
0x17, 0x00);
0x07, 0x00);
wcd_cls_h_fsm(component, &wcd938x->clsh_info,
WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_EAR,