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Merge "PCI: Disable L0s support for SDX65 with QPS615 on CPE platform"

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qctecmdr 2024-06-03 08:03:11 -07:00 • committed by Gerrit - the friendly Code Review server
commit b0184b0120
1 changed files with 16 additions and 0 deletions
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16
drivers/pci/quirks.c
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@ -2334,6 +2334,22 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
/*
* QPS615 PCIe-PCI bridge devices cause AER timeout errors on the upstream
* PCIe root port when L0s is enabled in CPE platform with SDX65.
* Disable L0s for both QPS615 and SDX65 when QPS615 switch is
* present.
*/
static void quirk_disable_aspm_qps615_l0s(struct pci_dev *dev)
{
struct pci_dev *p;
pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
p = pci_get_device(PCI_VENDOR_ID_QCOM, 0x0308, NULL);
pci_disable_link_state(p, PCIE_LINK_STATE_L0S);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA, 0x0623, quirk_disable_aspm_qps615_l0s);
static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
{
pci_info(dev, "Disabling ASPM L0s/L1\n");