From b0e8e846ed29da33fecbb61852182baa89c1b6ab Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Wed, 24 Mar 2021 12:32:21 +0530 Subject: [PATCH] pinctrl: qcom: Fix msm_dirconn_uncfg_reg() to correctly set intr cfg msm_dirconn_uncfg_reg() currently uses readl_/writel_relaxed() which do not check for per tile address for gpio intr cfg. Replace to use msm_readl/writel_intr_cfg() which takes care of per tile. While at this also fix dir_conn_reg to use per tile gpio cfg. Change-Id: If87e35f2943593c0723bd88a29d483fed70f7041 Signed-off-by: Maulik Shah --- drivers/pinctrl/qcom/pinctrl-msm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 9430df6269c5..0fffc6a2eb3f 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -997,10 +997,11 @@ static void msm_dirconn_uncfg_reg(struct irq_data *d, u32 offset) raw_spin_lock_irqsave(&pctrl->lock, flags); g = &pctrl->soc->groups[d->hwirq]; - writel_relaxed(val, pctrl->regs + g->dir_conn_reg + (offset * 4)); - val = readl_relaxed(pctrl->regs + g->intr_cfg_reg); + writel_relaxed(val, pctrl->regs[g->tile] + g->dir_conn_reg + + (offset * 4)); + val = msm_readl_intr_cfg(pctrl, g); val &= ~BIT(g->dir_conn_en_bit); - writel_relaxed(val, pctrl->regs + g->intr_cfg_reg); + msm_writel_intr_cfg(val, pctrl, g); raw_spin_unlock_irqrestore(&pctrl->lock, flags); }