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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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[PATCH] ppc32: Add 440SPe support
Add support for the AMCC PowerPC 440SPe SoC, including PCI Express in root port mode. Signed-off-by: Roland Dreier <[email protected]> Cc: Matt Porter <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
This commit is contained in:
Roland Dreier
Linus Torvalds
parent
41aace4fe8
commit
b0f7b8bc57
12 changed files with 904 additions and 19 deletions
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@ -41,6 +41,9 @@
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#if defined(CONFIG_440SP)
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#define UART0_PHYS_ERPN 1
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#define UART0_PHYS_IO_BASE 0xf0000200
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#elif defined(CONFIG_440SPE)
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#define UART0_PHYS_ERPN 4
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#define UART0_PHYS_IO_BASE 0xf0000200
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#elif defined(CONFIG_440EP)
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#define UART0_PHYS_IO_BASE 0xe0000000
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#else
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@ -61,6 +64,11 @@
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#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
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#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
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#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
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#elif defined(CONFIG_440SPE)
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#define PPC44x_IO_PAGE 0x0000000400000000ULL
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#define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL
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#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
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#define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL
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#elif defined(CONFIG_440EP)
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#define PPC44x_IO_PAGE 0x0000000000000000ULL
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#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
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@ -76,7 +84,7 @@
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/*
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* 36-bit trap ranges
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*/
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#if defined(CONFIG_440SP)
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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#define PPC44x_IO_LO 0xf0000000UL
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#define PPC44x_IO_HI 0xf0000fffUL
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#define PPC44x_PCI0CFG_LO 0x0ec00000UL
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@ -114,7 +122,7 @@
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*/
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/* CPRs (440GX and 440SP) */
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/* CPRs (440GX and 440SP/440SPe) */
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#define DCRN_CPR_CONFIG_ADDR 0xc
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#define DCRN_CPR_CONFIG_DATA 0xd
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@ -135,7 +143,7 @@
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mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
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mtdcr(DCRN_CPR_CONFIG_DATA, data);})
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/* SDRs (440GX and 440SP) */
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/* SDRs (440GX and 440SP/440SPe) */
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#define DCRN_SDR_CONFIG_ADDR 0xe
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#define DCRN_SDR_CONFIG_DATA 0xf
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#define DCRN_SDR_PFC0 0x4100
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@ -185,7 +193,7 @@
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mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
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mtdcr(DCRN_SDR_CONFIG_DATA,data);})
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/* DMA (excluding 440SP) */
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/* DMA (excluding 440SP/440SPe) */
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#define DCRN_DMA0_BASE 0x100
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#define DCRN_DMA1_BASE 0x108
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#define DCRN_DMA2_BASE 0x110
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@ -205,12 +213,20 @@
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/* UIC */
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#define DCRN_UIC0_BASE 0xc0
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#define DCRN_UIC1_BASE 0xd0
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#define DCRN_UIC2_BASE 0x210
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#define DCRN_UICB_BASE 0x200
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#define UIC0 DCRN_UIC0_BASE
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#define UIC1 DCRN_UIC1_BASE
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#ifdef CONFIG_440SPE
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#define DCRN_UIC2_BASE 0xe0
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#define DCRN_UIC3_BASE 0xf0
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#define UIC2 DCRN_UIC2_BASE
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#define UIC3 DCRN_UIC3_BASE
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#else
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#define DCRN_UIC2_BASE 0x210
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#define DCRN_UICB_BASE 0x200
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#define UIC2 DCRN_UIC2_BASE
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#define UICB DCRN_UICB_BASE
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#endif
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#define DCRN_UIC_SR(base) (base + 0x0)
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#define DCRN_UIC_ER(base) (base + 0x2)
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@ -223,6 +239,12 @@
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#define UIC0_UIC1NC 0x00000002
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#ifdef CONFIG_440SPE
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#define UIC0_UIC1NC 0x00000002
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#define UIC0_UIC2NC 0x00200000
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#define UIC0_UIC3NC 0x00008000
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#endif
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#define UICB_UIC0NC 0x40000000
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#define UICB_UIC1NC 0x10000000
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#define UICB_UIC2NC 0x04000000
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@ -302,8 +324,8 @@
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#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
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#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
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#if defined(CONFIG_440SP)
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/* 440SP PLB Arbiter DCRs */
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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/* 440SP/440SPe PLB Arbiter DCRs */
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#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */
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#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */
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@ -430,9 +452,13 @@
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#define PPC44x_MEM_SIZE_1G 0x40000000
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#define PPC44x_MEM_SIZE_2G 0x80000000
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/* 440SP memory controller DCRs */
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/* 440SP/440SPe memory controller DCRs */
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#define DCRN_MQ0_BS0BAS 0x40
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#define DCRN_MQ0_BS1BAS 0x41
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#if defined(CONFIG_440SP)
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#define MQ0_NUM_BANKS 2
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#elif defined(CONFIG_440SPE)
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#define MQ0_NUM_BANKS 4
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#endif
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#define MQ0_CONFIG_SIZE_MASK 0x0000fff0
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#define MQ0_CONFIG_SIZE_8M 0x0000ffc0
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@ -444,8 +470,9 @@
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#define MQ0_CONFIG_SIZE_512M 0x0000f000
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#define MQ0_CONFIG_SIZE_1G 0x0000e000
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#define MQ0_CONFIG_SIZE_2G 0x0000c000
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#define MQ0_CONFIG_SIZE_4G 0x00008000
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/* Internal SRAM Controller 440GX/440SP */
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/* Internal SRAM Controller 440GX/440SP/440SPe */
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#define DCRN_SRAM0_BASE 0x000
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#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020)
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@ -469,7 +496,7 @@
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#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a)
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#define SRAM_DPC_ENABLE 0x80000000
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/* L2 Cache Controller 440GX/440SP */
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/* L2 Cache Controller 440GX/440SP/440SPe */
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#define DCRN_L2C0_CFG 0x030
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#define L2C_CFG_L2M 0x80000000
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#define L2C_CFG_ICU 0x40000000
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@ -633,8 +660,10 @@
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#define IIC_CLOCK 50
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#undef NR_UICS
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#ifdef CONFIG_440GX
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#if defined(CONFIG_440GX)
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#define NR_UICS 3
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#elif defined(CONFIG_440SPE)
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#define NR_UICS 4
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#else
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#define NR_UICS 2
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#endif
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