From 5117e923e0aa7d3351a974195b8c72468f15737b Mon Sep 17 00:00:00 2001
From: Mao Jinlong <jinlmao@qti.qualcomm.com>
Date: Thu, 13 Feb 2020 17:12:19 +0800
Subject: [PATCH] ARM: dts: msm: Add cti trig_out gpio for Lahaina

Add pinctil setting to cti trig_out gpio and configure
trig_out gpio for Lahaina.

Change-Id: I31c766aac6a35ca5960a6fa680dfdc84652e70d7
---
 qcom/lahaina-coresight.dtsi |  4 ++++
 qcom/lahaina-pinctrl.dtsi   | 13 +++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi
index 746d801d6ded..570e06112f6c 100644
--- a/qcom/lahaina-coresight.dtsi
+++ b/qcom/lahaina-coresight.dtsi
@@ -3120,6 +3120,10 @@
 
 		clocks = <&clock_aop QDSS_CLK>;
 		clock-names = "apb_pclk";
+
+		qcom,cti-gpio-trigout = <0>;
+		pinctrl-names = "cti-trigout-pctrl";
+		pinctrl-0 = <&trigout_a>;
 	};
 
 	cti3: cti@6013000 {
diff --git a/qcom/lahaina-pinctrl.dtsi b/qcom/lahaina-pinctrl.dtsi
index f7c8bdd91c92..1cabdb7fa6fe 100644
--- a/qcom/lahaina-pinctrl.dtsi
+++ b/qcom/lahaina-pinctrl.dtsi
@@ -13,6 +13,19 @@
 		};
 	};
 
+	trigout_a: trigout_a {
+		mux {
+			pins = "gpio14";
+			function = "qdss_cti";
+		};
+
+		config {
+			pins = "gpio14";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
 	qupv3_se3_2uart_pins: qupv3_se3_2uart_pins {
 		qupv3_se3_2uart_active: qupv3_se3_2uart_active {
 			mux {