From b1332729e2de7edd53e96febedd86afd09d41c92 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 23 Aug 2020 15:30:04 +0530 Subject: [PATCH] clk: qcom: shima: Fix stuck at off warnings during probe Add CLK_DONT_HOLD_STATE flag to avoid the framework from placing a proxy vote to enable the clocks during probe since these GPU clocks are failing to turn on as their corresponding GDSC is not enabled yet. Change-Id: I4771d1c5696a069d0d67d407de3a7a5b1f5b139e Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/gcc-shima.c | 2 ++ drivers/clk/qcom/gpucc-shima.c | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-shima.c b/drivers/clk/qcom/gcc-shima.c index 95f5dcb4ed4b..56b1f7d276c4 100644 --- a/drivers/clk/qcom/gcc-shima.c +++ b/drivers/clk/qcom/gcc-shima.c @@ -1861,6 +1861,7 @@ static struct clk_branch gcc_gpu_memnoc_gfx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_memnoc_gfx_clk", + .flags = CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, @@ -1874,6 +1875,7 @@ static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_snoc_dvm_gfx_clk", + .flags = CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, diff --git a/drivers/clk/qcom/gpucc-shima.c b/drivers/clk/qcom/gpucc-shima.c index 7cab184c75d8..912cb6904fc6 100644 --- a/drivers/clk/qcom/gpucc-shima.c +++ b/drivers/clk/qcom/gpucc-shima.c @@ -306,7 +306,7 @@ static struct clk_branch gpu_cc_cx_gmu_clk = { .hw = &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, @@ -346,6 +346,7 @@ static struct clk_branch gpu_cc_cxo_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cxo_clk", + .flags = CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, @@ -412,7 +413,7 @@ static struct clk_branch gpu_cc_hub_cx_int_clk = { .hw = &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, },