From 65b24ebabcae62f6bec1cba3b65dc5612ce21758 Mon Sep 17 00:00:00 2001 From: Sudheer Papothi Date: Fri, 31 Jul 2020 10:34:29 +0530 Subject: [PATCH] ASoC: tx-macro: Allow regcache sync during clock enablement Allow regcache sync during clock enable to make sure the registers are in proper state before the usecase. Change-Id: I8a9214e460c7f77759d1956e0e7e2d6b2f5b3d3a Signed-off-by: Sudheer Papothi --- asoc/codecs/bolero/tx-macro.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/asoc/codecs/bolero/tx-macro.c b/asoc/codecs/bolero/tx-macro.c index 4f74c9dc31fd..ad7681ebcf0a 100644 --- a/asoc/codecs/bolero/tx-macro.c +++ b/asoc/codecs/bolero/tx-macro.c @@ -237,11 +237,11 @@ static int tx_macro_mclk_enable(struct tx_macro_priv *tx_priv, } bolero_clk_rsc_fs_gen_request(tx_priv->dev, true); + regcache_mark_dirty(regmap); + regcache_sync_region(regmap, + TX_START_OFFSET, + TX_MAX_OFFSET); if (tx_priv->tx_mclk_users == 0) { - regcache_mark_dirty(regmap); - regcache_sync_region(regmap, - TX_START_OFFSET, - TX_MAX_OFFSET); /* 9.6MHz MCLK, set value 0x00 if other frequency */ regmap_update_bits(regmap, BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01);