From 3c5b9fce970dc8b79de1a00266e3b6d5aafb6a9f Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 7 Apr 2020 15:31:39 +0530 Subject: [PATCH 1/3] clk: qcom: clk-alpha-pll: Add support for Lucid PLL print registers Lucid/Lucid5LPE PLL print registers are required to get the PLL values from the debugfs, thus add support for the same. Change-Id: I3a9eac33c80a98a0e612d9c7f740067aa54bde44 Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 64 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 65 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 35af4070446e..ace58135769b 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2525,6 +2525,64 @@ static int alpha_pll_lucid_is_enabled(struct clk_hw *hw) return lucid_pll_is_enabled(pll, pll->clkr.regmap); } +static void lucid_pll_list_registers(struct seq_file *f, + struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + int size, i, val; + + static struct clk_register_data data[] = { + {"PLL_MODE", PLL_OFF_MODE}, + {"PLL_L_VAL", PLL_OFF_L_VAL}, + {"PLL_CAL_L_VAL", PLL_OFF_CAL_L_VAL}, + {"PLL_USER_CTL", PLL_OFF_USER_CTL}, + {"PLL_USER_CTL_U", PLL_OFF_USER_CTL_U}, + {"PLL_USER_CTL_U1", PLL_OFF_USER_CTL_U1}, + {"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL}, + {"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U}, + {"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1}, + {"PLL_TEST_CTL", PLL_OFF_TEST_CTL}, + {"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U}, + {"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1}, + {"PLL_STATUS", PLL_OFF_STATUS}, + {"PLL_OPMODE", PLL_OFF_OPMODE}, + {"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL}, + }; + + static struct clk_register_data data1[] = { + {"APSS_PLL_VOTE", 0x0}, + }; + + size = ARRAY_SIZE(data); + + for (i = 0; i < size; i++) { + regmap_read(pll->clkr.regmap, pll->offset + + pll->regs[data[i].offset], &val); + seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val); + } + + regmap_read(pll->clkr.regmap, pll->offset + + pll->regs[data[0].offset], &val); + + if (val & PLL_FSM_ENA) { + regmap_read(pll->clkr.regmap, pll->clkr.enable_reg + + data1[0].offset, &val); + seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val); + } +} + +static struct clk_regmap_ops clk_lucid_pll_regmap_ops = { + .list_registers = &lucid_pll_list_registers, +}; + +static void clk_lucid_pll_init(struct clk_hw *hw) +{ + struct clk_regmap *rclk = to_clk_regmap(hw); + + if (!rclk->ops) + rclk->ops = &clk_lucid_pll_regmap_ops; +} + const struct clk_ops clk_alpha_pll_lucid_ops = { .prepare = alpha_pll_lucid_prepare, .unprepare = clk_unprepare_regmap, @@ -2536,6 +2594,8 @@ const struct clk_ops clk_alpha_pll_lucid_ops = { .recalc_rate = alpha_pll_lucid_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .set_rate = alpha_pll_lucid_set_rate, + .debug_init = clk_common_debug_init, + .init = clk_lucid_pll_init, #ifdef CONFIG_COMMON_CLK_QCOM_DEBUG .list_rate_vdd_level = clk_list_rate_vdd_level, #endif @@ -2554,6 +2614,7 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { .round_rate = clk_alpha_pll_round_rate, .set_rate = alpha_pll_lucid_5lpe_set_rate, .debug_init = clk_common_debug_init, + .init = clk_lucid_pll_init, #ifdef CONFIG_COMMON_CLK_QCOM_DEBUG .list_rate_vdd_level = clk_list_rate_vdd_level, #endif @@ -2570,6 +2631,8 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_ops = { .is_enabled = alpha_pll_lucid_is_enabled, .recalc_rate = alpha_pll_lucid_recalc_rate, .round_rate = clk_alpha_pll_round_rate, + .debug_init = clk_common_debug_init, + .init = clk_lucid_pll_init, #ifdef CONFIG_COMMON_CLK_QCOM_DEBUG .list_rate_vdd_level = clk_list_rate_vdd_level, #endif @@ -2594,6 +2657,7 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { .recalc_rate = alpha_pll_lucid_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .debug_init = clk_common_debug_init, + .init = clk_lucid_pll_init, #ifdef CONFIG_COMMON_CLK_QCOM_DEBUG .list_rate_vdd_level = clk_list_rate_vdd_level, #endif diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 9e560ee8daa5..251e5188248c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -25,6 +25,7 @@ enum { }; enum { + PLL_OFF_MODE, PLL_OFF_L_VAL, PLL_OFF_CAL_L_VAL, PLL_OFF_ALPHA_VAL, From f299e23e9a6d1e96657585b72742408c85c961b7 Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Wed, 8 Apr 2020 10:10:11 +0530 Subject: [PATCH 2/3] clk: qcom: clk-alpha-pll: Add support for Zonda print registers Zonda PLL print registers are required to get the PLL values from the debugfs, thus add support for the same. Change-Id: Ie8df05a84c972f412ee6d612ef5a6dde2ae98f9b Signed-off-by: Naveen Yadav --- drivers/clk/qcom/clk-alpha-pll.c | 62 ++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index ace58135769b..972d84ba72ad 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1447,6 +1447,61 @@ const struct clk_ops clk_trion_fixed_pll_ops = { }; EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops); +static void clk_alpha_pll_zonda_list_registers(struct seq_file *f, + struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + int size, i, val; + + static struct clk_register_data data[] = { + {"PLL_MODE", PLL_OFF_MODE}, + {"PLL_L_VAL", PLL_OFF_L_VAL}, + {"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL}, + {"PLL_USER_CTL", PLL_OFF_USER_CTL}, + {"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL}, + {"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U}, + {"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1}, + {"PLL_TEST_CTL", PLL_OFF_TEST_CTL}, + {"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U}, + {"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1}, + {"PLL_OPMODE", PLL_OFF_OPMODE}, + {"PLL_STATUS", PLL_OFF_STATUS}, + }; + + static struct clk_register_data data1[] = { + {"APSS_PLL_VOTE", 0x0}, + }; + + size = ARRAY_SIZE(data); + + for (i = 0; i < size; i++) { + regmap_read(pll->clkr.regmap, pll->offset + + pll->regs[data[i].offset], &val); + seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val); + } + + regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[0].offset], + &val); + + if (val & PLL_FSM_ENA) { + regmap_read(pll->clkr.regmap, pll->clkr.enable_reg + + data1[0].offset, &val); + seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val); + } +} + +static struct clk_regmap_ops clk_alpha_pll_zonda_regmap_ops = { + .list_registers = clk_alpha_pll_zonda_list_registers, +}; + +static void clk_alpha_pll_zonda_init(struct clk_hw *hw) +{ + struct clk_regmap *rclk = to_clk_regmap(hw); + + if (!rclk->ops) + rclk->ops = &clk_alpha_pll_zonda_regmap_ops; +} + const struct clk_ops clk_alpha_pll_zonda_ops = { .prepare = clk_prepare_regmap, .unprepare = clk_unprepare_regmap, @@ -1458,6 +1513,8 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { .recalc_rate = clk_zonda_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .set_rate = clk_zonda_pll_set_rate, + .debug_init = clk_common_debug_init, + .init = clk_alpha_pll_zonda_init, #ifdef CONFIG_COMMON_CLK_QCOM_DEBUG .list_rate_vdd_level = clk_list_rate_vdd_level, #endif @@ -1475,6 +1532,11 @@ const struct clk_ops clk_alpha_pll_zonda_5lpe_ops = { .recalc_rate = clk_zonda_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .set_rate = clk_zonda_pll_set_rate, + .debug_init = clk_common_debug_init, + .init = clk_alpha_pll_zonda_init, +#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG + .list_rate_vdd_level = clk_list_rate_vdd_level, +#endif }; EXPORT_SYMBOL(clk_alpha_pll_zonda_5lpe_ops); From 3cfeff426a4f955132b95cef3cc72a8f620d9d30 Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Wed, 8 Apr 2020 10:11:27 +0530 Subject: [PATCH 3/3] clk: qcom: clk-alpha-pll: Add support for Huayra print registers Huayra PLL print registers are required to get the PLL values from the debugfs, thus add support for the same. Change-Id: I439f64646d5995943cf8d0ef94daf3f85cd0ae45 Signed-off-by: Naveen Yadav --- drivers/clk/qcom/clk-alpha-pll.c | 57 ++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 972d84ba72ad..394afe70e3e5 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1377,6 +1377,61 @@ static void clk_alpha_pll_init(struct clk_hw *hw) rclk->ops = &clk_alpha_pll_regmap_ops; } +static void clk_alpha_pll_huayra_list_registers(struct seq_file *f, + struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + int size, i, val; + + static struct clk_register_data data[] = { + {"PLL_MODE", PLL_OFF_MODE}, + {"PLL_L_VAL", PLL_OFF_L_VAL}, + {"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL}, + {"PLL_USER_CTL", PLL_OFF_USER_CTL}, + {"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL}, + {"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U}, + {"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1}, + {"PLL_TEST_CTL", PLL_OFF_TEST_CTL}, + {"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U}, + {"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1}, + {"PLL_OPMODE", PLL_OFF_OPMODE}, + {"PLL_STATUS", PLL_OFF_STATUS}, + }; + + static struct clk_register_data data1[] = { + {"APSS_PLL_VOTE", 0x0}, + }; + + size = ARRAY_SIZE(data); + + for (i = 0; i < size; i++) { + regmap_read(pll->clkr.regmap, pll->offset + + pll->regs[data[i].offset], &val); + seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val); + } + + regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[0].offset], + &val); + + if (val & PLL_FSM_ENA) { + regmap_read(pll->clkr.regmap, pll->clkr.enable_reg + + data1[0].offset, &val); + seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val); + } +} + +static struct clk_regmap_ops clk_alpha_pll_huayra_regmap_ops = { + .list_registers = clk_alpha_pll_huayra_list_registers, +}; + +static void clk_alpha_pll_huayra_init(struct clk_hw *hw) +{ + struct clk_regmap *rclk = to_clk_regmap(hw); + + if (!rclk->ops) + rclk->ops = &clk_alpha_pll_huayra_regmap_ops; +} + const struct clk_ops clk_alpha_pll_ops = { .prepare = clk_prepare_regmap, .unprepare = clk_unprepare_regmap, @@ -1407,6 +1462,8 @@ const struct clk_ops clk_alpha_pll_huayra_ops = { .recalc_rate = alpha_pll_huayra_recalc_rate, .round_rate = alpha_pll_huayra_round_rate, .set_rate = alpha_pll_huayra_set_rate, + .debug_init = clk_common_debug_init, + .init = clk_alpha_pll_huayra_init, #ifdef CONFIG_COMMON_CLK_QCOM_DEBUG .list_rate_vdd_level = clk_list_rate_vdd_level, #endif