mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 12:58:12 -04:00
Merge 14e1479280 on remote branch
Change-Id: I1e3812454afb6a1951367ea62dc5f8f62e7a76c3
This commit is contained in:
Linux Build Service Account
commit
b236035824
21 changed files with 1093 additions and 581 deletions
219
fw/htt.h
219
fw/htt.h
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@ -234,9 +234,12 @@
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* 3.107 Add traffic_end_indication bitfield in htt_tx_msdu_desc_ext2_t.
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* 3.108 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP def.
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* 3.109 Add HTT_T2H RX_ADDBA_EXTN,RX_DELBA_EXTN defs.
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* 3.110 Add more word_mask fields in htt_tx_monitor_cfg_t.
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* 3.111 Add RXPCU filter enable flag in RX_RING_SELECTION_CFG msg.
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* 3.112 Add logical_link_id field in rx_peer_metadata_v1.
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*/
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#define HTT_CURRENT_VERSION_MAJOR 3
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#define HTT_CURRENT_VERSION_MINOR 109
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#define HTT_CURRENT_VERSION_MINOR 112
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#define HTT_NUM_TX_FRAG_DESC 1024
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@ -420,7 +423,7 @@ PREPACK struct htt_option_tlv_ll_bus_addr_size_t {
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* downloads over the host --> target bus are as slow as or slower than
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* the transmissions over the WLAN PHY. For cases where the bus is faster
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* than the WLAN PHY, the target will transmit relatively large A-MPDUs,
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* and consquently will send one TX_COMPL_IND message that covers several
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* and consequently will send one TX_COMPL_IND message that covers several
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* tx frames. For cases where the WLAN PHY is faster than the bus,
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* the target will end up transmitting very short A-MPDUs, and consequently
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* sending many TX_COMPL_IND messages, which each cover a very small number
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@ -463,7 +466,7 @@ PREPACK struct htt_option_tlv_hl_suppress_tx_compl_ind_t {
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* The MAX_TX_QUEUE_GROUPS TLV can be sent from the target to the host as
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* a suffix to the VERSION_CONF message. If the host has specified in the
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* VER_REQ message a limit on the number of tx queue groups the host can
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* supprt, the target shall limit its specification of the maximum tx groups
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* support, the target shall limit its specification of the maximum tx groups
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* to be no larger than this host-specified limit.
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*
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* If the target does not provide a MAX_TX_QUEUE_GROUPS TLV, then the host
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@ -760,6 +763,9 @@ typedef enum {
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HTT_STATS_LATENCY_PROF_CAL_STATS_TAG = 168, /* htt_latency_prof_cal_stats_tlv */
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HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG = 169, /* htt_tx_pdev_muedca_params_stats_tlv_v */
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HTT_STATS_PDEV_BW_MGR_STATS_TAG = 170, /* htt_pdev_bw_mgr_stats_tlv */
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HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v */
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HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, /* htt_txbf_ofdma_ax_steer_mpdu_stats_tlv */
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HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG = 173, /* htt_txbf_ofdma_be_steer_mpdu_stats_tlv */
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HTT_STATS_MAX_TAG,
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@ -1131,7 +1137,7 @@ PREPACK struct htt_tx_msdu_desc ## _paddr_bits_ ## _t \
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A_UINT16 chanfreq; \
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\
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/* Reason reserved is commented is increasing the htt structure size \
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* leads to some wierd issues. Contact Raj/Kyeyoon for more info \
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* leads to some weird issues. \
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* A_UINT32 reserved_dword3_bits0_31; \
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*/ \
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} POSTPACK
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@ -2716,7 +2722,7 @@ typedef enum {
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/**
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* @brief HTT TX WBM Completion from firmware to host
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* @details
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* This structure is passed from firmware to host overlayed on wbm_release_ring
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* This structure is passed from firmware to host overlaid on wbm_release_ring
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* DWORD 3 and 4 for software based completions (Exception frames and
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* TQM bypass frames)
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* For software based completions, wbm_release_ring->release_source_module will
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@ -2809,7 +2815,7 @@ PREPACK struct htt_tx_wbm_completion {
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* @details
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* This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
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* (WBM) offload HW.
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* This structure is passed from firmware to host overlayed on wbm_release_ring
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* This structure is passed from firmware to host overlaid on wbm_release_ring
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* For software based completions, release_source_module will
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* be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using
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* struct wbm_release_ring and then switch to this after looking at
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@ -2888,7 +2894,7 @@ PREPACK struct htt_tx_wbm_completion_v2 {
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* @details
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* This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
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* (WBM) offload HW.
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* This structure is passed from firmware to host overlayed on wbm_release_ring
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* This structure is passed from firmware to host overlaid on wbm_release_ring
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* For software based completions, release_source_module will
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* be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using
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* struct wbm_release_ring and then switch to this after looking at
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@ -2975,7 +2981,7 @@ typedef enum {
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* @details
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* This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
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* (WBM) offload HW.
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* This structure is passed from firmware to host overlayed on wbm_release_ring.
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* This structure is passed from firmware to host overlaid on wbm_release_ring.
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* used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP
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* or HTT_TX_FW2WBM_TX_STATUS_TTL
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*/
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@ -3106,7 +3112,7 @@ PREPACK struct htt_tx_wbm_transmit_status {
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* @details
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* This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
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* (WBM) offload HW.
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* This structure is passed from firmware to host overlayed on wbm_release_ring.
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* This structure is passed from firmware to host overlaid on wbm_release_ring.
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* used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_REINJECT.
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*/
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PREPACK struct htt_tx_wbm_reinject_status {
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@ -3123,7 +3129,7 @@ PREPACK struct htt_tx_wbm_reinject_status {
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* @details
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* This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
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* (WBM) offload HW.
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* This structure is passed from firmware to host overlayed on wbm_release_ring.
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* This structure is passed from firmware to host overlaid on wbm_release_ring.
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* used only if tx_status is HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY.
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* FW sends SA addresses to host for all multicast/broadcast packets received on
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* STA side.
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@ -5130,7 +5136,7 @@ enum htt_msi_setup_type {
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* 3'b010: 4 usec
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* 3'b011: 8 usec (default)
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* 3'b100: 16 usec
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* Others: Reserverd
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* Others: Reserved
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* b'19 - response_required:
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* Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
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* b'20 - ipa_drop_flag:
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@ -5531,38 +5537,43 @@ enum htt_srng_ring_id {
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*
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* The message would appear as follows:
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*
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* |31 28|27|26|25|24|23 16|15 | 11| 10|9 8|7 0|
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* |-----+--+--+--+--+----------------+----+---+---+---+---------------|
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* |rsvd1|DT|OV|PS|SS| ring_id | pdev_id | msg_type |
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* |-------------------------------------------------------------------|
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* | rsvd2 | ring_buffer_size |
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* |-------------------------------------------------------------------|
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* | packet_type_enable_flags_0 |
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* |-------------------------------------------------------------------|
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* | packet_type_enable_flags_1 |
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* |-------------------------------------------------------------------|
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* | packet_type_enable_flags_2 |
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* |-------------------------------------------------------------------|
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* | packet_type_enable_flags_3 |
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* |-------------------------------------------------------------------|
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* | tlv_filter_in_flags |
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* |-------------------------------------------------------------------|
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* | rx_header_offset | rx_packet_offset |
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* |-------------------------------------------------------------------|
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* | rx_mpdu_start_offset | rx_mpdu_end_offset |
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* |-------------------------------------------------------------------|
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* | rx_msdu_start_offset | rx_msdu_end_offset |
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* |-------------------------------------------------------------------|
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* | rsvd3 | rx_attention_offset |
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* |-------------------------------------------------------------------|
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* | rsvd4 | mo| fp| rx_drop_threshold |
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* | |ndp|ndp| |
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* |-------------------------------------------------------------------|
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* |31 28|27|26|25|24|23|22|21 19|18 16|15 | 11| 10|9 8|7 0|
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* |-----+--+--+--+--+-----------------+----+---+---+---+---------------|
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* |rsvd1|DT|OV|PS|SS| ring_id | pdev_id | msg_type |
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* |-----------------------+-----+-----+--------------------------------|
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* |rsvd2|RX|RXHDL| CLD | CLC | CLM | ring_buffer_size |
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* |--------------------------------------------------------------------|
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* | packet_type_enable_flags_0 |
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* |--------------------------------------------------------------------|
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* | packet_type_enable_flags_1 |
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* |--------------------------------------------------------------------|
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* | packet_type_enable_flags_2 |
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* |--------------------------------------------------------------------|
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* | packet_type_enable_flags_3 |
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* |--------------------------------------------------------------------|
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* | tlv_filter_in_flags |
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* |-----------------------------------+--------------------------------|
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* | rx_header_offset | rx_packet_offset |
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* |-----------------------------------+--------------------------------|
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* | rx_mpdu_start_offset | rx_mpdu_end_offset |
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* |-----------------------------------+--------------------------------|
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* | rx_msdu_start_offset | rx_msdu_end_offset |
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* |-----------------------------------+--------------------------------|
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* | rsvd3 | rx_attention_offset |
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* |--------------------------------------------------------------------|
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* | rsvd4 | mo| fp| rx_drop_threshold |
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* | |ndp|ndp| |
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* |--------------------------------------------------------------------|
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* Where:
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* PS = pkt_swap
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* SS = status_swap
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* OV = rx_offsets_valid
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* DT = drop_thresh_valid
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* CLM = config_length_mgmt
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* CLC = config_length_ctrl
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* CLD = config_length_data
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* RXHDL = rx_hdr_len
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* RX = rxpcu_filter_enable_flag
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* The message is interpreted as follows:
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* dword0 - b'0:7 - msg_type: This will be set to
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* 0xc (HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG)
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@ -5616,7 +5627,15 @@ enum htt_srng_ring_id {
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* 10 - 128bytes
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* 11 - 256bytes
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* default - 128 bytes
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* b'27:31 - rsvd2: Reserved for future use
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* b'27 - rxpcu_filter_enable_flag
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* For Scan Radio Host CPU utilization is very high.
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* In order to reduce CPU utilization we need to filter out
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* certain configured MAC frames.
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* To filter out configured MAC address frames, RxPCU should
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* be zero which means allow all frames for MD at RxOLE
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* host wil fiter out frames.
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* RxPCU (Filter IN) -> RxOLE (Filter In/Filter Out)
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* b'28:31 - rsvd2: Reserved for future use
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* dword2 - b'0:31 - packet_type_enable_flags_0:
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* Enable MGMT packet from 0b0000 to 0b1001
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* bits from low to high: FP, MD, MO - 3 bits
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@ -5755,7 +5774,8 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
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config_length_ctrl:3,
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config_length_data:3,
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rx_hdr_len: 2,
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rsvd2: 5;
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rxpcu_filter_enable_flag:1,
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rsvd2: 4;
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A_UINT32 packet_type_enable_flags_0;
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A_UINT32 packet_type_enable_flags_1;
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A_UINT32 packet_type_enable_flags_2;
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@ -5929,6 +5949,17 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S));\
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} while(0)
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#define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M 0x08000000
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#define HTT_RX_RING_SELECTION_CFG_RXPXU_FILTER_S 27
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#define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M) >> \
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HTT_RX_RING_SELECTION_CFG_RXPXU_FILTER_S)
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#define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXPXU_FILTER_S));\
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} while(0)
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_M 0xffffffff
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_S 0
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#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG_0_GET(_var) \
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@ -6961,6 +6992,13 @@ PREPACK struct htt_tx_monitor_cfg_t {
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dma_mpdu_ctrl: 1,
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dma_mpdu_data: 1,
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rsvd4: 10;
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A_UINT32 tx_queue_ext_v2_word_mask: 12,
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tx_peer_entry_v2_word_mask: 12,
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rsvd5: 10;
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A_UINT32 fes_status_end_word_mask: 16,
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response_end_status_word_mask: 16;
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A_UINT32 fes_status_prot_word_mask: 11,
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rsvd6: 21;
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} POSTPACK;
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#define HTT_TX_MONITOR_CFG_SZ (sizeof(struct htt_tx_monitor_cfg_t))
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@ -7339,6 +7377,61 @@ PREPACK struct htt_tx_monitor_cfg_t {
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_DMA_MPDU_DATA_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M 0x00000fff
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#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S 0
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#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_M) >> \
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HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S)
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#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_V2_WORD_MASK_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M 0x00fff000
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#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S 12
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#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_M) >> \
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HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S)
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#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_V2_WORD_MASK_S)); \
|
||||
} while (0)
|
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|
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#define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M 0x0000ffff
|
||||
#define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S 0
|
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#define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_M) >> \
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HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S)
|
||||
#define HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK, _val); \
|
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_END_WORD_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M 0xffff0000
|
||||
#define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S 16
|
||||
#define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_GET(_var) \
|
||||
(((_var) & HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_M) >> \
|
||||
HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S)
|
||||
#define HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK, _val); \
|
||||
((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RESPONSE_END_STATUS_WORD_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M 0x000007ff
|
||||
#define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S 0
|
||||
#define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_GET(_var) \
|
||||
(((_var) & HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_M) >> \
|
||||
HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)
|
||||
#define HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_SET(_var, _val) \
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||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK, _val); \
|
||||
((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* pkt_type_enable_flags
|
||||
*/
|
||||
|
|
@ -8251,7 +8344,7 @@ enum htt_ip_da_sa_prefix {
|
|||
* b'9 - DISABLE_TA_CHECK: 1- Disable TA check for MPDU Sequence
|
||||
* num jump
|
||||
* b'10 - DISABLE_QOS_CHECK: 1- Disable checking if qos/nonqos
|
||||
* data type switch has happend for MPDU Sequence num jump
|
||||
* data type switch has happened for MPDU Sequence num jump
|
||||
* b'11 - DISABLE_RAW_CHECK: 1- Disable checking for raw packet type
|
||||
* for MPDU Sequence num jump
|
||||
* b'12 - DISABLE_DECRYPT_ERR_CHECK: 1- Disable fisa cache commands
|
||||
|
|
@ -12046,7 +12139,7 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
|
|||
* In certain generations of chips, the peer map message also contains
|
||||
* a HW peer ID. This HW peer ID is used during rx --> tx frame forwarding
|
||||
* to identify which peer the frame needs to be forwarded to (i.e. the
|
||||
* peer assocated with the Destination MAC Address within the packet),
|
||||
* peer associated with the Destination MAC Address within the packet),
|
||||
* and particularly which vdev needs to transmit the frame (for cases
|
||||
* of inter-vdev rx --> tx forwarding). The HW peer id here is the same
|
||||
* meaning as AST_INDEX_0.
|
||||
|
|
@ -12189,7 +12282,7 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
|
|||
*
|
||||
* The peer map v2 message also contains a HW peer ID. This HW peer ID
|
||||
* is used during rx --> tx frame forwarding to identify which peer the
|
||||
* frame needs to be forwarded to (i.e. the peer assocated with the
|
||||
* frame needs to be forwarded to (i.e. the peer associated with the
|
||||
* Destination MAC Address within the packet), and particularly which vdev
|
||||
* needs to transmit the frame (for cases of inter-vdev rx --> tx forwarding).
|
||||
* This DA-based peer ID that is provided for certain rx frames
|
||||
|
|
@ -13825,7 +13918,7 @@ PREPACK struct htt_txq_group {
|
|||
* Purpose: Indicate whether data ACK RSSI is appended for each MSDU in
|
||||
* TX_COMP_IND message. The order of the per-MSDU ACK RSSI report
|
||||
* matches the order of the MSDU IDs. Although the ACK RSSI is the
|
||||
* same for all MSDUs witin a single PPDU, the RSSI is duplicated
|
||||
* same for all MSDUs within a single PPDU, the RSSI is duplicated
|
||||
* for each MSDU, for convenience.
|
||||
* The ACK RSSI values are valid when status is COMPLETE_OK (and
|
||||
* this append2 bit is set).
|
||||
|
|
@ -14460,7 +14553,7 @@ typedef struct {
|
|||
* Purpose: indicate how many 32-bit integers follow the message header
|
||||
* - NUM_CHARS
|
||||
* Bits 31:16
|
||||
* Purpose: indicate how many 8-bit charaters follow the series of integers
|
||||
* Purpose: indicate how many 8-bit characters follow the series of integers
|
||||
*/
|
||||
#define HTT_RX_TEST_NUM_INTS_M 0xff00
|
||||
#define HTT_RX_TEST_NUM_INTS_S 8
|
||||
|
|
@ -14663,7 +14756,7 @@ struct rx_reorder_stats {
|
|||
A_UINT32 rxdesc_bmc_msdus_inv_peer;
|
||||
/* Number of MSDUs dropped due to no first MSDU flag */
|
||||
A_UINT32 rxdesc_no_1st_msdu;
|
||||
/* Number of MSDUs droped due to ring overflow */
|
||||
/* Number of MSDUs dropped due to ring overflow */
|
||||
A_UINT32 msdu_drop_ring_ov;
|
||||
/* Number of MSDUs dropped due to FC mismatch */
|
||||
A_UINT32 msdu_drop_fc_mismatch;
|
||||
|
|
@ -16612,7 +16705,7 @@ typedef enum {
|
|||
*
|
||||
* b'0:15 - flow pool ID: Existing flow pool ID
|
||||
*
|
||||
* b'16:31 - flow pool new size: new pool size for exisiting flow pool ID
|
||||
* b'16:31 - flow pool new size: new pool size for existing flow pool ID
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
@ -17241,7 +17334,7 @@ PREPACK struct htt_cfr_dump_compl_ind {
|
|||
* subsequent period (100 ms) as long as the backpressure remains unabated.
|
||||
* This message indicates the ring id along with current head and tail index
|
||||
* locations (i.e. write and read indices).
|
||||
* The backpressure time indicates the time in ms for which continous
|
||||
* The backpressure time indicates the time in ms for which continuous
|
||||
* backpressure has been observed in the ring.
|
||||
*
|
||||
* The message format is as follows:
|
||||
|
|
@ -17260,11 +17353,12 @@ PREPACK struct htt_cfr_dump_compl_ind {
|
|||
* (HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND)
|
||||
* b'8:15 - pdev_id: 0 indicates msg is for UMAC ring.
|
||||
* 1, 2, 3 indicates pdev_id 0,1,2 and
|
||||
the msg is for LMAC ring.
|
||||
* the msg is for LMAC ring.
|
||||
* b'16:23 - ring_type: Refer to enum htt_backpressure_ring_type.
|
||||
* b'24:31 - ring_id: Refer enum htt_backpressure_umac_ring_id/
|
||||
* htt_backpressure_lmac_ring_id. This represents
|
||||
* the ring id for which continous backpressure is seen
|
||||
* the ring id for which continuous backpressure
|
||||
* is seen
|
||||
*
|
||||
* dword1 - b'0:15 - head_idx: This indicates the current head index of
|
||||
* the ring indicated by the ring_id
|
||||
|
|
@ -17272,7 +17366,7 @@ PREPACK struct htt_cfr_dump_compl_ind {
|
|||
* dword1 - b'16:31 - tail_idx: This indicates the current tail index of
|
||||
* the ring indicated by the ring id
|
||||
*
|
||||
* dword2 - b'0:31 - backpressure_time_ms: Indicates how long continous
|
||||
* dword2 - b'0:31 - backpressure_time_ms: Indicates how long continuous
|
||||
* backpressure has been seen in the ring
|
||||
* indicated by the ring_id.
|
||||
* Units = milliseconds
|
||||
|
|
@ -17780,7 +17874,7 @@ enum HTT_UL_OFDMA_TRIG_TYPE {
|
|||
* Bits 31:16
|
||||
* Purpose: indicates the secondary channel center frequency,
|
||||
* only for 11acvht 80plus80 mode
|
||||
* Value: secondary channel center frequeny, in MHz units, if applicable
|
||||
* Value: secondary channel center frequency, in MHz units, if applicable
|
||||
*
|
||||
* checksum field
|
||||
* - CHECK_SUM
|
||||
|
|
@ -18132,16 +18226,16 @@ PREPACK struct htt_rx_peer_metadata_v0 {
|
|||
*
|
||||
* The following diagram shows the format of the RX PEER METADATA V1 format.
|
||||
*
|
||||
* |31 29|28 26|25 24|23 16|15 14| 13 |12 0|
|
||||
* |-----------------------------------------------------------------------|
|
||||
* |Rsvd2|CHIP ID|LMAC ID| VDEV ID |Rsvd1|ML PEER| SW PEER ID/ML PEER ID|
|
||||
* |-----------------------------------------------------------------------|
|
||||
* |31 29|28 26|25 24|23 16|15 14| 13 |12 0|
|
||||
* |---------------------------------------------------------------------------|
|
||||
* |Rsvd2|CHIP ID|LMAC ID|VDEV ID|logical_link_id|ML PEER|SW PEER ID/ML PEER ID|
|
||||
* |---------------------------------------------------------------------------|
|
||||
*/
|
||||
PREPACK struct htt_rx_peer_metadata_v1 {
|
||||
A_UINT32
|
||||
peer_id: 13,
|
||||
ml_peer_valid: 1,
|
||||
reserved1: 2,
|
||||
logical_link_id: 2,
|
||||
vdev_id: 8,
|
||||
lmac_id: 2,
|
||||
chip_id: 3,
|
||||
|
|
@ -18175,6 +18269,17 @@ PREPACK struct htt_rx_peer_metadata_v1 {
|
|||
#define HTT_RX_PEER_META_DATA_V1_VDEV_ID_GET(_var) \
|
||||
(((_var) & HTT_RX_PEER_META_DATA_V1_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1_VDEV_ID_S)
|
||||
|
||||
#define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S 14
|
||||
#define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M 0x0000c000
|
||||
#define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_GET(_var) \
|
||||
(((_var) & HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S)
|
||||
|
||||
#define HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID, _val); \
|
||||
((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_LOGICAL_LINK_ID_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_RX_PEER_META_DATA_V1_VDEV_ID_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1_VDEV_ID, _val); \
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2012-2016, 2020 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
|
|
@ -62,7 +63,7 @@ enum htt_rx_ind_mpdu_status {
|
|||
HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
|
||||
HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, /* only accept EAPOL frames */
|
||||
HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
|
||||
HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscous mode */
|
||||
HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscuous mode */
|
||||
HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
|
||||
HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
|
||||
HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2012-2014 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
|
|
@ -237,7 +238,7 @@ enum {
|
|||
* - RMF_ENABLED (R)
|
||||
* Bit 6
|
||||
* Purpose: specify whether the peer in question has enable robust
|
||||
* management frames, to encrypt certain managment frames
|
||||
* management frames, to encrypt certain management frames
|
||||
* Value: HTT_ISOC_RMF enum
|
||||
* Value: HTT_ISOC_NON_QOS or HTT_ISOC_QOS
|
||||
* - VDEV_ID
|
||||
|
|
|
|||
|
|
@ -2732,7 +2732,7 @@ typedef struct {
|
|||
* The size of the actual mgmt payload (in bytes) can be obtained from
|
||||
* the frame_length field.
|
||||
* The size of entire payload including the padding for alignment
|
||||
* (in bytes) can be derived from the length in tlv parametes,
|
||||
* (in bytes) can be derived from the length in tlv parameters,
|
||||
* minus the 12 bytes of the above fields.
|
||||
*/
|
||||
A_UINT32 payload[1];
|
||||
|
|
@ -2774,7 +2774,7 @@ typedef struct {
|
|||
* The size of the actual mgmt payload (in bytes) can be obtained from
|
||||
* the frame_length field.
|
||||
* The size of entire payload including the padding for alignment
|
||||
* (in bytes) can be derived from the length in tlv parametes,
|
||||
* (in bytes) can be derived from the length in tlv parameters,
|
||||
* minus the 12 bytes of the above fields.
|
||||
*/
|
||||
A_UINT32 payload[1];
|
||||
|
|
|
|||
120
fw/htt_stats.h
120
fw/htt_stats.h
|
|
@ -901,7 +901,8 @@ typedef struct {
|
|||
/** Num of times su bf sequences are denylisted */
|
||||
A_UINT32 num_su_txbf_denylisted;
|
||||
/** pdev uptime in microseconds **/
|
||||
A_UINT32 pdev_up_time_us;
|
||||
A_UINT32 pdev_up_time_us_low;
|
||||
A_UINT32 pdev_up_time_us_high;
|
||||
} htt_tx_pdev_stats_cmn_tlv;
|
||||
|
||||
#define HTT_TX_PDEV_STATS_URRN_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
|
||||
|
|
@ -946,6 +947,18 @@ typedef struct {
|
|||
A_UINT32 cw_max[HTT_NUM_AC_WMM][HTT_STATS_MUEDCA_VALUE_MAX];
|
||||
} htt_tx_pdev_muedca_params_stats_tlv_v;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
A_UINT32 ul_mumimo_less_aggressive[HTT_NUM_AC_WMM];
|
||||
A_UINT32 ul_mumimo_medium_aggressive[HTT_NUM_AC_WMM];
|
||||
A_UINT32 ul_mumimo_highly_aggressive[HTT_NUM_AC_WMM];
|
||||
A_UINT32 ul_mumimo_default_relaxed[HTT_NUM_AC_WMM];
|
||||
A_UINT32 ul_muofdma_less_aggressive[HTT_NUM_AC_WMM];
|
||||
A_UINT32 ul_muofdma_medium_aggressive[HTT_NUM_AC_WMM];
|
||||
A_UINT32 ul_muofdma_highly_aggressive[HTT_NUM_AC_WMM];
|
||||
A_UINT32 ul_muofdma_default_relaxed[HTT_NUM_AC_WMM];
|
||||
} htt_tx_pdev_ap_edca_params_stats_tlv_v;
|
||||
|
||||
#define HTT_TX_PDEV_SIFS_BURST_HIST_STATS 10
|
||||
#define HTT_TX_PDEV_STATS_SIFS_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
|
||||
/* NOTE: Variable length TLV, use length spec to infer array size */
|
||||
|
|
@ -1589,7 +1602,11 @@ typedef struct {
|
|||
intra_bss : 1,
|
||||
chip_id : 2,
|
||||
ml_peer_id : 13,
|
||||
reserved : 1;
|
||||
on_chip : 1;
|
||||
A_UINT32
|
||||
tx_monitor_override_sta : 1,
|
||||
rx_monitor_override_sta : 1,
|
||||
reserved1 : 30;
|
||||
} htt_ast_entry_tlv;
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -1941,7 +1958,7 @@ typedef struct {
|
|||
A_UINT32 mu_mimo_mpdus_failed_usr;
|
||||
/** 11AC DL MU MIMO number of mpdus re-queued to HW, per user */
|
||||
A_UINT32 mu_mimo_mpdus_requeued_usr;
|
||||
/** 11AC DL MU MIMO BA not receieved, per user */
|
||||
/** 11AC DL MU MIMO BA not received, per user */
|
||||
A_UINT32 mu_mimo_err_no_ba_usr;
|
||||
/** 11AC DL MU MIMO mpdu underrun encountered, per user */
|
||||
A_UINT32 mu_mimo_mpdu_underrun_usr;
|
||||
|
|
@ -2084,7 +2101,7 @@ typedef struct {
|
|||
A_UINT32 mpdu_ack_fail_cnt;
|
||||
/** This will include sched cmd flush and time based discard */
|
||||
A_UINT32 mpdu_filt_cnt;
|
||||
/** Number of MPDUs for which ACK was sucessful but no Tx happened */
|
||||
/** Number of MPDUs for which ACK was successful but no Tx happened */
|
||||
A_UINT32 false_mpdu_ack_count;
|
||||
|
||||
/** Number of times txq timeout happened */
|
||||
|
|
@ -2156,7 +2173,7 @@ typedef struct {
|
|||
* completing the burst, we identify the txop used in the burst and
|
||||
* incr the corresponding bin.
|
||||
* Each bin represents 1ms & we have 10 bins in this histogram.
|
||||
* they are deined in FW using the following macros
|
||||
* they are defined in FW using the following macros
|
||||
* #define WAL_MAX_TXOP_USED_CNT_HISTOGRAM 10
|
||||
* #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms )
|
||||
*
|
||||
|
|
@ -2659,6 +2676,18 @@ typedef struct {
|
|||
htt_txbf_ofdma_ax_steer_stats_elem_t ax_steer[1]; /* variable length */
|
||||
} htt_txbf_ofdma_ax_steer_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
/* 11AX HE OFDMA MPDUs tried in rbo steering */
|
||||
A_UINT32 ax_ofdma_rbo_steer_mpdus_tried;
|
||||
/* 11AX HE OFDMA MPDUs failed in rbo steering */
|
||||
A_UINT32 ax_ofdma_rbo_steer_mpdus_failed;
|
||||
/* 11AX HE OFDMA MPDUs tried in sifs steering */
|
||||
A_UINT32 ax_ofdma_sifs_steer_mpdus_tried;
|
||||
/* 11AX HE OFDMA MPDUs failed in sifs steering */
|
||||
A_UINT32 ax_ofdma_sifs_steer_mpdus_failed;
|
||||
} htt_txbf_ofdma_ax_steer_mpdu_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
/** 11BE EHT OFDMA NDPA frame queued to the HW */
|
||||
A_UINT32 be_ofdma_ndpa_queued;
|
||||
|
|
@ -2793,16 +2822,30 @@ typedef struct {
|
|||
htt_txbf_ofdma_be_steer_stats_elem_t be_steer[1]; /* variable length */
|
||||
} htt_txbf_ofdma_be_steer_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
/* 11BE EHT OFDMA MPDUs tried in rbo steering */
|
||||
A_UINT32 be_ofdma_rbo_steer_mpdus_tried;
|
||||
/* 11BE EHT OFDMA MPDUs failed in rbo steering */
|
||||
A_UINT32 be_ofdma_rbo_steer_mpdus_failed;
|
||||
/* 11BE EHT OFDMA MPDUs tried in sifs steering */
|
||||
A_UINT32 be_ofdma_sifs_steer_mpdus_tried;
|
||||
/* 11BE EHT OFDMA MPDUs failed in sifs steering */
|
||||
A_UINT32 be_ofdma_sifs_steer_mpdus_failed;
|
||||
} htt_txbf_ofdma_be_steer_mpdu_stats_tlv;
|
||||
|
||||
/* STATS_TYPE : HTT_DBG_EXT_STATS_TXBF_OFDMA
|
||||
* TLV_TAGS:
|
||||
* - HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG
|
||||
* - HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG
|
||||
* - HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG
|
||||
* - HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG
|
||||
* - HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG
|
||||
* - HTT_STATS_TXBF_OFDMA_BE_NDPA_STATS_TAG
|
||||
* - HTT_STATS_TXBF_OFDMA_BE_NDP_STATS_TAG
|
||||
* - HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG
|
||||
* - HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG
|
||||
* - HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -3297,7 +3340,7 @@ typedef struct {
|
|||
A_UINT32 mu_mimo_mpdus_failed_usr;
|
||||
/** 11AC DL MU MIMO number of mpdus re-queued to HW, per user */
|
||||
A_UINT32 mu_mimo_mpdus_requeued_usr;
|
||||
/** 11AC DL MU MIMO BA not receieved, per user */
|
||||
/** 11AC DL MU MIMO BA not received, per user */
|
||||
A_UINT32 mu_mimo_err_no_ba_usr;
|
||||
/** 11AC DL MU MIMO mpdu underrun encountered, per user */
|
||||
A_UINT32 mu_mimo_mpdu_underrun_usr;
|
||||
|
|
@ -3312,7 +3355,7 @@ typedef struct {
|
|||
A_UINT32 ax_mu_mimo_mpdus_failed_usr;
|
||||
/** 11AX DL MU MIMO number of mpdus re-queued to HW, per user */
|
||||
A_UINT32 ax_mu_mimo_mpdus_requeued_usr;
|
||||
/** 11AX DL MU MIMO BA not receieved, per user */
|
||||
/** 11AX DL MU MIMO BA not received, per user */
|
||||
A_UINT32 ax_mu_mimo_err_no_ba_usr;
|
||||
/** 11AX DL MU MIMO mpdu underrun encountered, per user */
|
||||
A_UINT32 ax_mu_mimo_mpdu_underrun_usr;
|
||||
|
|
@ -3327,7 +3370,7 @@ typedef struct {
|
|||
A_UINT32 ax_ofdma_mpdus_failed_usr;
|
||||
/** 11AX MU OFDMA number of mpdus re-queued to HW, per user */
|
||||
A_UINT32 ax_ofdma_mpdus_requeued_usr;
|
||||
/** 11AX MU OFDMA BA not receieved, per user */
|
||||
/** 11AX MU OFDMA BA not received, per user */
|
||||
A_UINT32 ax_ofdma_err_no_ba_usr;
|
||||
/** 11AX MU OFDMA mpdu underrun encountered, per user */
|
||||
A_UINT32 ax_ofdma_mpdu_underrun_usr;
|
||||
|
|
@ -3459,7 +3502,7 @@ typedef enum {
|
|||
HTT_SCHED_TID_SKIP_UL_TWT_PAUSED, /* Skip ul tid if twt txq is paused */
|
||||
HTT_SCHED_TID_SKIP_PEER_UL_RX_NOT_ACTIVE, /* Skip ul tid if peer ul rx is not active */
|
||||
HTT_SCHED_TID_SKIP_NO_FORCE_TRIGGER, /* Skip ul tid if there is no force triggers */
|
||||
HTT_SCHED_TID_SKIP_SMART_BASIC_TRIGGER, /* Skip ul tid if smart basic trigger doesnot have enough data */
|
||||
HTT_SCHED_TID_SKIP_SMART_BASIC_TRIGGER, /* Skip ul tid if smart basic trigger doesn't have enough data */
|
||||
|
||||
|
||||
HTT_SCHED_INELIGIBILITY_MAX,
|
||||
|
|
@ -3481,7 +3524,7 @@ typedef struct {
|
|||
} htt_sched_txq_sched_ineligibility_tlv_v;
|
||||
|
||||
typedef enum {
|
||||
HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, /* Supercycle not triggerd */
|
||||
HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, /* Supercycle not triggered */
|
||||
HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED, /* forced supercycle trigger */
|
||||
HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES, /* Num tidq entries is less than max_client threshold */
|
||||
HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS, /* Num active tids is less than max_client threshold */
|
||||
|
|
@ -4944,8 +4987,12 @@ typedef struct {
|
|||
htt_tlv_hdr_t tlv_hdr;
|
||||
/** Tx PPDU duration histogram **/
|
||||
A_UINT32 tx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS];
|
||||
A_UINT32 tx_success_time_us;
|
||||
A_UINT32 tx_fail_time_us;
|
||||
A_UINT32 tx_success_time_us_low;
|
||||
A_UINT32 tx_success_time_us_high;
|
||||
A_UINT32 tx_fail_time_us_low;
|
||||
A_UINT32 tx_fail_time_us_high;
|
||||
A_UINT32 pdev_up_time_us_low;
|
||||
A_UINT32 pdev_up_time_us_high;
|
||||
} htt_tx_pdev_ppdu_dur_stats_tlv;
|
||||
|
||||
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE
|
||||
|
|
@ -6271,7 +6318,7 @@ typedef enum {
|
|||
HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3,
|
||||
/* Multi user random back off steer stats */
|
||||
HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS = 4,
|
||||
/* For backward compatability new modes cannot be added */
|
||||
/* For backward compatibility new modes cannot be added */
|
||||
HTT_TXBF_MAX_NUM_OF_MODES = 5
|
||||
} htt_txbf_sound_steer_modes;
|
||||
|
||||
|
|
@ -6443,7 +6490,7 @@ typedef struct {
|
|||
* opportunities created. Incoming OBSS frame RSSI is compared with per
|
||||
* PPDU non-SRG RSSI threshold configured in each PPDU. If incoming OBSS
|
||||
* RSSI < non-SRG RSSI threshold configured in each PPDU, then non-SRG
|
||||
* tranmission happens.
|
||||
* transmission happens.
|
||||
*/
|
||||
A_UINT32 num_non_srg_ppdu_tried;
|
||||
/**
|
||||
|
|
@ -6464,7 +6511,7 @@ typedef struct {
|
|||
* Incoming OBSS frame RSSI is compared with per PPDU SRG RSSI
|
||||
* threshold configured in each PPDU.
|
||||
* If incoming OBSS RSSI < SRG RSSI threshold configured in each PPDU,
|
||||
* then SRG tranmission happens.
|
||||
* then SRG transmission happens.
|
||||
*/
|
||||
A_UINT32 num_srg_ppdu_tried;
|
||||
/**
|
||||
|
|
@ -6542,15 +6589,15 @@ typedef struct {
|
|||
* histogram showing how many times different degrees of backpressure
|
||||
* duration occurred:
|
||||
* Index 0 indicates the number of times ring was
|
||||
* continously in backpressure state for 100 - 200ms.
|
||||
* continuously in backpressure state for 100 - 200ms.
|
||||
* Index 1 indicates the number of times ring was
|
||||
* continously in backpressure state for 200 - 300ms.
|
||||
* continuously in backpressure state for 200 - 300ms.
|
||||
* Index 2 indicates the number of times ring was
|
||||
* continously in backpressure state for 300 - 400ms.
|
||||
* continuously in backpressure state for 300 - 400ms.
|
||||
* Index 3 indicates the number of times ring was
|
||||
* continously in backpressure state for 400 - 500ms.
|
||||
* continuously in backpressure state for 400 - 500ms.
|
||||
* Index 4 indicates the number of times ring was
|
||||
* continously in backpressure state beyond 500ms.
|
||||
* continuously in backpressure state beyond 500ms.
|
||||
*/
|
||||
A_UINT32 backpressure_hist[5];
|
||||
} htt_ring_backpressure_stats_tlv;
|
||||
|
|
@ -6815,6 +6862,15 @@ typedef struct {
|
|||
A_UINT32 reduced_tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
|
||||
/** Open loop TX BW stats */
|
||||
A_UINT32 reduced_tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
|
||||
/** Txbf flag reason stats */
|
||||
A_UINT32 txbf_flag_set_mu_mode;
|
||||
A_UINT32 txbf_flag_set_final_status;
|
||||
A_UINT32 txbf_flag_not_set_verified_txbf_mode;
|
||||
A_UINT32 txbf_flag_not_set_disable_p2p_access;
|
||||
A_UINT32 txbf_flag_not_set_max_nss_reached_in_he160;
|
||||
A_UINT32 txbf_flag_not_set_disable_ul_dl_ofdma;
|
||||
A_UINT32 txbf_flag_not_set_mcs_threshold_value;
|
||||
A_UINT32 txbf_flag_not_set_final_status;
|
||||
} htt_tx_pdev_txbf_rate_stats_tlv;
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -7271,27 +7327,27 @@ typedef enum {
|
|||
|
||||
typedef enum {
|
||||
HTT_STATS_RESET_CAUSE_FIRST_RESET = 0x00000001, /* First reset by application */
|
||||
HTT_STATS_RESET_CAUSE_ERROR = 0x00000002, /* Trigered due to error */
|
||||
HTT_STATS_RESET_CAUSE_ERROR = 0x00000002, /* Triggered due to error */
|
||||
HTT_STATS_RESET_CAUSE_DEEP_SLEEP = 0x00000004, /* Reset after deep sleep */
|
||||
HTT_STATS_RESET_CAUSE_FULL_RESET = 0x00000008, /* Full reset without any optimizations */
|
||||
HTT_STATS_RESET_CAUSE_CHANNEL_CHANGE = 0x00000010, /* For normal channel change */
|
||||
HTT_STATS_RESET_CAUSE_BAND_CHANGE = 0x00000020, /* Trigered due to band change */
|
||||
HTT_STATS_RESET_CAUSE_DO_CAL = 0x00000040, /* Trigered due to calibrations */
|
||||
HTT_STATS_RESET_CAUSE_BAND_CHANGE = 0x00000020, /* Triggered due to band change */
|
||||
HTT_STATS_RESET_CAUSE_DO_CAL = 0x00000040, /* Triggered due to calibrations */
|
||||
HTT_STATS_RESET_CAUSE_MCI_ERROR = 0x00000080, /* Triggered due to MCI ERROR */
|
||||
HTT_STATS_RESET_CAUSE_CHWIDTH_CHANGE = 0x00000100, /* Trigered due to channel width change */
|
||||
HTT_STATS_RESET_CAUSE_WARM_RESTORE_CAL = 0x00000200, /* Trigered due to warm reset we want to just restore calibrations */
|
||||
HTT_STATS_RESET_CAUSE_COLD_RESTORE_CAL = 0x00000400, /* Trigered due to cold reset we want to just restore calibrations */
|
||||
HTT_STATS_RESET_CAUSE_PHY_WARM_RESET = 0x00000800, /* Trigered due to phy warm reset we want to just restore calibrations */
|
||||
HTT_STATS_RESET_CAUSE_M3_SSR = 0x00001000, /* Trigered due to SSR Restart */
|
||||
HTT_STATS_RESET_CAUSE_CHWIDTH_CHANGE = 0x00000100, /* Triggered due to channel width change */
|
||||
HTT_STATS_RESET_CAUSE_WARM_RESTORE_CAL = 0x00000200, /* Triggered due to warm reset we want to just restore calibrations */
|
||||
HTT_STATS_RESET_CAUSE_COLD_RESTORE_CAL = 0x00000400, /* Triggered due to cold reset we want to just restore calibrations */
|
||||
HTT_STATS_RESET_CAUSE_PHY_WARM_RESET = 0x00000800, /* Triggered due to phy warm reset we want to just restore calibrations */
|
||||
HTT_STATS_RESET_CAUSE_M3_SSR = 0x00001000, /* Triggered due to SSR Restart */
|
||||
HTT_STATS_RESET_CAUSE_FORCE_CAL = 0x00002000, /* Reset to force the calibration */
|
||||
/* 0x00004000, 0x00008000 reserved */
|
||||
HTT_STATS_NO_RESET_CHANNEL_CHANGE = 0x00010000, /* No reset, normal channel change */
|
||||
HTT_STATS_NO_RESET_BAND_CHANGE = 0x00020000, /* No reset, channel change across band */
|
||||
HTT_STATS_NO_RESET_CHWIDTH_CHANGE = 0x00040000, /* No reset, channel change across channel width */
|
||||
HTT_STATS_NO_RESET_CHAINMASK_CHANGE = 0x00080000, /* No reset, chainmask change */
|
||||
HTT_STATS_RESET_CAUSE_PHY_WARM_RESET_UCODE_TRIG = 0x00100000, /* Trigered due to phy warm reset we want to just restore calibrations */
|
||||
HTT_STATS_RESET_CAUSE_PHY_WARM_RESET_UCODE_TRIG = 0x00100000, /* Triggered due to phy warm reset we want to just restore calibrations */
|
||||
HTT_STATS_RESET_CAUSE_PHY_OFF_TIMEOUT_RESET = 0x00200000, /* Reset ucode because phy off ack timeout*/
|
||||
HTT_STATS_RESET_CAUSE_LMAC_RESET_UMAC_NOC_ERR = 0x00400000, /* LMAC reset trigered due to NOC Address/Slave error originating at LMAC */
|
||||
HTT_STATS_RESET_CAUSE_LMAC_RESET_UMAC_NOC_ERR = 0x00400000, /* LMAC reset triggered due to NOC Address/Slave error originating at LMAC */
|
||||
HTT_STATS_NO_RESET_SCAN_BACK_TO_SAME_HOME_CHANNEL_CHANGE = 0x00800000, /* No reset, scan to home channel change */
|
||||
} HTT_STATS_RESET_CAUSE;
|
||||
|
||||
|
|
@ -7343,7 +7399,7 @@ typedef struct {
|
|||
A_UINT32 phytx_abort_cnt;
|
||||
/** number of times rx abort initiated by phy */
|
||||
A_UINT32 phyrx_abort_cnt;
|
||||
/** number of rx defered count initiated by phy */
|
||||
/** number of rx deferred count initiated by phy */
|
||||
A_UINT32 phyrx_defer_abort_cnt;
|
||||
/** number of sizing events generated at LSTF */
|
||||
A_UINT32 rx_gain_adj_lstf_event_cnt; /* a.k.a sizing1 */
|
||||
|
|
@ -8285,7 +8341,7 @@ typedef struct _htt_ml_peer_stats {
|
|||
} htt_ml_peer_stats_t;
|
||||
|
||||
/*
|
||||
* ODD Mandatory Stats are grouped together from all the exisitng different
|
||||
* ODD Mandatory Stats are grouped together from all the existing different
|
||||
* stats, to form a set of stats that will be used by the ODD application to
|
||||
* post the stats to the cloud instead of polling for the individual stats.
|
||||
* This is done to avoid non-mandatory stats to be polled as the data will not
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2017 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
|
|
@ -408,7 +409,7 @@ A_COMPILE_TIME_ASSERT(verify_Pkt_pool_sz,
|
|||
* Purpose: Specify length Ethernet Packet
|
||||
* - VDEV_ID
|
||||
* Bits 23:16
|
||||
* Purpose: Specify the VDEV ID corrsponding the the packet
|
||||
* Purpose: Specify the VDEV ID corresponding to the packet
|
||||
*/
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@
|
|||
*/
|
||||
#define MAX_SPATIAL_STREAM_ANY MAX_SPATIAL_STREAM_ANY_V2 /* DEPRECATED */
|
||||
|
||||
/* defines to set Packet extension values whic can be 0 us, 8 usec or 16 usec */
|
||||
/* defines to set Packet extension values which can be 0, 8, or 16 usec */
|
||||
/* NOTE: Below values cannot be changed without breaking WMI Compatibility */
|
||||
#define MAX_HE_NSS 8
|
||||
#define MAX_HE_MODULATION 8
|
||||
|
|
@ -477,8 +477,8 @@ typedef struct {
|
|||
|
||||
/*
|
||||
* Used to update rate-control logic with the status of the tx-completion.
|
||||
* In host-based implementation of the rate-control feature, this struture is used to
|
||||
* create the payload for HTT message/s from target to host.
|
||||
* In host-based implementation of the rate-control feature, this structure
|
||||
* is used to create the payload for HTT message/s from target to host.
|
||||
*/
|
||||
#ifndef CONFIG_MOVE_RC_STRUCT_TO_MACCORE
|
||||
#if (NUM_SPATIAL_STREAM > 3)
|
||||
|
|
@ -680,7 +680,7 @@ typedef struct {
|
|||
#endif
|
||||
|
||||
/**
|
||||
* strucutre describing host memory chunk.
|
||||
* structure describing host memory chunk.
|
||||
*/
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wlan_host_memory_chunk */
|
||||
|
|
@ -809,9 +809,9 @@ struct wlan_dbg_tx_stats_v1 {
|
|||
A_UINT32 sw_retry_failure;
|
||||
/* illegal rate phy errors */
|
||||
A_UINT32 illgl_rate_phy_err;
|
||||
/* wal pdev continous xretry */
|
||||
/* wal pdev continuous xretry */
|
||||
A_UINT32 pdev_cont_xretry;
|
||||
/* wal pdev continous xretry */
|
||||
/* wal pdev continuous xretry */
|
||||
A_UINT32 pdev_tx_timeout;
|
||||
/* wal pdev resets */
|
||||
A_UINT32 pdev_resets;
|
||||
|
|
@ -861,9 +861,9 @@ struct wlan_dbg_tx_stats_v2 {
|
|||
A_UINT32 sw_retry_failure;
|
||||
/* illegal rate phy errors */
|
||||
A_UINT32 illgl_rate_phy_err;
|
||||
/* wal pdev continous xretry */
|
||||
/* wal pdev continuous xretry */
|
||||
A_UINT32 pdev_cont_xretry;
|
||||
/* wal pdev continous xretry */
|
||||
/* wal pdev continuous xretry */
|
||||
A_UINT32 pdev_tx_timeout;
|
||||
/* wal pdev resets */
|
||||
A_UINT32 pdev_resets;
|
||||
|
|
@ -1733,7 +1733,7 @@ typedef struct {
|
|||
*/
|
||||
A_UINT32 link_info;
|
||||
/* This TLV is followed by array of mlo_glb_link:
|
||||
* mlo_glb_link will have mutiple instances equal to num of hw links
|
||||
* mlo_glb_link will have multiple instances equal to num of hw links
|
||||
* received by no_of_link
|
||||
* mlo_glb_link glb_link_info[];
|
||||
*/
|
||||
|
|
@ -1779,7 +1779,7 @@ typedef struct {
|
|||
*/
|
||||
A_UINT32 chip_info;
|
||||
/* This TLV is followed by array of mlo_glb_per_chip_crash_info:
|
||||
* mlo_glb_per_chip_crash_info will have mutiple instances equal to num of partner chips
|
||||
* mlo_glb_per_chip_crash_info will have multiple instances equal to num of partner chips
|
||||
* received by no_of_chips
|
||||
* mlo_glb_per_chip_crash_info per_chip_crash_info[];
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -139,6 +139,7 @@ typedef enum {
|
|||
WLAN_MODULE_T2LM, /* 0x64 */
|
||||
WLAN_MODULE_HEALTH_MON, /* 0x65 */
|
||||
WLAN_MODULE_XGAP, /* 0x66 */
|
||||
WLAN_MODULE_MLO_OWNERSHIP_UPDATE, /* 0x67 */
|
||||
|
||||
|
||||
WLAN_MODULE_ID_MAX,
|
||||
|
|
|
|||
5
fw/wmi.h
5
fw/wmi.h
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2017 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
|
||||
*
|
||||
|
|
@ -111,7 +112,7 @@ typedef PREPACK struct {
|
|||
#define WMI_CMD_HDR_PLT_PRIV_OFFSET 0x00000000
|
||||
|
||||
/*
|
||||
* List of Commnands
|
||||
* List of Commands
|
||||
*/
|
||||
typedef enum {
|
||||
WMI_EXTENSION_CMDID, //used in wmi_svc.c /* Non-wireless extensions */
|
||||
|
|
@ -168,7 +169,7 @@ typedef enum {
|
|||
} WMI_PHY_CAPABILITY;
|
||||
|
||||
|
||||
/* Deprectated, need clean up */
|
||||
/* Deprecated, need clean up */
|
||||
#define WMI_MAX_RX_META_SZ (12)
|
||||
|
||||
typedef PREPACK struct {
|
||||
|
|
|
|||
|
|
@ -65,10 +65,10 @@ typedef enum {
|
|||
WMI_SERVICE_GPIO=25, /* GPIO service */
|
||||
WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM=26, /* Modulated DTIM support */
|
||||
WMI_STA_UAPSD_BASIC_AUTO_TRIG=27, /* Basic version of station UAPSD AC Trigger Generation Method with
|
||||
* variable tigger periods (service, delay, and suspend intervals) */
|
||||
* variable trigger periods (service, delay, and suspend intervals) */
|
||||
WMI_STA_UAPSD_VAR_AUTO_TRIG=28, /* Station UAPSD AC Trigger Generation Method with variable
|
||||
* trigger periods (service, delay, and suspend intervals) */
|
||||
WMI_SERVICE_STA_KEEP_ALIVE=29, /* Serivce to support the STA KEEP ALIVE mechanism */
|
||||
WMI_SERVICE_STA_KEEP_ALIVE=29, /* Service to support the STA KEEP ALIVE mechanism */
|
||||
WMI_SERVICE_TX_ENCAP=30, /* Packet type for TX encapsulation */
|
||||
WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC=31, /* detect out-of-sync sleeping stations */
|
||||
WMI_SERVICE_EARLY_RX=32, /* adaptive early-rx feature */
|
||||
|
|
@ -523,8 +523,8 @@ typedef enum {
|
|||
WMI_SERVICE_WAPI_CONCURRENCY_SUPPORTED = 277, /* Indicates FW support for WAPI concurrency */
|
||||
WMI_SERVICE_SAP_CONNECTED_D3WOW = 278, /* Indicates FW support for D3WoW for SAP connected case */
|
||||
WMI_SERVICE_GO_CONNECTED_D3WOW = 279, /* Indicates FW support for D3WoW for P2P GO connected case */
|
||||
WMI_SERVICE_EXT_TPC_REG_SUPPORT = 280, /* Support for new 6G TPC power limits */
|
||||
WMI_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, /* Support for Extended REG_CC Event with additional params for 6G */
|
||||
WMI_SERVICE_EXT_TPC_REG_SUPPORT = 280, /* Support for new 6 GHz TPC power limits */
|
||||
WMI_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, /* Support for Extended REG_CC Event with additional params for 6 GHz */
|
||||
WMI_SERVICE_NDI_TXBF_SUPPORT = 282, /* Indicates FW support for Tx beamforming with NDI VDEV */
|
||||
WMI_SERVICE_ENABLE_LOWER_6G_EDGE_CH_SUPP = 283, /* Indicates FW support for enabling lower 6 GHz edge channel 5935 */
|
||||
WMI_SERVICE_DISABLE_UPPER_6G_EDGE_CH_SUPP = 284, /* Indicates FW support for disabling upper 6 GHz edge channel 7115 */
|
||||
|
|
@ -600,6 +600,9 @@ typedef enum {
|
|||
WMI_SERVICE_XGAP_SUPPORT = 347, /* FW support for XGAP */
|
||||
WMI_SERVICE_OBSS_PER_PACKET_SR_SUPPORT = 348, /* Spatial Reuse support for per PPDU setting */
|
||||
WMI_SERVICE_MULTIPLE_VDEV_RESTART_BITMAP_SUPPORT = 349, /* Extended Multiple VDEV Restart with Bitmap Support */
|
||||
WMI_SERVICE_WMI_SERVICE_WPA3_SHA384_ROAM_SUPPORT = 350, /* Indicates FW supports WPA3 SHA384 roaming */
|
||||
WMI_SERVICE_ODD_LIVEDUMP_SUPPORT = 351, /* Support for ODD Livedump from the FW */
|
||||
WMI_SERVICE_EIRP_PREFERRED_SUPPORT = 352, /* Support for OOBE feature where only EIRP powers will be sent in 6 GHz TPC WMI */
|
||||
|
||||
|
||||
WMI_MAX_EXT2_SERVICE
|
||||
|
|
|
|||
|
|
@ -1299,6 +1299,10 @@ typedef enum {
|
|||
WMITLV_TAG_STRUC_wmi_xgap_enable_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_xgap_enable_complete_event_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_pdev_mesh_rx_filter_enable_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_wfa_config_ofdma,
|
||||
WMITLV_TAG_STRUC_wmi_livedump_request_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_livedump_response_event_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_prb_resp_tmpl_ml_info,
|
||||
} WMITLV_TAG_ID;
|
||||
|
||||
/*
|
||||
|
|
@ -1808,6 +1812,7 @@ typedef enum {
|
|||
OP(WMI_VDEV_PARAM_ENABLE_SR_PROHIBIT_CMDID) \
|
||||
OP(WMI_XGAP_ENABLE_CMDID) \
|
||||
OP(WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID) \
|
||||
OP(WMI_ODD_LIVEDUMP_REQUEST_CMDID) \
|
||||
/* add new CMD_LIST elements above this line */
|
||||
|
||||
|
||||
|
|
@ -2102,6 +2107,7 @@ typedef enum {
|
|||
OP(WMI_IPA_LINK_STATS_EVENTID) \
|
||||
OP(WMI_PDEV_SCHED_TIDQ_SUSP_INFO_EVENTID) \
|
||||
OP(WMI_XGAP_ENABLE_COMPLETE_EVENTID) \
|
||||
OP(WMI_ODD_LIVEDUMP_RESPONSE_EVENTID) \
|
||||
/* add new EVT_LIST elements above this line */
|
||||
|
||||
|
||||
|
|
@ -2507,7 +2513,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_P2P_GO_SET_BEACON_IE);
|
|||
/* GTK offload Cmd */
|
||||
#define WMITLV_TABLE_WMI_GTK_OFFLOAD_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_CMD_fixed_param, WMI_GTK_OFFLOAD_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_gtk_offload_fils_tlv_param, wmi_fils_gtk_info, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_gtk_offload_fils_tlv_param, wmi_fils_gtk_info, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, kek_ext, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, kck_ext, WMITLV_SIZE_VAR)
|
||||
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_GTK_OFFLOAD_CMDID);
|
||||
|
||||
|
|
@ -2535,7 +2543,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_STA_UAPSD_AUTO_TRIG_CMDID);
|
|||
#define WMITLV_TABLE_WMI_PRB_TMPL_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_prb_tmpl_cmd_fixed_param, wmi_prb_tmpl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bcn_prb_info, wmi_bcn_prb_info, bcn_prb_info, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_prb_resp_tmpl_ml_info, ml_prb_resp_info, WMITLV_SIZE_VAR)
|
||||
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PRB_TMPL_CMDID);
|
||||
|
||||
|
|
@ -3199,7 +3208,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DFS_PHYERR_FILTER_DIS_CMDID);
|
|||
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID);
|
||||
|
||||
/* DFS phyerr processing offload disble cmd */
|
||||
/* DFS phyerr processing offload disable cmd */
|
||||
#define WMITLV_TABLE_WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_phyerr_offload_disable_cmd_fixed_param, wmi_pdev_dfs_phyerr_offload_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
|
||||
|
|
@ -4410,7 +4419,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_REORDER_QUEUE_SETUP_CMDID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_reorder_queue_remove_cmd_fixed_param, wmi_peer_reorder_queue_remove_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_REORDER_QUEUE_REMOVE_CMDID);
|
||||
|
||||
/* Filter in monitor mode paramters Cmd */
|
||||
/* Filter in monitor mode parameters Cmd */
|
||||
#define WMITLV_TABLE_WMI_MNT_FILTER_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mnt_filter_cmd_fixed_param, wmi_mnt_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_MNT_FILTER_CMDID);
|
||||
|
|
@ -4912,7 +4921,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SIMULATION_TEST_CMDID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_rsnxe, wfa_config_rsnxe, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_csa, wfa_config_csa, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ocv, wfa_config_ocv, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_saquery, wfa_config_saquery, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_saquery, wfa_config_saquery, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ofdma, wfa_config_ofdma, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_WFA_CONFIG_CMDID);
|
||||
|
||||
/* SRG OBSS color Enable Bitmap */
|
||||
|
|
@ -5160,6 +5170,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PARAM_ENABLE_SR_PROHIBIT_CMDID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_xgap_enable_cmd_fixed_param, wmi_xgap_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_XGAP_ENABLE_CMDID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_ODD_LIVEDUMP_REQUEST_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_livedump_request_cmd_fixed_param, wmi_livedump_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_livedump_id_list, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ODD_LIVEDUMP_REQUEST_CMDID);
|
||||
|
||||
|
||||
|
||||
/************************** TLV definitions of WMI events *******************************/
|
||||
|
|
@ -5622,7 +5637,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_GTK_OFFLOAD_STATUS_EVENTID);
|
||||
|
||||
/* DCA interferance Event */
|
||||
/* DCA interference Event */
|
||||
#define WMITLV_TABLE_WMI_DCS_INTERFERENCE_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dcs_interference_event_fixed_param, wmi_dcs_interference_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wlan_dcs_cw_int, cw_int, WMITLV_SIZE_VAR) \
|
||||
|
|
@ -6051,7 +6066,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NDP_CONFIRM_EVENTID);
|
|||
WMITLV_CREATE_PARAM_STRUC(WMI_NDP_END_INDICATION_EVENTID);
|
||||
|
||||
/** NDL schedule update event
|
||||
* TLV (tag lenght value ) parameters follow the ndl_schedule_update
|
||||
* TLV (tag length value) parameters follow the ndl_schedule_update
|
||||
* structure. The TLV's are:
|
||||
* A_UINT32 ndp_instance_list[];
|
||||
* wmi_channel ndl_channel_list[];
|
||||
|
|
@ -7002,6 +7017,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HEALTH_MON_INIT_DONE_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_xgap_enable_complete_event_fixed_param, wmi_xgap_enable_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_XGAP_ENABLE_COMPLETE_EVENTID);
|
||||
|
||||
/* ODD Livedump */
|
||||
#define WMITLV_TABLE_WMI_ODD_LIVEDUMP_RESPONSE_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_livedump_response_event_fixed_param, wmi_livedump_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_ODD_LIVEDUMP_RESPONSE_EVENTID);
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
525
fw/wmi_unified.h
525
fw/wmi_unified.h
File diff suppressed because it is too large
Load diff
|
|
@ -37,7 +37,7 @@
|
|||
#define __WMI_VER_MINOR_ 0
|
||||
/** WMI revision number has to be incremented when there is a
|
||||
* change that may or may not break compatibility. */
|
||||
#define __WMI_REVISION_ 1214
|
||||
#define __WMI_REVISION_ 1224
|
||||
|
||||
/** The Version Namespace should not be normally changed. Only
|
||||
* host and firmware of the same WMI namespace will work
|
||||
|
|
|
|||
|
|
@ -14,15 +14,6 @@
|
|||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_MSDU_LINK_H_
|
||||
#define _RX_MSDU_LINK_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
|
|
@ -141,15 +132,39 @@ struct rx_msdu_link {
|
|||
#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
|
||||
|
||||
|
||||
/* Description TX_MPDU_QUEUE_NUMBER
|
||||
|
||||
Consumer: TQM/Debug
|
||||
Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
|
||||
|
||||
Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
|
||||
|
||||
|
||||
Indicates the MPDU queue ID to which this MPDU descriptor
|
||||
belongs
|
||||
Used for tracking and debugging
|
||||
|
||||
Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,'
|
||||
word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT'
|
||||
for this.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
|
||||
#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
|
||||
#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
|
||||
#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
|
||||
#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
|
||||
#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
|
||||
#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
|
||||
#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
|
||||
#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
|
||||
|
||||
|
||||
/* Description NEXT_MSDU_LINK_DESC_ADDR_INFO
|
||||
|
|
|
|||
|
|
@ -14,14 +14,6 @@
|
|||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_PPDU_END_USER_STATS_H_
|
||||
#define _RX_PPDU_END_USER_STATS_H_
|
||||
|
|
@ -123,7 +115,7 @@ struct rx_ppdu_end_user_stats {
|
|||
amsdu_msdu_count : 16; // [31:16]
|
||||
uint32_t non_amsdu_msdu_count : 16, // [15:0]
|
||||
ucast_msdu_count : 16; // [31:16]
|
||||
uint32_t mcast_msdu_count : 16, // [15:0]
|
||||
uint32_t bcast_msdu_count : 16, // [15:0]
|
||||
mcast_bcast_msdu_count : 16; // [31:16]
|
||||
#else
|
||||
struct rx_rxpcu_classification_overview rxpcu_classification_details;
|
||||
|
|
@ -214,7 +206,7 @@ struct rx_ppdu_end_user_stats {
|
|||
uint32_t ucast_msdu_count : 16, // [31:16]
|
||||
non_amsdu_msdu_count : 16; // [15:0]
|
||||
uint32_t mcast_bcast_msdu_count : 16, // [31:16]
|
||||
mcast_msdu_count : 16; // [15:0]
|
||||
bcast_msdu_count : 16; // [15:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -1801,9 +1793,8 @@ struct rx_ppdu_end_user_stats {
|
|||
Field filled in by RX OLE
|
||||
Set to 0 by RXPCU
|
||||
|
||||
The number of MSDUs that are part of MPDUs without FCS error
|
||||
|
||||
TODO: unicast AD1 or DA?
|
||||
The number of MSDUs that are part of MPDUs without FCS error,
|
||||
that are directed to a unicast destination address
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
|
|
@ -1813,21 +1804,21 @@ struct rx_ppdu_end_user_stats {
|
|||
#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description MCAST_MSDU_COUNT
|
||||
/* Description BCAST_MSDU_COUNT
|
||||
|
||||
Field filled in by RX OLE
|
||||
Set to 0 by RXPCU
|
||||
|
||||
The number of MSDUs that are part of MPDUs without FCS error
|
||||
The number of MSDUs that are part of MPDUs without FCS error,
|
||||
whose destination addresses are broadcast (0xFFFF_FFFF_FFFF)
|
||||
|
||||
TODO: multicast AD1 or DA?
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RX_PPDU_END_USER_STATS_MCAST_MSDU_COUNT_OFFSET 0x0000000000000070
|
||||
#define RX_PPDU_END_USER_STATS_MCAST_MSDU_COUNT_LSB 32
|
||||
#define RX_PPDU_END_USER_STATS_MCAST_MSDU_COUNT_MSB 47
|
||||
#define RX_PPDU_END_USER_STATS_MCAST_MSDU_COUNT_MASK 0x0000ffff00000000
|
||||
#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070
|
||||
#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32
|
||||
#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47
|
||||
#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description MCAST_BCAST_MSDU_COUNT
|
||||
|
|
@ -1835,9 +1826,9 @@ struct rx_ppdu_end_user_stats {
|
|||
Field filled in by RX OLE
|
||||
Set to 0 by RXPCU
|
||||
|
||||
The number of MSDUs that are part of MPDUs without FCS error
|
||||
The number of MSDUs that are part of MPDUs without FCS error,
|
||||
whose destination addresses are either multicast or broadcast
|
||||
|
||||
TODO: multicast/broadcast AD1 or DA?
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -14,14 +14,6 @@
|
|||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_REO_QUEUE_H_
|
||||
#define _RX_REO_QUEUE_H_
|
||||
|
|
@ -243,15 +235,39 @@ struct rx_reo_queue {
|
|||
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
|
||||
|
||||
|
||||
/* Description TX_MPDU_QUEUE_NUMBER
|
||||
|
||||
Consumer: TQM/Debug
|
||||
Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
|
||||
|
||||
Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
|
||||
|
||||
|
||||
Indicates the MPDU queue ID to which this MPDU descriptor
|
||||
belongs
|
||||
Used for tracking and debugging
|
||||
|
||||
Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,'
|
||||
word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT'
|
||||
for this.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
|
||||
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
|
||||
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
|
||||
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
|
||||
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
|
||||
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
|
||||
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
|
||||
|
||||
|
||||
/* Description RECEIVE_QUEUE_NUMBER
|
||||
|
|
|
|||
|
|
@ -14,14 +14,6 @@
|
|||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_REO_QUEUE_1K_H_
|
||||
#define _RX_REO_QUEUE_1K_H_
|
||||
|
|
@ -173,15 +165,39 @@ struct rx_reo_queue_1k {
|
|||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
|
||||
|
||||
|
||||
/* Description TX_MPDU_QUEUE_NUMBER
|
||||
|
||||
Consumer: TQM/Debug
|
||||
Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
|
||||
|
||||
Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
|
||||
|
||||
|
||||
Indicates the MPDU queue ID to which this MPDU descriptor
|
||||
belongs
|
||||
Used for tracking and debugging
|
||||
|
||||
Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,'
|
||||
word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT'
|
||||
for this.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
|
||||
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
|
||||
|
||||
|
||||
/* Description RX_BITMAP_319_288
|
||||
|
|
|
|||
|
|
@ -14,14 +14,6 @@
|
|||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_REO_QUEUE_EXT_H_
|
||||
#define _RX_REO_QUEUE_EXT_H_
|
||||
|
|
@ -144,15 +136,39 @@ struct rx_reo_queue_ext {
|
|||
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
|
||||
|
||||
|
||||
/* Description TX_MPDU_QUEUE_NUMBER
|
||||
|
||||
Consumer: TQM/Debug
|
||||
Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
|
||||
|
||||
Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
|
||||
|
||||
|
||||
Indicates the MPDU queue ID to which this MPDU descriptor
|
||||
belongs
|
||||
Used for tracking and debugging
|
||||
|
||||
Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,'
|
||||
word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT'
|
||||
for this.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
|
||||
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
|
||||
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
|
||||
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
|
||||
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
|
||||
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
|
||||
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
|
||||
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
|
|
|||
|
|
@ -14,14 +14,6 @@
|
|||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
|
||||
#define _UNIFORM_DESCRIPTOR_HEADER_H_
|
||||
|
|
@ -35,9 +27,11 @@ struct uniform_descriptor_header {
|
|||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t owner : 4, // [3:0]
|
||||
buffer_type : 4, // [7:4]
|
||||
reserved_0a : 24; // [31:8]
|
||||
tx_mpdu_queue_number : 20, // [27:8]
|
||||
reserved_0a : 4; // [31:28]
|
||||
#else
|
||||
uint32_t reserved_0a : 24, // [31:8]
|
||||
uint32_t reserved_0a : 4, // [31:28]
|
||||
tx_mpdu_queue_number : 20, // [27:8]
|
||||
buffer_type : 4, // [7:4]
|
||||
owner : 4; // [3:0]
|
||||
#endif
|
||||
|
|
@ -106,15 +100,39 @@ struct uniform_descriptor_header {
|
|||
#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
|
||||
|
||||
|
||||
/* Description TX_MPDU_QUEUE_NUMBER
|
||||
|
||||
Consumer: TQM/Debug
|
||||
Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere)
|
||||
|
||||
Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor
|
||||
|
||||
|
||||
Indicates the MPDU queue ID to which this MPDU descriptor
|
||||
belongs
|
||||
Used for tracking and debugging
|
||||
|
||||
Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,'
|
||||
word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT'
|
||||
for this.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
|
||||
#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
|
||||
#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
|
||||
#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
|
||||
#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
|
||||
#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
|
||||
#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
|
||||
#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
|
||||
#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
|
||||
#ifndef __WCSS_SEQ_HWIOREG_UMAC_H__
|
||||
#define __WCSS_SEQ_HWIOREG_UMAC_H__
|
||||
|
||||
#include "seq_hwio.h"
|
||||
#include "wcss_seq_hwiobase.h"
|
||||
#ifdef SCALE_INCLUDES
|
||||
|
|
@ -767,9 +766,49 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_ADDR_BMSK 0x1fffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_ADDR_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x) ((x) + 0xa0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_PHYS(x) ((x) + 0xa0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_OFFS (0xa0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xa0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xa0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xa0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0x7
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \
|
||||
in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \
|
||||
in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \
|
||||
out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \
|
||||
out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7
|
||||
#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xa4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xa4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xa4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \
|
||||
in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x))
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \
|
||||
in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \
|
||||
out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \
|
||||
out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x))
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x) ((x) + 0xa8)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_PHYS(x) ((x) + 0xa8)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_OFFS (0xa8)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_POR_RMSK 0xffffffff
|
||||
|
|
@ -785,9 +824,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_VAL_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_VAL_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x) ((x) + 0xa4)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_PHYS(x) ((x) + 0xa4)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_OFFS (0xa4)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x) ((x) + 0xac)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_PHYS(x) ((x) + 0xac)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_OFFS (0xac)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_POR_RMSK 0xffffffff
|
||||
|
|
@ -803,9 +842,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_BASE_ADDR_LSB_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_BASE_ADDR_LSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x) ((x) + 0xa8)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_PHYS(x) ((x) + 0xa8)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_OFFS (0xa8)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x) ((x) + 0xb0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_PHYS(x) ((x) + 0xb0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_OFFS (0xb0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_RMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_POR_RMSK 0xffffffff
|
||||
|
|
@ -821,9 +860,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_BASE_ADDR_MSB_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_BASE_ADDR_MSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x) ((x) + 0xac)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_PHYS(x) ((x) + 0xac)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_OFFS (0xac)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x) ((x) + 0xb4)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_PHYS(x) ((x) + 0xb4)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_OFFS (0xb4)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_POR_RMSK 0xffffffff
|
||||
|
|
@ -839,9 +878,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_BASE_ADDR_MASK_LSB_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_BASE_ADDR_MASK_LSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x) ((x) + 0xb0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_PHYS(x) ((x) + 0xb0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_OFFS (0xb0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x) ((x) + 0xb8)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_PHYS(x) ((x) + 0xb8)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_OFFS (0xb8)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_RMSK 0xc00000ff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_POR 0x00000010
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_POR_RMSK 0xffffffff
|
||||
|
|
@ -861,9 +900,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_BASE_ADDR_MASK_MSB_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_BASE_ADDR_MASK_MSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ADDR(x) ((x) + 0xb4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_PHYS(x) ((x) + 0xb4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_OFFS (0xb4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ADDR(x) ((x) + 0xbc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_PHYS(x) ((x) + 0xbc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_OFFS (0xbc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_POR_RMSK 0xffffffff
|
||||
|
|
@ -875,9 +914,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_VALUE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ADDR(x) ((x) + 0xb8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_PHYS(x) ((x) + 0xb8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_OFFS (0xb8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ADDR(x) ((x) + 0xc0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_PHYS(x) ((x) + 0xc0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_OFFS (0xc0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_RMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_POR_RMSK 0xffffffff
|
||||
|
|
@ -889,9 +928,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_VALUE_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_VALUE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ADDR(x) ((x) + 0xbc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_PHYS(x) ((x) + 0xbc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_OFFS (0xbc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ADDR(x) ((x) + 0xc4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_PHYS(x) ((x) + 0xc4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_OFFS (0xc4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_RMSK 0xfff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_POR 0x00000211
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_POR_RMSK 0xffffffff
|
||||
|
|
@ -907,9 +946,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0xf
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x) ((x) + 0xc0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_PHYS(x) ((x) + 0xc0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_OFFS (0xc0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x) ((x) + 0xc8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_PHYS(x) ((x) + 0xc8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_OFFS (0xc8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_RMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_POR_RMSK 0xffffffff
|
||||
|
|
@ -925,9 +964,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x) ((x) + 0xc4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_PHYS(x) ((x) + 0xc4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_OFFS (0xc4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x) ((x) + 0xcc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_PHYS(x) ((x) + 0xcc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_OFFS (0xcc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RMSK 0x80003fff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_POR_RMSK 0xffffffff
|
||||
|
|
@ -971,10 +1010,10 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ADDR(x) ((x) + 0xc8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_PHYS(x) ((x) + 0xc8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_OFFS (0xc8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_RMSK 0x81010101
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ADDR(x) ((x) + 0xd0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_PHYS(x) ((x) + 0xd0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_OFFS (0xd0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_RMSK 0x81011f01
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_POR_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ATTR 0x1
|
||||
|
|
@ -988,14 +1027,22 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 24
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x10000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 16
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_HW_ERR_INT_BMSK 0x100
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_HW_ERR_INT_SHFT 8
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_WARN_INT_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_WARN_INT_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ADDR(x) ((x) + 0xcc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_PHYS(x) ((x) + 0xcc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_OFFS (0xcc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ADDR(x) ((x) + 0xd4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_PHYS(x) ((x) + 0xd4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_OFFS (0xd4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_RMSK 0xffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_POR_RMSK 0xffffffff
|
||||
|
|
@ -1011,9 +1058,29 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ADDR(x) ((x) + 0xd0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_PHYS(x) ((x) + 0xd0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_OFFS (0xd0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0xd8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0xd8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0xd8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \
|
||||
in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x))
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \
|
||||
in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ADDR(x) ((x) + 0xdc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_PHYS(x) ((x) + 0xdc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_OFFS (0xdc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_RMSK 0x1010101
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_POR_RMSK 0xffffffff
|
||||
|
|
@ -1031,9 +1098,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_TIMEOUT_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_TIMEOUT_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ADDR(x) ((x) + 0xd4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_PHYS(x) ((x) + 0xd4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_OFFS (0xd4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ADDR(x) ((x) + 0xe0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_PHYS(x) ((x) + 0xe0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_OFFS (0xe0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_RMSK 0xffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_POR_RMSK 0xffffffff
|
||||
|
|
@ -1047,9 +1114,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_RD_PCIE_L0_ACC_ERR_PORT_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_RD_PCIE_L0_ACC_ERR_PORT_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x) ((x) + 0xd8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_PHYS(x) ((x) + 0xd8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_OFFS (0xd8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x) ((x) + 0xe4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_PHYS(x) ((x) + 0xe4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_OFFS (0xe4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_POR_RMSK 0xffffffff
|
||||
|
|
@ -1071,9 +1138,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x3f
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x) ((x) + 0xdc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_PHYS(x) ((x) + 0xdc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_OFFS (0xdc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x) ((x) + 0xe8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_PHYS(x) ((x) + 0xe8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_OFFS (0xe8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_POR_RMSK 0xffffffff
|
||||
|
|
@ -1095,9 +1162,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x3f
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x) ((x) + 0xe0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_PHYS(x) ((x) + 0xe0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_OFFS (0xe0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x) ((x) + 0xec)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_PHYS(x) ((x) + 0xec)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_OFFS (0xec)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_RMSK 0xefffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_POR 0x46000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_POR_RMSK 0xffffffff
|
||||
|
|
@ -1121,9 +1188,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_CLEAR_STATS_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_CLEAR_STATS_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x) ((x) + 0xe4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_PHYS(x) ((x) + 0xe4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_OFFS (0xe4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x) ((x) + 0xf0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_PHYS(x) ((x) + 0xf0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_OFFS (0xf0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_RMSK 0xc00007ff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_POR 0x00000013
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_POR_RMSK 0xffffffff
|
||||
|
|
@ -1155,9 +1222,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_EXT_BMSK 0x7
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_EXT_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x) ((x) + 0xe8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_PHYS(x) ((x) + 0xe8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_OFFS (0xe8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x) ((x) + 0xf4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_PHYS(x) ((x) + 0xf4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_OFFS (0xf4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_RMSK 0xffff0001
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_POR 0x00ff0000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_POR_RMSK 0xffffffff
|
||||
|
|
@ -1175,9 +1242,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_DISABLE_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_DISABLE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ADDR(x) ((x) + 0xec)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_PHYS(x) ((x) + 0xec)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_OFFS (0xec)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ADDR(x) ((x) + 0xf8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_PHYS(x) ((x) + 0xf8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_OFFS (0xf8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_RMSK 0xffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_POR_RMSK 0xffffffff
|
||||
|
|
@ -1189,9 +1256,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_GXI_WDOG_WARN_STATUS_BMSK 0xffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_GXI_WDOG_WARN_STATUS_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ADDR(x) ((x) + 0xf0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_PHYS(x) ((x) + 0xf0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_OFFS (0xf0)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ADDR(x) ((x) + 0xfc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_PHYS(x) ((x) + 0xfc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_OFFS (0xfc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_POR_RMSK 0xffffffff
|
||||
|
|
@ -1205,9 +1272,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0xffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x) ((x) + 0xf4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_PHYS(x) ((x) + 0xf4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_OFFS (0xf4)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x) ((x) + 0x100)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_PHYS(x) ((x) + 0x100)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_OFFS (0x100)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_RMSK 0xffff0001
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_POR 0x00ff0000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_POR_RMSK 0xffffffff
|
||||
|
|
@ -1225,9 +1292,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_DISABLE_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_DISABLE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ADDR(x) ((x) + 0xf8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_PHYS(x) ((x) + 0xf8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_OFFS (0xf8)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ADDR(x) ((x) + 0x104)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_PHYS(x) ((x) + 0x104)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_OFFS (0x104)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_RMSK 0xffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_POR_RMSK 0xffffffff
|
||||
|
|
@ -1239,9 +1306,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_GXI_WDOG_HW_ERR_STATUS_BMSK 0xffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_GXI_WDOG_HW_ERR_STATUS_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) ((x) + 0xfc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) ((x) + 0xfc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_OFFS (0xfc)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) ((x) + 0x108)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) ((x) + 0x108)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_OFFS (0x108)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_RMSK 0xfffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_POR_RMSK 0xffffffff
|
||||
|
|
@ -1261,9 +1328,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) ((x) + 0x100)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) ((x) + 0x100)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_OFFS (0x100)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) ((x) + 0x10c)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) ((x) + 0x10c)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_OFFS (0x10c)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_RMSK 0xfffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_POR_RMSK 0xffffffff
|
||||
|
|
@ -1283,9 +1350,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x104)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x104)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS (0x104)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x110)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x110)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS (0x110)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xffffffff
|
||||
|
|
@ -1301,9 +1368,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x108)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x108)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS (0x108)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x114)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x114)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS (0x114)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xffffffff
|
||||
|
|
@ -1319,9 +1386,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x10c)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x10c)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS (0x10c)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x118)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x118)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS (0x118)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xffffffff
|
||||
|
|
@ -1337,9 +1404,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x110)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x110)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS (0x110)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x11c)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x11c)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS (0x11c)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xffffffff
|
||||
|
|
@ -1355,9 +1422,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) ((x) + 0x114)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) ((x) + 0x114)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_OFFS (0x114)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) ((x) + 0x120)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) ((x) + 0x120)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_OFFS (0x120)
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0xbfbf
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_POR_RMSK 0xffffffff
|
||||
|
|
@ -1379,9 +1446,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x3f
|
||||
#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x) ((x) + 0x118)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_PHYS(x) ((x) + 0x118)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_OFFS (0x118)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x) ((x) + 0x124)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_PHYS(x) ((x) + 0x124)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_OFFS (0x124)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RMSK 0xbfbf
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_POR_RMSK 0xffffffff
|
||||
|
|
@ -1403,9 +1470,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_ADDR_BMSK 0x3f
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_ADDR_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ADDR(x) ((x) + 0x11c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_PHYS(x) ((x) + 0x11c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_OFFS (0x11c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ADDR(x) ((x) + 0x128)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_PHYS(x) ((x) + 0x128)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_OFFS (0x128)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RMSK 0x3f3f3f3f
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_POR_RMSK 0xffffffff
|
||||
|
|
@ -1423,9 +1490,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_RD_PTR_BMSK 0x3f
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_RD_PTR_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ADDR(x) ((x) + 0x120)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_PHYS(x) ((x) + 0x120)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_OFFS (0x120)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ADDR(x) ((x) + 0x12c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_PHYS(x) ((x) + 0x12c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_OFFS (0x12c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_POR_RMSK 0xffffffff
|
||||
|
|
@ -1437,9 +1504,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_VALUE_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_VALUE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ADDR(x) ((x) + 0x124)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_PHYS(x) ((x) + 0x124)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_OFFS (0x124)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ADDR(x) ((x) + 0x130)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_PHYS(x) ((x) + 0x130)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_OFFS (0x130)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_POR_RMSK 0xffffffff
|
||||
|
|
@ -1451,9 +1518,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_VALUE_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_VALUE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ADDR(x) ((x) + 0x128)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_PHYS(x) ((x) + 0x128)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_OFFS (0x128)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ADDR(x) ((x) + 0x134)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_PHYS(x) ((x) + 0x134)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_OFFS (0x134)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_POR_RMSK 0xffffffff
|
||||
|
|
@ -1465,9 +1532,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_VALUE_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_VALUE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ADDR(x) ((x) + 0x12c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_PHYS(x) ((x) + 0x12c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_OFFS (0x12c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ADDR(x) ((x) + 0x138)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_PHYS(x) ((x) + 0x138)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_OFFS (0x138)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_POR_RMSK 0xffffffff
|
||||
|
|
@ -1479,9 +1546,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_VALUE_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_VALUE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_ADDR(x) ((x) + 0x130)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_PHYS(x) ((x) + 0x130)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_OFFS (0x130)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_ADDR(x) ((x) + 0x13c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_PHYS(x) ((x) + 0x13c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_OFFS (0x13c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_POR 0xff000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_POR_RMSK 0xffffffff
|
||||
|
|
@ -1497,9 +1564,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_REG_SS_ADDR_MASK_LSB_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_LSB_REG_SS_ADDR_MASK_LSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_ADDR(x) ((x) + 0x134)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_PHYS(x) ((x) + 0x134)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_OFFS (0x134)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_ADDR(x) ((x) + 0x140)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_PHYS(x) ((x) + 0x140)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_OFFS (0x140)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_RMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_POR 0x0000007f
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_POR_RMSK 0xffffffff
|
||||
|
|
@ -1515,9 +1582,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_REG_SS_ADDR_MASK_MSB_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_MASK_MSB_REG_SS_ADDR_MASK_MSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x) ((x) + 0x138)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_PHYS(x) ((x) + 0x138)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_OFFS (0x138)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x) ((x) + 0x144)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_PHYS(x) ((x) + 0x144)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_OFFS (0x144)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_POR_RMSK 0xffffffff
|
||||
|
|
@ -1533,9 +1600,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_REG_INT_ADDR_MASK_LSB_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_REG_INT_ADDR_MASK_LSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x) ((x) + 0x13c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_PHYS(x) ((x) + 0x13c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_OFFS (0x13c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x) ((x) + 0x148)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_PHYS(x) ((x) + 0x148)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_OFFS (0x148)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_RMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_POR 0x00000010
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_POR_RMSK 0xffffffff
|
||||
|
|
@ -1551,9 +1618,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_REG_INT_ADDR_MASK_MSB_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_REG_INT_ADDR_MASK_MSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x) ((x) + 0x140)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_PHYS(x) ((x) + 0x140)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_OFFS (0x140)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x) ((x) + 0x14c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_PHYS(x) ((x) + 0x14c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_OFFS (0x14c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_POR 0x00b80000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_POR_RMSK 0xffffffff
|
||||
|
|
@ -1569,9 +1636,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_REG_SS_ADDR_RANGE_LSB_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_REG_SS_ADDR_RANGE_LSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x) ((x) + 0x144)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_PHYS(x) ((x) + 0x144)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_OFFS (0x144)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x) ((x) + 0x150)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_PHYS(x) ((x) + 0x150)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_OFFS (0x150)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_RMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_POR 0x00000010
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_POR_RMSK 0xffffffff
|
||||
|
|
@ -1587,9 +1654,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_REG_SS_ADDR_RANGE_MSB_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_REG_SS_ADDR_RANGE_MSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x) ((x) + 0x148)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_PHYS(x) ((x) + 0x148)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_OFFS (0x148)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x) ((x) + 0x154)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_PHYS(x) ((x) + 0x154)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_OFFS (0x154)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_RMSK 0xff13ff13
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_POR_RMSK 0xffffffff
|
||||
|
|
@ -1619,9 +1686,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_INJ_ENABLE_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_INJ_ENABLE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x) ((x) + 0x14c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_PHYS(x) ((x) + 0x14c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_OFFS (0x14c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x) ((x) + 0x158)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_PHYS(x) ((x) + 0x158)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_OFFS (0x158)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_RMSK 0xff07ff07
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_POR_RMSK 0xffffffff
|
||||
|
|
@ -1651,9 +1718,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_INJ_ENABLE_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_INJ_ENABLE_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x) ((x) + 0x150)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_PHYS(x) ((x) + 0x150)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_OFFS (0x150)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x) ((x) + 0x15c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_PHYS(x) ((x) + 0x15c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_OFFS (0x15c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_POR_RMSK 0xffffffff
|
||||
|
|
@ -1669,9 +1736,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x) ((x) + 0x154)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_PHYS(x) ((x) + 0x154)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_OFFS (0x154)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x) ((x) + 0x160)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_PHYS(x) ((x) + 0x160)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_OFFS (0x160)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_RMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_POR_RMSK 0xffffffff
|
||||
|
|
@ -1687,9 +1754,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x) ((x) + 0x158)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_PHYS(x) ((x) + 0x158)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_OFFS (0x158)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x) ((x) + 0x164)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_PHYS(x) ((x) + 0x164)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_OFFS (0x164)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_POR_RMSK 0xffffffff
|
||||
|
|
@ -1705,9 +1772,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x) ((x) + 0x15c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_PHYS(x) ((x) + 0x15c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_OFFS (0x15c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x) ((x) + 0x168)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_PHYS(x) ((x) + 0x168)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_OFFS (0x168)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_POR_RMSK 0xffffffff
|
||||
|
|
@ -1723,9 +1790,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x) ((x) + 0x160)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_PHYS(x) ((x) + 0x160)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_OFFS (0x160)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x) ((x) + 0x16c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_PHYS(x) ((x) + 0x16c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_OFFS (0x16c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_POR_RMSK 0xffffffff
|
||||
|
|
@ -1741,9 +1808,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x) ((x) + 0x164)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_PHYS(x) ((x) + 0x164)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_OFFS (0x164)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x) ((x) + 0x170)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_PHYS(x) ((x) + 0x170)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_OFFS (0x170)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_RMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_POR_RMSK 0xffffffff
|
||||
|
|
@ -1759,9 +1826,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x) ((x) + 0x168)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_PHYS(x) ((x) + 0x168)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_OFFS (0x168)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x) ((x) + 0x174)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_PHYS(x) ((x) + 0x174)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_OFFS (0x174)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_POR_RMSK 0xffffffff
|
||||
|
|
@ -1777,9 +1844,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x) ((x) + 0x16c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_PHYS(x) ((x) + 0x16c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_OFFS (0x16c)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x) ((x) + 0x178)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_PHYS(x) ((x) + 0x178)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_OFFS (0x178)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_POR_RMSK 0xffffffff
|
||||
|
|
@ -1795,9 +1862,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x) ((x) + 0x170)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_PHYS(x) ((x) + 0x170)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_OFFS (0x170)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x) ((x) + 0x17c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_PHYS(x) ((x) + 0x17c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_OFFS (0x17c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_RMSK 0x3fffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_POR 0x08000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_POR_RMSK 0xffffffff
|
||||
|
|
@ -1823,9 +1890,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_BMSK 0x1ffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x) ((x) + 0x174)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_PHYS(x) ((x) + 0x174)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_OFFS (0x174)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x) ((x) + 0x180)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_PHYS(x) ((x) + 0x180)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_OFFS (0x180)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_POR_RMSK 0xffffffff
|
||||
|
|
@ -1841,9 +1908,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ID_BITMAP_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ID_BITMAP_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x) ((x) + 0x178)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_PHYS(x) ((x) + 0x178)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_OFFS (0x178)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x) ((x) + 0x184)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_PHYS(x) ((x) + 0x184)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_OFFS (0x184)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_POR_RMSK 0xffffffff
|
||||
|
|
@ -1859,9 +1926,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ID_BITMAP_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ID_BITMAP_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ADDR(x) ((x) + 0x17c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_PHYS(x) ((x) + 0x17c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_OFFS (0x17c)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ADDR(x) ((x) + 0x188)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_PHYS(x) ((x) + 0x188)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_OFFS (0x188)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_RMSK 0xf
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_POR_RMSK 0xffffffff
|
||||
|
|
@ -1877,9 +1944,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_ERROR_STATUS_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_ERROR_STATUS_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR(base,n) ((base) + 0X180 + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_PHYS(base,n) ((base) + 0X180 + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_OFFS(n) (0X180 + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR(base,n) ((base) + 0X18C + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_PHYS(base,n) ((base) + 0X18C + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_OFFS(n) (0X18C + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_MAXn 3
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_POR 0x00000000
|
||||
|
|
@ -1892,9 +1959,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR_LOW_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR_LOW_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR(base,n) ((base) + 0X190 + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_PHYS(base,n) ((base) + 0X190 + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_OFFS(n) (0X190 + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR(base,n) ((base) + 0X19C + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_PHYS(base,n) ((base) + 0X19C + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_OFFS(n) (0X19C + (0x4*(n)))
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_MAXn 3
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_POR 0x00000000
|
||||
|
|
@ -1919,9 +1986,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR_HIGH_BMSK 0xff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR_HIGH_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ADDR(x) ((x) + 0x1a0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_PHYS(x) ((x) + 0x1a0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_OFFS (0x1a0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ADDR(x) ((x) + 0x1ac)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_PHYS(x) ((x) + 0x1ac)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_OFFS (0x1ac)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_POR_RMSK 0xffffffff
|
||||
|
|
@ -1933,9 +2000,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_TIMESTAMP_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_TIMESTAMP_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ADDR(x) ((x) + 0x1a4)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_PHYS(x) ((x) + 0x1a4)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_OFFS (0x1a4)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ADDR(x) ((x) + 0x1b0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_PHYS(x) ((x) + 0x1b0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_OFFS (0x1b0)
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_RMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_POR_RMSK 0xffffffff
|
||||
|
|
@ -1947,9 +2014,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_TIMESTAMP_BMSK 0xffffffff
|
||||
#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_TIMESTAMP_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x) ((x) + 0x1a8)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_PHYS(x) ((x) + 0x1a8)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_OFFS (0x1a8)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x) ((x) + 0x1b4)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_PHYS(x) ((x) + 0x1b4)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_OFFS (0x1b4)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_RMSK 0xfff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_POR 0x00000049
|
||||
#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_POR_RMSK 0xffffffff
|
||||
|
|
@ -1979,9 +2046,9 @@
|
|||
#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_EN_BMSK 0x1
|
||||
#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_EN_SHFT 0
|
||||
|
||||
#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ADDR(x) ((x) + 0x1ac)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_PHYS(x) ((x) + 0x1ac)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_OFFS (0x1ac)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ADDR(x) ((x) + 0x1b8)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_PHYS(x) ((x) + 0x1b8)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_OFFS (0x1b8)
|
||||
#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RMSK 0x1ff01ff
|
||||
#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_POR 0x00000000
|
||||
#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_POR_RMSK 0xffffffff
|
||||
|
|
@ -15747,7 +15814,7 @@
|
|||
#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18)
|
||||
#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18)
|
||||
#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff
|
||||
#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x6666ba98
|
||||
#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x66666668
|
||||
#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff
|
||||
#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3
|
||||
#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \
|
||||
|
|
@ -35084,7 +35151,7 @@
|
|||
#define HWIO_UMCMN_R0_ISR_S16_ADDR(x) ((x) + 0x74)
|
||||
#define HWIO_UMCMN_R0_ISR_S16_PHYS(x) ((x) + 0x74)
|
||||
#define HWIO_UMCMN_R0_ISR_S16_OFFS (0x74)
|
||||
#define HWIO_UMCMN_R0_ISR_S16_RMSK 0x1f
|
||||
#define HWIO_UMCMN_R0_ISR_S16_RMSK 0x1ff
|
||||
#define HWIO_UMCMN_R0_ISR_S16_POR 0x00000000
|
||||
#define HWIO_UMCMN_R0_ISR_S16_POR_RMSK 0xffffffff
|
||||
#define HWIO_UMCMN_R0_ISR_S16_ATTR 0x0
|
||||
|
|
@ -35096,6 +35163,14 @@
|
|||
out_dword(HWIO_UMCMN_R0_ISR_S16_ADDR(x),v)
|
||||
#define HWIO_UMCMN_R0_ISR_S16_OUTM(x,m,v) \
|
||||
out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S16_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S16_IN(x))
|
||||
#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100
|
||||
#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8
|
||||
#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80
|
||||
#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7
|
||||
#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40
|
||||
#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6
|
||||
#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20
|
||||
#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5
|
||||
#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_ERR_BMSK 0x10
|
||||
#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_ERR_SHFT 4
|
||||
#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_AXI_WR_ERR_BMSK 0x8
|
||||
|
|
@ -36054,7 +36129,7 @@
|
|||
#define HWIO_UMCMN_R0_IMR_S16_ADDR(x) ((x) + 0xbc)
|
||||
#define HWIO_UMCMN_R0_IMR_S16_PHYS(x) ((x) + 0xbc)
|
||||
#define HWIO_UMCMN_R0_IMR_S16_OFFS (0xbc)
|
||||
#define HWIO_UMCMN_R0_IMR_S16_RMSK 0x1f
|
||||
#define HWIO_UMCMN_R0_IMR_S16_RMSK 0x1ff
|
||||
#define HWIO_UMCMN_R0_IMR_S16_POR 0x00000000
|
||||
#define HWIO_UMCMN_R0_IMR_S16_POR_RMSK 0xffffffff
|
||||
#define HWIO_UMCMN_R0_IMR_S16_ATTR 0x3
|
||||
|
|
@ -36066,6 +36141,14 @@
|
|||
out_dword(HWIO_UMCMN_R0_IMR_S16_ADDR(x),v)
|
||||
#define HWIO_UMCMN_R0_IMR_S16_OUTM(x,m,v) \
|
||||
out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S16_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S16_IN(x))
|
||||
#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100
|
||||
#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8
|
||||
#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80
|
||||
#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7
|
||||
#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40
|
||||
#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6
|
||||
#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20
|
||||
#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5
|
||||
#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_ERR_BMSK 0x10
|
||||
#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_ERR_SHFT 4
|
||||
#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_AXI_WR_ERR_BMSK 0x8
|
||||
|
|
@ -36820,8 +36903,36 @@
|
|||
#define HWIO_UMCMN_R0_TRC_CTRL_2_UMAC_MISC_TRC_EVENT_SEL_SHFT 19
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_BUS_MUX_SEL_BMSK 0x78000
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_BUS_MUX_SEL_SHFT 15
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_BIT_2_BMSK 0x7fff
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_BIT_2_SHFT 0
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1
|
||||
#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0
|
||||
|
||||
#define HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x) ((x) + 0x17c)
|
||||
#define HWIO_UMCMN_R0_EVENTMASK_IX0_PHYS(x) ((x) + 0x17c)
|
||||
|
|
|
|||
|
|
@ -13,5 +13,5 @@
|
|||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#define WCSS_VERSION 2327
|
||||
|
||||
#define WCSS_VERSION 2357
|
||||
|
|
|
|||
Loading…
Reference in a new issue