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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 12:58:12 -04:00
cpufreq: qcom-hw: cleanup the driver for HW driver
Move the current code to support as per the upstream code and bring in fixes required to support the EPSS driver. Fix em_register_perf_domain as new API convention. Change-Id: I267731a89a130d1fca5b1fb25aab95430a9099c7 Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das
parent
3f05717d9f
commit
b23d5d6083
1 changed files with 102 additions and 94 deletions
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@ -3,19 +3,24 @@
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/cpufreq.h>
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#include <linux/cpu_cooling.h>
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#include <linux/energy_model.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pm_opp.h>
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#include <linux/energy_model.h>
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#include <linux/sched.h>
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#include <linux/cpu_cooling.h>
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#include <linux/slab.h>
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#define LUT_MAX_ENTRIES 40U
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#define CORE_COUNT_VAL(val) (((val) & (GENMASK(18, 16))) >> 16)
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#define LUT_SRC GENMASK(31, 30)
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#define LUT_L_VAL GENMASK(7, 0)
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#define LUT_CORE_COUNT GENMASK(18, 16)
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#define LUT_VOLT GENMASK(11, 0)
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#define LUT_ROW_SIZE 32
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#define CLK_HW_DIV 2
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@ -23,24 +28,23 @@
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(acc_count ? ((c - cpumask_first(m) + 1) * 4) : 0)
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enum {
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REG_ENABLE,
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REG_FREQ_LUT_TABLE,
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REG_VOLT_LUT_TABLE,
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REG_FREQ_LUT,
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REG_VOLT_LUT,
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REG_PERF_STATE,
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REG_CYCLE_CNTR,
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REG_ARRAY_SIZE,
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};
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static unsigned long cpu_hw_rate, xo_rate;
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static const u16 *offsets;
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static unsigned int lut_row_size = LUT_ROW_SIZE;
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static bool accumulative_counter;
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struct cpufreq_qcom {
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struct cpufreq_frequency_table *table;
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void __iomem *reg_bases[REG_ARRAY_SIZE];
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void __iomem *base;
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cpumask_t related_cpus;
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unsigned int max_cores;
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unsigned long xo_rate;
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unsigned long cpu_hw_rate;
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};
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struct cpufreq_counter {
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@ -51,40 +55,43 @@ struct cpufreq_counter {
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static const u16 cpufreq_qcom_std_offsets[REG_ARRAY_SIZE] = {
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[REG_ENABLE] = 0x0,
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[REG_FREQ_LUT_TABLE] = 0x110,
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[REG_VOLT_LUT_TABLE] = 0x114,
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[REG_FREQ_LUT] = 0x110,
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[REG_VOLT_LUT] = 0x114,
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[REG_PERF_STATE] = 0x920,
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[REG_CYCLE_CNTR] = 0x9c0,
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};
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static const u16 cpufreq_qcom_epss_std_offsets[REG_ARRAY_SIZE] = {
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[REG_ENABLE] = 0x0,
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[REG_FREQ_LUT_TABLE] = 0x100,
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[REG_VOLT_LUT_TABLE] = 0x200,
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[REG_FREQ_LUT] = 0x100,
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[REG_VOLT_LUT] = 0x200,
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[REG_PERF_STATE] = 0x320,
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[REG_CYCLE_CNTR] = 0x3c4,
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};
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static struct cpufreq_counter qcom_cpufreq_counter[NR_CPUS];
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static struct cpufreq_qcom *qcom_freq_domain_map[NR_CPUS];
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static struct cpufreq_counter qcom_cpufreq_counter[NR_CPUS];
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static u64 qcom_cpufreq_get_cpu_cycle_counter(int cpu)
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{
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struct cpufreq_counter *cpu_counter;
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struct cpufreq_qcom *cpu_domain;
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struct cpufreq_policy *policy;
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u64 cycle_counter_ret;
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unsigned long flags;
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u16 offset;
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u32 val;
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cpu_domain = qcom_freq_domain_map[cpu];
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policy = cpufreq_cpu_get_raw(cpu);
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if (!policy)
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return 0;
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cpu_counter = &qcom_cpufreq_counter[cpu];
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spin_lock_irqsave(&cpu_counter->lock, flags);
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offset = CYCLE_CNTR_OFFSET(cpu, &cpu_domain->related_cpus,
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offset = CYCLE_CNTR_OFFSET(cpu, policy->related_cpus,
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accumulative_counter);
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val = readl_relaxed_no_log(cpu_domain->reg_bases[REG_CYCLE_CNTR] +
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offset);
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val = readl_relaxed_no_log(policy->driver_data +
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offsets[REG_CYCLE_CNTR] + offset);
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if (val < cpu_counter->prev_cycle_counter) {
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/* Handle counter overflow */
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@ -106,9 +113,9 @@ static int
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qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct cpufreq_qcom *c = policy->driver_data;
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void __iomem *base = policy->driver_data;
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writel_relaxed(index, c->reg_bases[REG_PERF_STATE]);
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writel_relaxed(index, base + offsets[REG_PERF_STATE]);
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arch_set_freq_scale(policy->related_cpus,
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policy->freq_table[index].frequency,
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policy->cpuinfo.max_freq);
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@ -118,17 +125,17 @@ qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
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static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
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{
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struct cpufreq_qcom *c;
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struct cpufreq_policy *policy;
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void __iomem *base;
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unsigned int index;
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policy = cpufreq_cpu_get_raw(cpu);
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if (!policy)
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return 0;
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c = policy->driver_data;
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base = policy->driver_data;
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index = readl_relaxed(c->reg_bases[REG_PERF_STATE]);
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index = readl_relaxed(base + offsets[REG_PERF_STATE]);
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index = min(index, LUT_MAX_ENTRIES - 1);
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return policy->freq_table[index].frequency;
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@ -152,7 +159,6 @@ qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
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static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
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{
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struct em_data_callback em_cb = EM_DATA_CB(of_dev_pm_opp_get_cpu_power);
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struct cpufreq_qcom *c;
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struct device *cpu_dev;
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int ret;
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@ -176,12 +182,12 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
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if (ret <= 0)
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dev_err(cpu_dev, "OPP table is not ready\n");
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policy->fast_switch_possible = true;
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policy->freq_table = c->table;
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policy->driver_data = c;
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policy->driver_data = c->base;
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policy->fast_switch_possible = true;
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policy->dvfs_possible_from_any_cpu = true;
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em_register_perf_domain(policy->cpus, ret, &em_cb);
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dev_pm_opp_of_register_em(policy->cpus);
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return 0;
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}
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@ -236,11 +242,10 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = {
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};
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static int qcom_cpufreq_hw_read_lut(struct platform_device *pdev,
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struct cpufreq_qcom *c)
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struct cpufreq_qcom *c, u32 max_cores)
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{
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struct device *dev = &pdev->dev;
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void __iomem *base_freq, *base_volt;
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u32 data, src, lval, i, core_count, prev_cc, prev_freq, cur_freq, volt;
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u32 data, src, lval, i, core_count, prev_cc, prev_freq, freq, volt;
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unsigned long cpu;
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c->table = devm_kcalloc(dev, LUT_MAX_ENTRIES + 1,
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@ -248,57 +253,63 @@ static int qcom_cpufreq_hw_read_lut(struct platform_device *pdev,
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if (!c->table)
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return -ENOMEM;
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base_freq = c->reg_bases[REG_FREQ_LUT_TABLE];
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base_volt = c->reg_bases[REG_VOLT_LUT_TABLE];
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cpu = cpumask_first(&c->related_cpus);
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for (i = 0; i < LUT_MAX_ENTRIES; i++) {
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data = readl_relaxed(base_freq + i * lut_row_size);
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src = (data & GENMASK(31, 30)) >> 30;
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lval = data & GENMASK(7, 0);
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core_count = CORE_COUNT_VAL(data);
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data = readl_relaxed(c->base + offsets[REG_FREQ_LUT] +
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i * lut_row_size);
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src = FIELD_GET(LUT_SRC, data);
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lval = FIELD_GET(LUT_L_VAL, data);
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core_count = FIELD_GET(LUT_CORE_COUNT, data);
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data = readl_relaxed(base_volt + i * lut_row_size);
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volt = (data & GENMASK(11, 0)) * 1000;
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data = readl_relaxed(c->base + offsets[REG_VOLT_LUT] +
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i * lut_row_size);
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volt = FIELD_GET(LUT_VOLT, data) * 1000;
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if (src)
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c->table[i].frequency = c->xo_rate * lval / 1000;
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freq = xo_rate * lval / 1000;
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else
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c->table[i].frequency = c->cpu_hw_rate / 1000;
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freq = cpu_hw_rate / 1000;
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cur_freq = c->table[i].frequency;
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dev_dbg(dev, "index=%d freq=%d, core_count %d\n",
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i, c->table[i].frequency, core_count);
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if (core_count != c->max_cores)
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cur_freq = CPUFREQ_ENTRY_INVALID;
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if (freq != prev_freq && core_count == max_cores) {
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c->table[i].frequency = freq;
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dev_pm_opp_add(get_cpu_device(cpu), freq * 1000, volt);
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dev_dbg(dev, "index=%d freq=%d, core_count %d\n",
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i, c->table[i].frequency, core_count);
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} else {
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c->table[i].frequency = CPUFREQ_ENTRY_INVALID;
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}
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/*
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* Two of the same frequencies with the same core counts means
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* end of table.
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*/
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if (i > 0 && c->table[i - 1].frequency ==
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c->table[i].frequency && prev_cc == core_count) {
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if (i > 0 && prev_freq == freq && prev_cc == core_count) {
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struct cpufreq_frequency_table *prev = &c->table[i - 1];
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if (prev_freq == CPUFREQ_ENTRY_INVALID)
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if (prev_cc != max_cores) {
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prev->frequency = prev_freq;
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prev->flags = CPUFREQ_BOOST_FREQ;
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dev_pm_opp_add(get_cpu_device(cpu),
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prev_freq * 1000, volt);
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}
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break;
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}
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prev_cc = core_count;
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prev_freq = cur_freq;
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cur_freq *= 1000;
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for_each_cpu(cpu, &c->related_cpus)
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dev_pm_opp_add(get_cpu_device(cpu), cur_freq, volt);
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prev_cc = core_count;
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prev_freq = freq;
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freq *= 1000;
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}
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c->table[i].frequency = CPUFREQ_TABLE_END;
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dev_pm_opp_set_sharing_cpus(get_cpu_device(cpu), &c->related_cpus);
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return 0;
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}
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static int qcom_get_related_cpus(int index, struct cpumask *m)
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static void qcom_get_related_cpus(int index, struct cpumask *m)
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{
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struct device_node *cpu_np;
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struct of_phandle_args args;
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@ -318,25 +329,17 @@ static int qcom_get_related_cpus(int index, struct cpumask *m)
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if (index == args.args[0])
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cpumask_set_cpu(cpu, m);
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}
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return 0;
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}
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static int qcom_cpu_resources_init(struct platform_device *pdev,
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unsigned int cpu, int index,
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unsigned int max_cores,
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unsigned long xo_rate,
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unsigned long cpu_hw_rate)
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unsigned int max_cores)
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{
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struct cpufreq_qcom *c;
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struct resource *res;
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struct device *dev = &pdev->dev;
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const u16 *offsets;
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int ret, i, cpu_r;
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void __iomem *base;
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if (qcom_freq_domain_map[cpu])
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return 0;
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int ret, cpu_r;
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c = devm_kzalloc(dev, sizeof(*c), GFP_KERNEL);
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if (!c)
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@ -351,12 +354,9 @@ static int qcom_cpu_resources_init(struct platform_device *pdev,
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if (IS_ERR(base))
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return PTR_ERR(base);
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for (i = REG_ENABLE; i < REG_ARRAY_SIZE; i++)
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c->reg_bases[i] = base + offsets[i];
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if (!of_property_read_bool(dev->of_node, "qcom,skip-enable-check")) {
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/* HW should be in enabled state to proceed */
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if (!(readl_relaxed(c->reg_bases[REG_ENABLE]) & 0x1)) {
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if (!(readl_relaxed(base + offsets[REG_ENABLE]) & 0x1)) {
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dev_err(dev, "Domain-%d cpufreq hardware not enabled\n",
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index);
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return -ENODEV;
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@ -364,22 +364,16 @@ static int qcom_cpu_resources_init(struct platform_device *pdev,
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}
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accumulative_counter = !of_property_read_bool(dev->of_node,
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"qcom,no-accumulative-counter");
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"qcom,no-accumulative-counter");
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c->base = base;
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ret = qcom_get_related_cpus(index, &c->related_cpus);
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if (ret) {
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qcom_get_related_cpus(index, &c->related_cpus);
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if (!cpumask_weight(&c->related_cpus)) {
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dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
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return ret;
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return -ENONET;
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}
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c->max_cores = max_cores;
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if (!c->max_cores)
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return -ENOENT;
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c->xo_rate = xo_rate;
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c->cpu_hw_rate = cpu_hw_rate;
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ret = qcom_cpufreq_hw_read_lut(pdev, c);
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ret = qcom_cpufreq_hw_read_lut(pdev, c, max_cores);
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if (ret) {
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dev_err(dev, "Domain-%d failed to read LUT\n", index);
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return ret;
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@ -397,7 +391,6 @@ static int qcom_resources_init(struct platform_device *pdev)
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struct of_phandle_args args;
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struct clk *clk;
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unsigned int cpu;
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unsigned long xo_rate, cpu_hw_rate;
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int ret;
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clk = devm_clk_get(&pdev->dev, "xo");
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@ -405,16 +398,14 @@ static int qcom_resources_init(struct platform_device *pdev)
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return PTR_ERR(clk);
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xo_rate = clk_get_rate(clk);
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devm_clk_put(&pdev->dev, clk);
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clk_put(clk);
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clk = devm_clk_get(&pdev->dev, "alternate");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
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devm_clk_put(&pdev->dev, clk);
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clk_put(clk);
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of_property_read_u32(pdev->dev.of_node, "qcom,lut-row-size",
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&lut_row_size);
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@ -428,13 +419,17 @@ static int qcom_resources_init(struct platform_device *pdev)
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}
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ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
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"#freq-domain-cells", 0, &args);
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if (ret < 0)
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"#freq-domain-cells", 0,
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&args);
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of_node_put(cpu_np);
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if (ret)
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return ret;
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if (qcom_freq_domain_map[cpu])
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continue;
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ret = qcom_cpu_resources_init(pdev, cpu, args.args[0],
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args.args[1], xo_rate,
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cpu_hw_rate);
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args.args[1]);
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if (ret)
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return ret;
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}
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@ -471,12 +466,17 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
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return rc;
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}
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dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
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of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
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dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
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return 0;
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}
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static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
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{
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return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
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}
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static const struct of_device_id qcom_cpufreq_hw_match[] = {
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{ .compatible = "qcom,cpufreq-hw", .data = &cpufreq_qcom_std_offsets },
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{ .compatible = "qcom,cpufreq-hw-epss",
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@ -486,6 +486,7 @@ static const struct of_device_id qcom_cpufreq_hw_match[] = {
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static struct platform_driver qcom_cpufreq_hw_driver = {
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.probe = qcom_cpufreq_hw_driver_probe,
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.remove = qcom_cpufreq_hw_driver_remove,
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.driver = {
|
||||
.name = "qcom-cpufreq-hw",
|
||||
.of_match_table = qcom_cpufreq_hw_match,
|
||||
|
|
@ -498,4 +499,11 @@ static int __init qcom_cpufreq_hw_init(void)
|
|||
}
|
||||
subsys_initcall(qcom_cpufreq_hw_init);
|
||||
|
||||
MODULE_DESCRIPTION("QCOM firmware-based CPU Frequency driver");
|
||||
static void __exit qcom_cpufreq_hw_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&qcom_cpufreq_hw_driver);
|
||||
}
|
||||
module_exit(qcom_cpufreq_hw_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
Loading…
Reference in a new issue